1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_lrc_reg.h" 8 #include "intel_sseu.h" 9 10 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, 11 u8 max_subslices, u8 max_eus_per_subslice) 12 { 13 sseu->max_slices = max_slices; 14 sseu->max_subslices = max_subslices; 15 sseu->max_eus_per_subslice = max_eus_per_subslice; 16 17 sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices); 18 GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE); 19 sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); 20 GEM_BUG_ON(sseu->eu_stride > GEN_MAX_EU_STRIDE); 21 } 22 23 unsigned int 24 intel_sseu_subslice_total(const struct sseu_dev_info *sseu) 25 { 26 unsigned int i, total = 0; 27 28 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) 29 total += hweight8(sseu->subslice_mask[i]); 30 31 return total; 32 } 33 34 u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice) 35 { 36 int i, offset = slice * sseu->ss_stride; 37 u32 mask = 0; 38 39 GEM_BUG_ON(slice >= sseu->max_slices); 40 41 for (i = 0; i < sseu->ss_stride; i++) 42 mask |= (u32)sseu->subslice_mask[offset + i] << 43 i * BITS_PER_BYTE; 44 45 return mask; 46 } 47 48 void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, 49 u32 ss_mask) 50 { 51 int offset = slice * sseu->ss_stride; 52 53 memcpy(&sseu->subslice_mask[offset], &ss_mask, sseu->ss_stride); 54 } 55 56 unsigned int 57 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice) 58 { 59 return hweight32(intel_sseu_get_subslices(sseu, slice)); 60 } 61 62 static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, 63 int subslice) 64 { 65 int slice_stride = sseu->max_subslices * sseu->eu_stride; 66 67 return slice * slice_stride + subslice * sseu->eu_stride; 68 } 69 70 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, 71 int subslice) 72 { 73 int i, offset = sseu_eu_idx(sseu, slice, subslice); 74 u16 eu_mask = 0; 75 76 for (i = 0; i < sseu->eu_stride; i++) 77 eu_mask |= 78 ((u16)sseu->eu_mask[offset + i]) << (i * BITS_PER_BYTE); 79 80 return eu_mask; 81 } 82 83 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, 84 u16 eu_mask) 85 { 86 int i, offset = sseu_eu_idx(sseu, slice, subslice); 87 88 for (i = 0; i < sseu->eu_stride; i++) 89 sseu->eu_mask[offset + i] = 90 (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; 91 } 92 93 static u16 compute_eu_total(const struct sseu_dev_info *sseu) 94 { 95 u16 i, total = 0; 96 97 for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++) 98 total += hweight8(sseu->eu_mask[i]); 99 100 return total; 101 } 102 103 static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, 104 u8 s_en, u32 ss_en, u16 eu_en) 105 { 106 int s, ss; 107 108 /* ss_en represents entire subslice mask across all slices */ 109 GEM_BUG_ON(sseu->max_slices * sseu->max_subslices > 110 sizeof(ss_en) * BITS_PER_BYTE); 111 112 for (s = 0; s < sseu->max_slices; s++) { 113 if ((s_en & BIT(s)) == 0) 114 continue; 115 116 sseu->slice_mask |= BIT(s); 117 118 intel_sseu_set_subslices(sseu, s, ss_en); 119 120 for (ss = 0; ss < sseu->max_subslices; ss++) 121 if (intel_sseu_has_subslice(sseu, s, ss)) 122 sseu_set_eus(sseu, s, ss, eu_en); 123 } 124 sseu->eu_per_subslice = hweight16(eu_en); 125 sseu->eu_total = compute_eu_total(sseu); 126 } 127 128 static void gen12_sseu_info_init(struct intel_gt *gt) 129 { 130 struct sseu_dev_info *sseu = >->info.sseu; 131 struct intel_uncore *uncore = gt->uncore; 132 u32 dss_en; 133 u16 eu_en = 0; 134 u8 eu_en_fuse; 135 u8 s_en; 136 int eu; 137 138 /* 139 * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS. 140 * Instead of splitting these, provide userspace with an array 141 * of DSS to more closely represent the hardware resource. 142 */ 143 intel_sseu_set_info(sseu, 1, 6, 16); 144 145 s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & 146 GEN11_GT_S_ENA_MASK; 147 148 dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE); 149 150 /* one bit per pair of EUs */ 151 eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & 152 GEN11_EU_DIS_MASK); 153 for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) 154 if (eu_en_fuse & BIT(eu)) 155 eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); 156 157 gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en); 158 159 /* TGL only supports slice-level power gating */ 160 sseu->has_slice_pg = 1; 161 } 162 163 static void gen11_sseu_info_init(struct intel_gt *gt) 164 { 165 struct sseu_dev_info *sseu = >->info.sseu; 166 struct intel_uncore *uncore = gt->uncore; 167 u32 ss_en; 168 u8 eu_en; 169 u8 s_en; 170 171 if (IS_JSL_EHL(gt->i915)) 172 intel_sseu_set_info(sseu, 1, 4, 8); 173 else 174 intel_sseu_set_info(sseu, 1, 8, 8); 175 176 s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & 177 GEN11_GT_S_ENA_MASK; 178 ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE); 179 180 eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & 181 GEN11_EU_DIS_MASK); 182 183 gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en); 184 185 /* ICL has no power gating restrictions. */ 186 sseu->has_slice_pg = 1; 187 sseu->has_subslice_pg = 1; 188 sseu->has_eu_pg = 1; 189 } 190 191 static void gen10_sseu_info_init(struct intel_gt *gt) 192 { 193 struct intel_uncore *uncore = gt->uncore; 194 struct sseu_dev_info *sseu = >->info.sseu; 195 const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); 196 const int eu_mask = 0xff; 197 u32 subslice_mask, eu_en; 198 int s, ss; 199 200 intel_sseu_set_info(sseu, 6, 4, 8); 201 202 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> 203 GEN10_F2_S_ENA_SHIFT; 204 205 /* Slice0 */ 206 eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0); 207 for (ss = 0; ss < sseu->max_subslices; ss++) 208 sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); 209 /* Slice1 */ 210 sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); 211 eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1); 212 sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); 213 /* Slice2 */ 214 sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); 215 sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); 216 /* Slice3 */ 217 sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); 218 eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2); 219 sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); 220 /* Slice4 */ 221 sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); 222 sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); 223 /* Slice5 */ 224 sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); 225 eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3); 226 sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); 227 228 subslice_mask = (1 << 4) - 1; 229 subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> 230 GEN10_F2_SS_DIS_SHIFT); 231 232 for (s = 0; s < sseu->max_slices; s++) { 233 u32 subslice_mask_with_eus = subslice_mask; 234 235 for (ss = 0; ss < sseu->max_subslices; ss++) { 236 if (sseu_get_eus(sseu, s, ss) == 0) 237 subslice_mask_with_eus &= ~BIT(ss); 238 } 239 240 /* 241 * Slice0 can have up to 3 subslices, but there are only 2 in 242 * slice1/2. 243 */ 244 intel_sseu_set_subslices(sseu, s, s == 0 ? 245 subslice_mask_with_eus : 246 subslice_mask_with_eus & 0x3); 247 } 248 249 sseu->eu_total = compute_eu_total(sseu); 250 251 /* 252 * CNL is expected to always have a uniform distribution 253 * of EU across subslices with the exception that any one 254 * EU in any one subslice may be fused off for die 255 * recovery. 256 */ 257 sseu->eu_per_subslice = 258 intel_sseu_subslice_total(sseu) ? 259 DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) : 260 0; 261 262 /* No restrictions on Power Gating */ 263 sseu->has_slice_pg = 1; 264 sseu->has_subslice_pg = 1; 265 sseu->has_eu_pg = 1; 266 } 267 268 static void cherryview_sseu_info_init(struct intel_gt *gt) 269 { 270 struct sseu_dev_info *sseu = >->info.sseu; 271 u32 fuse; 272 u8 subslice_mask = 0; 273 274 fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT); 275 276 sseu->slice_mask = BIT(0); 277 intel_sseu_set_info(sseu, 1, 2, 8); 278 279 if (!(fuse & CHV_FGT_DISABLE_SS0)) { 280 u8 disabled_mask = 281 ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> 282 CHV_FGT_EU_DIS_SS0_R0_SHIFT) | 283 (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> 284 CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); 285 286 subslice_mask |= BIT(0); 287 sseu_set_eus(sseu, 0, 0, ~disabled_mask); 288 } 289 290 if (!(fuse & CHV_FGT_DISABLE_SS1)) { 291 u8 disabled_mask = 292 ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> 293 CHV_FGT_EU_DIS_SS1_R0_SHIFT) | 294 (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> 295 CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); 296 297 subslice_mask |= BIT(1); 298 sseu_set_eus(sseu, 0, 1, ~disabled_mask); 299 } 300 301 intel_sseu_set_subslices(sseu, 0, subslice_mask); 302 303 sseu->eu_total = compute_eu_total(sseu); 304 305 /* 306 * CHV expected to always have a uniform distribution of EU 307 * across subslices. 308 */ 309 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 310 sseu->eu_total / 311 intel_sseu_subslice_total(sseu) : 312 0; 313 /* 314 * CHV supports subslice power gating on devices with more than 315 * one subslice, and supports EU power gating on devices with 316 * more than one EU pair per subslice. 317 */ 318 sseu->has_slice_pg = 0; 319 sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; 320 sseu->has_eu_pg = (sseu->eu_per_subslice > 2); 321 } 322 323 static void gen9_sseu_info_init(struct intel_gt *gt) 324 { 325 struct drm_i915_private *i915 = gt->i915; 326 struct intel_device_info *info = mkwrite_device_info(i915); 327 struct sseu_dev_info *sseu = >->info.sseu; 328 struct intel_uncore *uncore = gt->uncore; 329 u32 fuse2, eu_disable, subslice_mask; 330 const u8 eu_mask = 0xff; 331 int s, ss; 332 333 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); 334 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 335 336 /* BXT has a single slice and at most 3 subslices. */ 337 intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3, 338 IS_GEN9_LP(i915) ? 3 : 4, 8); 339 340 /* 341 * The subslice disable field is global, i.e. it applies 342 * to each of the enabled slices. 343 */ 344 subslice_mask = (1 << sseu->max_subslices) - 1; 345 subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> 346 GEN9_F2_SS_DIS_SHIFT); 347 348 /* 349 * Iterate through enabled slices and subslices to 350 * count the total enabled EU. 351 */ 352 for (s = 0; s < sseu->max_slices; s++) { 353 if (!(sseu->slice_mask & BIT(s))) 354 /* skip disabled slice */ 355 continue; 356 357 intel_sseu_set_subslices(sseu, s, subslice_mask); 358 359 eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s)); 360 for (ss = 0; ss < sseu->max_subslices; ss++) { 361 int eu_per_ss; 362 u8 eu_disabled_mask; 363 364 if (!intel_sseu_has_subslice(sseu, s, ss)) 365 /* skip disabled subslice */ 366 continue; 367 368 eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; 369 370 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); 371 372 eu_per_ss = sseu->max_eus_per_subslice - 373 hweight8(eu_disabled_mask); 374 375 /* 376 * Record which subslice(s) has(have) 7 EUs. we 377 * can tune the hash used to spread work among 378 * subslices if they are unbalanced. 379 */ 380 if (eu_per_ss == 7) 381 sseu->subslice_7eu[s] |= BIT(ss); 382 } 383 } 384 385 sseu->eu_total = compute_eu_total(sseu); 386 387 /* 388 * SKL is expected to always have a uniform distribution 389 * of EU across subslices with the exception that any one 390 * EU in any one subslice may be fused off for die 391 * recovery. BXT is expected to be perfectly uniform in EU 392 * distribution. 393 */ 394 sseu->eu_per_subslice = 395 intel_sseu_subslice_total(sseu) ? 396 DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) : 397 0; 398 399 /* 400 * SKL+ supports slice power gating on devices with more than 401 * one slice, and supports EU power gating on devices with 402 * more than one EU pair per subslice. BXT+ supports subslice 403 * power gating on devices with more than one subslice, and 404 * supports EU power gating on devices with more than one EU 405 * pair per subslice. 406 */ 407 sseu->has_slice_pg = 408 !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1; 409 sseu->has_subslice_pg = 410 IS_GEN9_LP(i915) && intel_sseu_subslice_total(sseu) > 1; 411 sseu->has_eu_pg = sseu->eu_per_subslice > 2; 412 413 if (IS_GEN9_LP(i915)) { 414 #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) 415 info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; 416 417 sseu->min_eu_in_pool = 0; 418 if (info->has_pooled_eu) { 419 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) 420 sseu->min_eu_in_pool = 3; 421 else if (IS_SS_DISABLED(1)) 422 sseu->min_eu_in_pool = 6; 423 else 424 sseu->min_eu_in_pool = 9; 425 } 426 #undef IS_SS_DISABLED 427 } 428 } 429 430 static void bdw_sseu_info_init(struct intel_gt *gt) 431 { 432 struct sseu_dev_info *sseu = >->info.sseu; 433 struct intel_uncore *uncore = gt->uncore; 434 int s, ss; 435 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ 436 u32 eu_disable0, eu_disable1, eu_disable2; 437 438 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); 439 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 440 intel_sseu_set_info(sseu, 3, 3, 8); 441 442 /* 443 * The subslice disable field is global, i.e. it applies 444 * to each of the enabled slices. 445 */ 446 subslice_mask = GENMASK(sseu->max_subslices - 1, 0); 447 subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> 448 GEN8_F2_SS_DIS_SHIFT); 449 eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0); 450 eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1); 451 eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2); 452 eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK; 453 eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) | 454 ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) << 455 (32 - GEN8_EU_DIS0_S1_SHIFT)); 456 eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) | 457 ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) << 458 (32 - GEN8_EU_DIS1_S2_SHIFT)); 459 460 /* 461 * Iterate through enabled slices and subslices to 462 * count the total enabled EU. 463 */ 464 for (s = 0; s < sseu->max_slices; s++) { 465 if (!(sseu->slice_mask & BIT(s))) 466 /* skip disabled slice */ 467 continue; 468 469 intel_sseu_set_subslices(sseu, s, subslice_mask); 470 471 for (ss = 0; ss < sseu->max_subslices; ss++) { 472 u8 eu_disabled_mask; 473 u32 n_disabled; 474 475 if (!intel_sseu_has_subslice(sseu, s, ss)) 476 /* skip disabled subslice */ 477 continue; 478 479 eu_disabled_mask = 480 eu_disable[s] >> (ss * sseu->max_eus_per_subslice); 481 482 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); 483 484 n_disabled = hweight8(eu_disabled_mask); 485 486 /* 487 * Record which subslices have 7 EUs. 488 */ 489 if (sseu->max_eus_per_subslice - n_disabled == 7) 490 sseu->subslice_7eu[s] |= 1 << ss; 491 } 492 } 493 494 sseu->eu_total = compute_eu_total(sseu); 495 496 /* 497 * BDW is expected to always have a uniform distribution of EU across 498 * subslices with the exception that any one EU in any one subslice may 499 * be fused off for die recovery. 500 */ 501 sseu->eu_per_subslice = 502 intel_sseu_subslice_total(sseu) ? 503 DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) : 504 0; 505 506 /* 507 * BDW supports slice power gating on devices with more than 508 * one slice. 509 */ 510 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; 511 sseu->has_subslice_pg = 0; 512 sseu->has_eu_pg = 0; 513 } 514 515 static void hsw_sseu_info_init(struct intel_gt *gt) 516 { 517 struct drm_i915_private *i915 = gt->i915; 518 struct sseu_dev_info *sseu = >->info.sseu; 519 u32 fuse1; 520 u8 subslice_mask = 0; 521 int s, ss; 522 523 /* 524 * There isn't a register to tell us how many slices/subslices. We 525 * work off the PCI-ids here. 526 */ 527 switch (INTEL_INFO(i915)->gt) { 528 default: 529 MISSING_CASE(INTEL_INFO(i915)->gt); 530 fallthrough; 531 case 1: 532 sseu->slice_mask = BIT(0); 533 subslice_mask = BIT(0); 534 break; 535 case 2: 536 sseu->slice_mask = BIT(0); 537 subslice_mask = BIT(0) | BIT(1); 538 break; 539 case 3: 540 sseu->slice_mask = BIT(0) | BIT(1); 541 subslice_mask = BIT(0) | BIT(1); 542 break; 543 } 544 545 fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1); 546 switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { 547 default: 548 MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >> 549 HSW_F1_EU_DIS_SHIFT); 550 fallthrough; 551 case HSW_F1_EU_DIS_10EUS: 552 sseu->eu_per_subslice = 10; 553 break; 554 case HSW_F1_EU_DIS_8EUS: 555 sseu->eu_per_subslice = 8; 556 break; 557 case HSW_F1_EU_DIS_6EUS: 558 sseu->eu_per_subslice = 6; 559 break; 560 } 561 562 intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), 563 hweight8(subslice_mask), 564 sseu->eu_per_subslice); 565 566 for (s = 0; s < sseu->max_slices; s++) { 567 intel_sseu_set_subslices(sseu, s, subslice_mask); 568 569 for (ss = 0; ss < sseu->max_subslices; ss++) { 570 sseu_set_eus(sseu, s, ss, 571 (1UL << sseu->eu_per_subslice) - 1); 572 } 573 } 574 575 sseu->eu_total = compute_eu_total(sseu); 576 577 /* No powergating for you. */ 578 sseu->has_slice_pg = 0; 579 sseu->has_subslice_pg = 0; 580 sseu->has_eu_pg = 0; 581 } 582 583 void intel_sseu_info_init(struct intel_gt *gt) 584 { 585 struct drm_i915_private *i915 = gt->i915; 586 587 if (IS_HASWELL(i915)) 588 hsw_sseu_info_init(gt); 589 else if (IS_CHERRYVIEW(i915)) 590 cherryview_sseu_info_init(gt); 591 else if (IS_BROADWELL(i915)) 592 bdw_sseu_info_init(gt); 593 else if (IS_GEN(i915, 9)) 594 gen9_sseu_info_init(gt); 595 else if (IS_GEN(i915, 10)) 596 gen10_sseu_info_init(gt); 597 else if (IS_GEN(i915, 11)) 598 gen11_sseu_info_init(gt); 599 else if (INTEL_GEN(i915) >= 12) 600 gen12_sseu_info_init(gt); 601 } 602 603 u32 intel_sseu_make_rpcs(struct intel_gt *gt, 604 const struct intel_sseu *req_sseu) 605 { 606 struct drm_i915_private *i915 = gt->i915; 607 const struct sseu_dev_info *sseu = >->info.sseu; 608 bool subslice_pg = sseu->has_subslice_pg; 609 u8 slices, subslices; 610 u32 rpcs = 0; 611 612 /* 613 * No explicit RPCS request is needed to ensure full 614 * slice/subslice/EU enablement prior to Gen9. 615 */ 616 if (INTEL_GEN(i915) < 9) 617 return 0; 618 619 /* 620 * If i915/perf is active, we want a stable powergating configuration 621 * on the system. Use the configuration pinned by i915/perf. 622 */ 623 if (i915->perf.exclusive_stream) 624 req_sseu = &i915->perf.sseu; 625 626 slices = hweight8(req_sseu->slice_mask); 627 subslices = hweight8(req_sseu->subslice_mask); 628 629 /* 630 * Since the SScount bitfield in GEN8_R_PWR_CLK_STATE is only three bits 631 * wide and Icelake has up to eight subslices, specfial programming is 632 * needed in order to correctly enable all subslices. 633 * 634 * According to documentation software must consider the configuration 635 * as 2x4x8 and hardware will translate this to 1x8x8. 636 * 637 * Furthemore, even though SScount is three bits, maximum documented 638 * value for it is four. From this some rules/restrictions follow: 639 * 640 * 1. 641 * If enabled subslice count is greater than four, two whole slices must 642 * be enabled instead. 643 * 644 * 2. 645 * When more than one slice is enabled, hardware ignores the subslice 646 * count altogether. 647 * 648 * From these restrictions it follows that it is not possible to enable 649 * a count of subslices between the SScount maximum of four restriction, 650 * and the maximum available number on a particular SKU. Either all 651 * subslices are enabled, or a count between one and four on the first 652 * slice. 653 */ 654 if (IS_GEN(i915, 11) && 655 slices == 1 && 656 subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) { 657 GEM_BUG_ON(subslices & 1); 658 659 subslice_pg = false; 660 slices *= 2; 661 } 662 663 /* 664 * Starting in Gen9, render power gating can leave 665 * slice/subslice/EU in a partially enabled state. We 666 * must make an explicit request through RPCS for full 667 * enablement. 668 */ 669 if (sseu->has_slice_pg) { 670 u32 mask, val = slices; 671 672 if (INTEL_GEN(i915) >= 11) { 673 mask = GEN11_RPCS_S_CNT_MASK; 674 val <<= GEN11_RPCS_S_CNT_SHIFT; 675 } else { 676 mask = GEN8_RPCS_S_CNT_MASK; 677 val <<= GEN8_RPCS_S_CNT_SHIFT; 678 } 679 680 GEM_BUG_ON(val & ~mask); 681 val &= mask; 682 683 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_S_CNT_ENABLE | val; 684 } 685 686 if (subslice_pg) { 687 u32 val = subslices; 688 689 val <<= GEN8_RPCS_SS_CNT_SHIFT; 690 691 GEM_BUG_ON(val & ~GEN8_RPCS_SS_CNT_MASK); 692 val &= GEN8_RPCS_SS_CNT_MASK; 693 694 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val; 695 } 696 697 if (sseu->has_eu_pg) { 698 u32 val; 699 700 val = req_sseu->min_eus_per_subslice << GEN8_RPCS_EU_MIN_SHIFT; 701 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK); 702 val &= GEN8_RPCS_EU_MIN_MASK; 703 704 rpcs |= val; 705 706 val = req_sseu->max_eus_per_subslice << GEN8_RPCS_EU_MAX_SHIFT; 707 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK); 708 val &= GEN8_RPCS_EU_MAX_MASK; 709 710 rpcs |= val; 711 712 rpcs |= GEN8_RPCS_ENABLE; 713 } 714 715 return rpcs; 716 } 717 718 void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) 719 { 720 int s; 721 722 drm_printf(p, "slice total: %u, mask=%04x\n", 723 hweight8(sseu->slice_mask), sseu->slice_mask); 724 drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); 725 for (s = 0; s < sseu->max_slices; s++) { 726 drm_printf(p, "slice%d: %u subslices, mask=%08x\n", 727 s, intel_sseu_subslices_per_slice(sseu, s), 728 intel_sseu_get_subslices(sseu, s)); 729 } 730 drm_printf(p, "EU total: %u\n", sseu->eu_total); 731 drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); 732 drm_printf(p, "has slice power gating: %s\n", 733 yesno(sseu->has_slice_pg)); 734 drm_printf(p, "has subslice power gating: %s\n", 735 yesno(sseu->has_subslice_pg)); 736 drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); 737 } 738 739 void intel_sseu_print_topology(const struct sseu_dev_info *sseu, 740 struct drm_printer *p) 741 { 742 int s, ss; 743 744 if (sseu->max_slices == 0) { 745 drm_printf(p, "Unavailable\n"); 746 return; 747 } 748 749 for (s = 0; s < sseu->max_slices; s++) { 750 drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n", 751 s, intel_sseu_subslices_per_slice(sseu, s), 752 intel_sseu_get_subslices(sseu, s)); 753 754 for (ss = 0; ss < sseu->max_subslices; ss++) { 755 u16 enabled_eus = sseu_get_eus(sseu, s, ss); 756 757 drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", 758 ss, hweight16(enabled_eus), enabled_eus); 759 } 760 } 761 } 762