1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef INTEL_RPS_TYPES_H
7 #define INTEL_RPS_TYPES_H
8 
9 #include <linux/atomic.h>
10 #include <linux/ktime.h>
11 #include <linux/mutex.h>
12 #include <linux/types.h>
13 #include <linux/workqueue.h>
14 
15 struct intel_ips {
16 	u64 last_count1;
17 	unsigned long last_time1;
18 	unsigned long chipset_power;
19 	u64 last_count2;
20 	u64 last_time2;
21 	unsigned long gfx_power;
22 	u8 corr;
23 
24 	int c, m;
25 };
26 
27 struct intel_rps_ei {
28 	ktime_t ktime;
29 	u32 render_c0;
30 	u32 media_c0;
31 };
32 
33 enum {
34 	INTEL_RPS_ENABLED = 0,
35 	INTEL_RPS_ACTIVE,
36 	INTEL_RPS_INTERRUPTS,
37 	INTEL_RPS_TIMER,
38 };
39 
40 /**
41  * struct intel_rps_freq_caps - rps freq capabilities
42  * @rp0_freq: non-overclocked max frequency
43  * @rp1_freq: "less than" RP0 power/freqency
44  * @min_freq: aka RPn, minimum frequency
45  *
46  * Freq caps exposed by HW, values are in "hw units" and intel_gpu_freq()
47  * should be used to convert to MHz
48  */
49 struct intel_rps_freq_caps {
50 	u8 rp0_freq;
51 	u8 rp1_freq;
52 	u8 min_freq;
53 };
54 
55 struct intel_rps {
56 	struct mutex lock; /* protects enabling and the worker */
57 
58 	/*
59 	 * work, interrupts_enabled and pm_iir are protected by
60 	 * dev_priv->irq_lock
61 	 */
62 	struct timer_list timer;
63 	struct work_struct work;
64 	unsigned long flags;
65 
66 	ktime_t pm_timestamp;
67 	u32 pm_interval;
68 	u32 pm_iir;
69 
70 	/* PM interrupt bits that should never be masked */
71 	u32 pm_intrmsk_mbz;
72 	u32 pm_events;
73 
74 	/* Frequencies are stored in potentially platform dependent multiples.
75 	 * In other words, *_freq needs to be multiplied by X to be interesting.
76 	 * Soft limits are those which are used for the dynamic reclocking done
77 	 * by the driver (raise frequencies under heavy loads, and lower for
78 	 * lighter loads). Hard limits are those imposed by the hardware.
79 	 *
80 	 * A distinction is made for overclocking, which is never enabled by
81 	 * default, and is considered to be above the hard limit if it's
82 	 * possible at all.
83 	 */
84 	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
85 	u8 last_freq;		/* Last SWREQ frequency */
86 	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
87 	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
88 	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
89 	u8 min_freq;		/* AKA RPn. Minimum frequency */
90 	u8 boost_freq;		/* Frequency to request when wait boosting */
91 	u8 idle_freq;		/* Frequency to request when we are idle */
92 	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
93 	u8 rp1_freq;		/* "less than" RP0 power/freqency */
94 	u8 rp0_freq;		/* Non-overclocked max frequency. */
95 	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
96 
97 	int last_adj;
98 
99 	struct {
100 		struct mutex mutex;
101 
102 		enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
103 		unsigned int interactive;
104 
105 		u8 up_threshold; /* Current %busy required to uplock */
106 		u8 down_threshold; /* Current %busy required to downclock */
107 	} power;
108 
109 	atomic_t num_waiters;
110 	unsigned int boosts;
111 
112 	/* manual wa residency calculations */
113 	struct intel_rps_ei ei;
114 	struct intel_ips ips;
115 };
116 
117 #endif /* INTEL_RPS_TYPES_H */
118