1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2019 Intel Corporation 5 */ 6 7 #ifndef INTEL_RPS_TYPES_H 8 #define INTEL_RPS_TYPES_H 9 10 #include <linux/atomic.h> 11 #include <linux/ktime.h> 12 #include <linux/mutex.h> 13 #include <linux/types.h> 14 #include <linux/workqueue.h> 15 16 struct intel_ips { 17 u64 last_count1; 18 unsigned long last_time1; 19 unsigned long chipset_power; 20 u64 last_count2; 21 u64 last_time2; 22 unsigned long gfx_power; 23 u8 corr; 24 25 int c, m; 26 }; 27 28 struct intel_rps_ei { 29 ktime_t ktime; 30 u32 render_c0; 31 u32 media_c0; 32 }; 33 34 struct intel_rps { 35 struct mutex lock; /* protects enabling and the worker */ 36 37 /* 38 * work, interrupts_enabled and pm_iir are protected by 39 * dev_priv->irq_lock 40 */ 41 struct work_struct work; 42 bool enabled; 43 bool active; 44 u32 pm_iir; 45 46 /* PM interrupt bits that should never be masked */ 47 u32 pm_intrmsk_mbz; 48 u32 pm_events; 49 50 /* Frequencies are stored in potentially platform dependent multiples. 51 * In other words, *_freq needs to be multiplied by X to be interesting. 52 * Soft limits are those which are used for the dynamic reclocking done 53 * by the driver (raise frequencies under heavy loads, and lower for 54 * lighter loads). Hard limits are those imposed by the hardware. 55 * 56 * A distinction is made for overclocking, which is never enabled by 57 * default, and is considered to be above the hard limit if it's 58 * possible at all. 59 */ 60 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 61 u8 last_freq; /* Last SWREQ frequency */ 62 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 63 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 64 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 65 u8 min_freq; /* AKA RPn. Minimum frequency */ 66 u8 boost_freq; /* Frequency to request when wait boosting */ 67 u8 idle_freq; /* Frequency to request when we are idle */ 68 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 69 u8 rp1_freq; /* "less than" RP0 power/freqency */ 70 u8 rp0_freq; /* Non-overclocked max frequency. */ 71 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ 72 73 int last_adj; 74 75 struct { 76 struct mutex mutex; 77 78 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode; 79 unsigned int interactive; 80 81 u8 up_threshold; /* Current %busy required to uplock */ 82 u8 down_threshold; /* Current %busy required to downclock */ 83 } power; 84 85 atomic_t num_waiters; 86 atomic_t boosts; 87 88 /* manual wa residency calculations */ 89 struct intel_rps_ei ei; 90 struct intel_ips ips; 91 }; 92 93 #endif /* INTEL_RPS_TYPES_H */ 94