1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <drm/i915_drm.h> 7 8 #include "i915_drv.h" 9 #include "intel_breadcrumbs.h" 10 #include "intel_gt.h" 11 #include "intel_gt_clock_utils.h" 12 #include "intel_gt_irq.h" 13 #include "intel_gt_pm_irq.h" 14 #include "intel_pcode.h" 15 #include "intel_rps.h" 16 #include "vlv_sideband.h" 17 #include "../../../platform/x86/intel_ips.h" 18 19 #define BUSY_MAX_EI 20u /* ms */ 20 21 /* 22 * Lock protecting IPS related data structures 23 */ 24 static DEFINE_SPINLOCK(mchdev_lock); 25 26 static struct intel_gt *rps_to_gt(struct intel_rps *rps) 27 { 28 return container_of(rps, struct intel_gt, rps); 29 } 30 31 static struct drm_i915_private *rps_to_i915(struct intel_rps *rps) 32 { 33 return rps_to_gt(rps)->i915; 34 } 35 36 static struct intel_uncore *rps_to_uncore(struct intel_rps *rps) 37 { 38 return rps_to_gt(rps)->uncore; 39 } 40 41 static struct intel_guc_slpc *rps_to_slpc(struct intel_rps *rps) 42 { 43 struct intel_gt *gt = rps_to_gt(rps); 44 45 return >->uc.guc.slpc; 46 } 47 48 static bool rps_uses_slpc(struct intel_rps *rps) 49 { 50 struct intel_gt *gt = rps_to_gt(rps); 51 52 return intel_uc_uses_guc_slpc(>->uc); 53 } 54 55 static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask) 56 { 57 return mask & ~rps->pm_intrmsk_mbz; 58 } 59 60 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) 61 { 62 intel_uncore_write_fw(uncore, reg, val); 63 } 64 65 static void rps_timer(struct timer_list *t) 66 { 67 struct intel_rps *rps = from_timer(rps, t, timer); 68 struct intel_engine_cs *engine; 69 ktime_t dt, last, timestamp; 70 enum intel_engine_id id; 71 s64 max_busy[3] = {}; 72 73 timestamp = 0; 74 for_each_engine(engine, rps_to_gt(rps), id) { 75 s64 busy; 76 int i; 77 78 dt = intel_engine_get_busy_time(engine, ×tamp); 79 last = engine->stats.rps; 80 engine->stats.rps = dt; 81 82 busy = ktime_to_ns(ktime_sub(dt, last)); 83 for (i = 0; i < ARRAY_SIZE(max_busy); i++) { 84 if (busy > max_busy[i]) 85 swap(busy, max_busy[i]); 86 } 87 } 88 last = rps->pm_timestamp; 89 rps->pm_timestamp = timestamp; 90 91 if (intel_rps_is_active(rps)) { 92 s64 busy; 93 int i; 94 95 dt = ktime_sub(timestamp, last); 96 97 /* 98 * Our goal is to evaluate each engine independently, so we run 99 * at the lowest clocks required to sustain the heaviest 100 * workload. However, a task may be split into sequential 101 * dependent operations across a set of engines, such that 102 * the independent contributions do not account for high load, 103 * but overall the task is GPU bound. For example, consider 104 * video decode on vcs followed by colour post-processing 105 * on vecs, followed by general post-processing on rcs. 106 * Since multi-engines being active does imply a single 107 * continuous workload across all engines, we hedge our 108 * bets by only contributing a factor of the distributed 109 * load into our busyness calculation. 110 */ 111 busy = max_busy[0]; 112 for (i = 1; i < ARRAY_SIZE(max_busy); i++) { 113 if (!max_busy[i]) 114 break; 115 116 busy += div_u64(max_busy[i], 1 << i); 117 } 118 GT_TRACE(rps_to_gt(rps), 119 "busy:%lld [%d%%], max:[%lld, %lld, %lld], interval:%d\n", 120 busy, (int)div64_u64(100 * busy, dt), 121 max_busy[0], max_busy[1], max_busy[2], 122 rps->pm_interval); 123 124 if (100 * busy > rps->power.up_threshold * dt && 125 rps->cur_freq < rps->max_freq_softlimit) { 126 rps->pm_iir |= GEN6_PM_RP_UP_THRESHOLD; 127 rps->pm_interval = 1; 128 schedule_work(&rps->work); 129 } else if (100 * busy < rps->power.down_threshold * dt && 130 rps->cur_freq > rps->min_freq_softlimit) { 131 rps->pm_iir |= GEN6_PM_RP_DOWN_THRESHOLD; 132 rps->pm_interval = 1; 133 schedule_work(&rps->work); 134 } else { 135 rps->last_adj = 0; 136 } 137 138 mod_timer(&rps->timer, 139 jiffies + msecs_to_jiffies(rps->pm_interval)); 140 rps->pm_interval = min(rps->pm_interval * 2, BUSY_MAX_EI); 141 } 142 } 143 144 static void rps_start_timer(struct intel_rps *rps) 145 { 146 rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp); 147 rps->pm_interval = 1; 148 mod_timer(&rps->timer, jiffies + 1); 149 } 150 151 static void rps_stop_timer(struct intel_rps *rps) 152 { 153 del_timer_sync(&rps->timer); 154 rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp); 155 cancel_work_sync(&rps->work); 156 } 157 158 static u32 rps_pm_mask(struct intel_rps *rps, u8 val) 159 { 160 u32 mask = 0; 161 162 /* We use UP_EI_EXPIRED interrupts for both up/down in manual mode */ 163 if (val > rps->min_freq_softlimit) 164 mask |= (GEN6_PM_RP_UP_EI_EXPIRED | 165 GEN6_PM_RP_DOWN_THRESHOLD | 166 GEN6_PM_RP_DOWN_TIMEOUT); 167 168 if (val < rps->max_freq_softlimit) 169 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; 170 171 mask &= rps->pm_events; 172 173 return rps_pm_sanitize_mask(rps, ~mask); 174 } 175 176 static void rps_reset_ei(struct intel_rps *rps) 177 { 178 memset(&rps->ei, 0, sizeof(rps->ei)); 179 } 180 181 static void rps_enable_interrupts(struct intel_rps *rps) 182 { 183 struct intel_gt *gt = rps_to_gt(rps); 184 185 GEM_BUG_ON(rps_uses_slpc(rps)); 186 187 GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n", 188 rps->pm_events, rps_pm_mask(rps, rps->last_freq)); 189 190 rps_reset_ei(rps); 191 192 spin_lock_irq(>->irq_lock); 193 gen6_gt_pm_enable_irq(gt, rps->pm_events); 194 spin_unlock_irq(>->irq_lock); 195 196 intel_uncore_write(gt->uncore, 197 GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq)); 198 } 199 200 static void gen6_rps_reset_interrupts(struct intel_rps *rps) 201 { 202 gen6_gt_pm_reset_iir(rps_to_gt(rps), GEN6_PM_RPS_EVENTS); 203 } 204 205 static void gen11_rps_reset_interrupts(struct intel_rps *rps) 206 { 207 while (gen11_gt_reset_one_iir(rps_to_gt(rps), 0, GEN11_GTPM)) 208 ; 209 } 210 211 static void rps_reset_interrupts(struct intel_rps *rps) 212 { 213 struct intel_gt *gt = rps_to_gt(rps); 214 215 spin_lock_irq(>->irq_lock); 216 if (GRAPHICS_VER(gt->i915) >= 11) 217 gen11_rps_reset_interrupts(rps); 218 else 219 gen6_rps_reset_interrupts(rps); 220 221 rps->pm_iir = 0; 222 spin_unlock_irq(>->irq_lock); 223 } 224 225 static void rps_disable_interrupts(struct intel_rps *rps) 226 { 227 struct intel_gt *gt = rps_to_gt(rps); 228 229 intel_uncore_write(gt->uncore, 230 GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u)); 231 232 spin_lock_irq(>->irq_lock); 233 gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS); 234 spin_unlock_irq(>->irq_lock); 235 236 intel_synchronize_irq(gt->i915); 237 238 /* 239 * Now that we will not be generating any more work, flush any 240 * outstanding tasks. As we are called on the RPS idle path, 241 * we will reset the GPU to minimum frequencies, so the current 242 * state of the worker can be discarded. 243 */ 244 cancel_work_sync(&rps->work); 245 246 rps_reset_interrupts(rps); 247 GT_TRACE(gt, "interrupts:off\n"); 248 } 249 250 static const struct cparams { 251 u16 i; 252 u16 t; 253 u16 m; 254 u16 c; 255 } cparams[] = { 256 { 1, 1333, 301, 28664 }, 257 { 1, 1066, 294, 24460 }, 258 { 1, 800, 294, 25192 }, 259 { 0, 1333, 276, 27605 }, 260 { 0, 1066, 276, 27605 }, 261 { 0, 800, 231, 23784 }, 262 }; 263 264 static void gen5_rps_init(struct intel_rps *rps) 265 { 266 struct drm_i915_private *i915 = rps_to_i915(rps); 267 struct intel_uncore *uncore = rps_to_uncore(rps); 268 u8 fmax, fmin, fstart; 269 u32 rgvmodectl; 270 int c_m, i; 271 272 if (i915->fsb_freq <= 3200) 273 c_m = 0; 274 else if (i915->fsb_freq <= 4800) 275 c_m = 1; 276 else 277 c_m = 2; 278 279 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 280 if (cparams[i].i == c_m && cparams[i].t == i915->mem_freq) { 281 rps->ips.m = cparams[i].m; 282 rps->ips.c = cparams[i].c; 283 break; 284 } 285 } 286 287 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); 288 289 /* Set up min, max, and cur for interrupt handling */ 290 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 291 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 292 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 293 MEMMODE_FSTART_SHIFT; 294 drm_dbg(&i915->drm, "fmax: %d, fmin: %d, fstart: %d\n", 295 fmax, fmin, fstart); 296 297 rps->min_freq = fmax; 298 rps->efficient_freq = fstart; 299 rps->max_freq = fmin; 300 } 301 302 static unsigned long 303 __ips_chipset_val(struct intel_ips *ips) 304 { 305 struct intel_uncore *uncore = 306 rps_to_uncore(container_of(ips, struct intel_rps, ips)); 307 unsigned long now = jiffies_to_msecs(jiffies), dt; 308 unsigned long result; 309 u64 total, delta; 310 311 lockdep_assert_held(&mchdev_lock); 312 313 /* 314 * Prevent division-by-zero if we are asking too fast. 315 * Also, we don't get interesting results if we are polling 316 * faster than once in 10ms, so just return the saved value 317 * in such cases. 318 */ 319 dt = now - ips->last_time1; 320 if (dt <= 10) 321 return ips->chipset_power; 322 323 /* FIXME: handle per-counter overflow */ 324 total = intel_uncore_read(uncore, DMIEC); 325 total += intel_uncore_read(uncore, DDREC); 326 total += intel_uncore_read(uncore, CSIEC); 327 328 delta = total - ips->last_count1; 329 330 result = div_u64(div_u64(ips->m * delta, dt) + ips->c, 10); 331 332 ips->last_count1 = total; 333 ips->last_time1 = now; 334 335 ips->chipset_power = result; 336 337 return result; 338 } 339 340 static unsigned long ips_mch_val(struct intel_uncore *uncore) 341 { 342 unsigned int m, x, b; 343 u32 tsfs; 344 345 tsfs = intel_uncore_read(uncore, TSFS); 346 x = intel_uncore_read8(uncore, TR1); 347 348 b = tsfs & TSFS_INTR_MASK; 349 m = (tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT; 350 351 return m * x / 127 - b; 352 } 353 354 static int _pxvid_to_vd(u8 pxvid) 355 { 356 if (pxvid == 0) 357 return 0; 358 359 if (pxvid >= 8 && pxvid < 31) 360 pxvid = 31; 361 362 return (pxvid + 2) * 125; 363 } 364 365 static u32 pvid_to_extvid(struct drm_i915_private *i915, u8 pxvid) 366 { 367 const int vd = _pxvid_to_vd(pxvid); 368 369 if (INTEL_INFO(i915)->is_mobile) 370 return max(vd - 1125, 0); 371 372 return vd; 373 } 374 375 static void __gen5_ips_update(struct intel_ips *ips) 376 { 377 struct intel_uncore *uncore = 378 rps_to_uncore(container_of(ips, struct intel_rps, ips)); 379 u64 now, delta, dt; 380 u32 count; 381 382 lockdep_assert_held(&mchdev_lock); 383 384 now = ktime_get_raw_ns(); 385 dt = now - ips->last_time2; 386 do_div(dt, NSEC_PER_MSEC); 387 388 /* Don't divide by 0 */ 389 if (dt <= 10) 390 return; 391 392 count = intel_uncore_read(uncore, GFXEC); 393 delta = count - ips->last_count2; 394 395 ips->last_count2 = count; 396 ips->last_time2 = now; 397 398 /* More magic constants... */ 399 ips->gfx_power = div_u64(delta * 1181, dt * 10); 400 } 401 402 static void gen5_rps_update(struct intel_rps *rps) 403 { 404 spin_lock_irq(&mchdev_lock); 405 __gen5_ips_update(&rps->ips); 406 spin_unlock_irq(&mchdev_lock); 407 } 408 409 static unsigned int gen5_invert_freq(struct intel_rps *rps, 410 unsigned int val) 411 { 412 /* Invert the frequency bin into an ips delay */ 413 val = rps->max_freq - val; 414 val = rps->min_freq + val; 415 416 return val; 417 } 418 419 static int __gen5_rps_set(struct intel_rps *rps, u8 val) 420 { 421 struct intel_uncore *uncore = rps_to_uncore(rps); 422 u16 rgvswctl; 423 424 lockdep_assert_held(&mchdev_lock); 425 426 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); 427 if (rgvswctl & MEMCTL_CMD_STS) { 428 DRM_DEBUG("gpu busy, RCS change rejected\n"); 429 return -EBUSY; /* still busy with another command */ 430 } 431 432 /* Invert the frequency bin into an ips delay */ 433 val = gen5_invert_freq(rps, val); 434 435 rgvswctl = 436 (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 437 (val << MEMCTL_FREQ_SHIFT) | 438 MEMCTL_SFCAVM; 439 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl); 440 intel_uncore_posting_read16(uncore, MEMSWCTL); 441 442 rgvswctl |= MEMCTL_CMD_STS; 443 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl); 444 445 return 0; 446 } 447 448 static int gen5_rps_set(struct intel_rps *rps, u8 val) 449 { 450 int err; 451 452 spin_lock_irq(&mchdev_lock); 453 err = __gen5_rps_set(rps, val); 454 spin_unlock_irq(&mchdev_lock); 455 456 return err; 457 } 458 459 static unsigned long intel_pxfreq(u32 vidfreq) 460 { 461 int div = (vidfreq & 0x3f0000) >> 16; 462 int post = (vidfreq & 0x3000) >> 12; 463 int pre = (vidfreq & 0x7); 464 465 if (!pre) 466 return 0; 467 468 return div * 133333 / (pre << post); 469 } 470 471 static unsigned int init_emon(struct intel_uncore *uncore) 472 { 473 u8 pxw[16]; 474 int i; 475 476 /* Disable to program */ 477 intel_uncore_write(uncore, ECR, 0); 478 intel_uncore_posting_read(uncore, ECR); 479 480 /* Program energy weights for various events */ 481 intel_uncore_write(uncore, SDEW, 0x15040d00); 482 intel_uncore_write(uncore, CSIEW0, 0x007f0000); 483 intel_uncore_write(uncore, CSIEW1, 0x1e220004); 484 intel_uncore_write(uncore, CSIEW2, 0x04000004); 485 486 for (i = 0; i < 5; i++) 487 intel_uncore_write(uncore, PEW(i), 0); 488 for (i = 0; i < 3; i++) 489 intel_uncore_write(uncore, DEW(i), 0); 490 491 /* Program P-state weights to account for frequency power adjustment */ 492 for (i = 0; i < 16; i++) { 493 u32 pxvidfreq = intel_uncore_read(uncore, PXVFREQ(i)); 494 unsigned int freq = intel_pxfreq(pxvidfreq); 495 unsigned int vid = 496 (pxvidfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT; 497 unsigned int val; 498 499 val = vid * vid * freq / 1000 * 255; 500 val /= 127 * 127 * 900; 501 502 pxw[i] = val; 503 } 504 /* Render standby states get 0 weight */ 505 pxw[14] = 0; 506 pxw[15] = 0; 507 508 for (i = 0; i < 4; i++) { 509 intel_uncore_write(uncore, PXW(i), 510 pxw[i * 4 + 0] << 24 | 511 pxw[i * 4 + 1] << 16 | 512 pxw[i * 4 + 2] << 8 | 513 pxw[i * 4 + 3] << 0); 514 } 515 516 /* Adjust magic regs to magic values (more experimental results) */ 517 intel_uncore_write(uncore, OGW0, 0); 518 intel_uncore_write(uncore, OGW1, 0); 519 intel_uncore_write(uncore, EG0, 0x00007f00); 520 intel_uncore_write(uncore, EG1, 0x0000000e); 521 intel_uncore_write(uncore, EG2, 0x000e0000); 522 intel_uncore_write(uncore, EG3, 0x68000300); 523 intel_uncore_write(uncore, EG4, 0x42000000); 524 intel_uncore_write(uncore, EG5, 0x00140031); 525 intel_uncore_write(uncore, EG6, 0); 526 intel_uncore_write(uncore, EG7, 0); 527 528 for (i = 0; i < 8; i++) 529 intel_uncore_write(uncore, PXWL(i), 0); 530 531 /* Enable PMON + select events */ 532 intel_uncore_write(uncore, ECR, 0x80000019); 533 534 return intel_uncore_read(uncore, LCFUSE02) & LCFUSE_HIV_MASK; 535 } 536 537 static bool gen5_rps_enable(struct intel_rps *rps) 538 { 539 struct drm_i915_private *i915 = rps_to_i915(rps); 540 struct intel_uncore *uncore = rps_to_uncore(rps); 541 u8 fstart, vstart; 542 u32 rgvmodectl; 543 544 spin_lock_irq(&mchdev_lock); 545 546 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); 547 548 /* Enable temp reporting */ 549 intel_uncore_write16(uncore, PMMISC, 550 intel_uncore_read16(uncore, PMMISC) | MCPPCE_EN); 551 intel_uncore_write16(uncore, TSC1, 552 intel_uncore_read16(uncore, TSC1) | TSE); 553 554 /* 100ms RC evaluation intervals */ 555 intel_uncore_write(uncore, RCUPEI, 100000); 556 intel_uncore_write(uncore, RCDNEI, 100000); 557 558 /* Set max/min thresholds to 90ms and 80ms respectively */ 559 intel_uncore_write(uncore, RCBMAXAVG, 90000); 560 intel_uncore_write(uncore, RCBMINAVG, 80000); 561 562 intel_uncore_write(uncore, MEMIHYST, 1); 563 564 /* Set up min, max, and cur for interrupt handling */ 565 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 566 MEMMODE_FSTART_SHIFT; 567 568 vstart = (intel_uncore_read(uncore, PXVFREQ(fstart)) & 569 PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT; 570 571 intel_uncore_write(uncore, 572 MEMINTREN, 573 MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 574 575 intel_uncore_write(uncore, VIDSTART, vstart); 576 intel_uncore_posting_read(uncore, VIDSTART); 577 578 rgvmodectl |= MEMMODE_SWMODE_EN; 579 intel_uncore_write(uncore, MEMMODECTL, rgvmodectl); 580 581 if (wait_for_atomic((intel_uncore_read(uncore, MEMSWCTL) & 582 MEMCTL_CMD_STS) == 0, 10)) 583 drm_err(&uncore->i915->drm, 584 "stuck trying to change perf mode\n"); 585 mdelay(1); 586 587 __gen5_rps_set(rps, rps->cur_freq); 588 589 rps->ips.last_count1 = intel_uncore_read(uncore, DMIEC); 590 rps->ips.last_count1 += intel_uncore_read(uncore, DDREC); 591 rps->ips.last_count1 += intel_uncore_read(uncore, CSIEC); 592 rps->ips.last_time1 = jiffies_to_msecs(jiffies); 593 594 rps->ips.last_count2 = intel_uncore_read(uncore, GFXEC); 595 rps->ips.last_time2 = ktime_get_raw_ns(); 596 597 spin_lock(&i915->irq_lock); 598 ilk_enable_display_irq(i915, DE_PCU_EVENT); 599 spin_unlock(&i915->irq_lock); 600 601 spin_unlock_irq(&mchdev_lock); 602 603 rps->ips.corr = init_emon(uncore); 604 605 return true; 606 } 607 608 static void gen5_rps_disable(struct intel_rps *rps) 609 { 610 struct drm_i915_private *i915 = rps_to_i915(rps); 611 struct intel_uncore *uncore = rps_to_uncore(rps); 612 u16 rgvswctl; 613 614 spin_lock_irq(&mchdev_lock); 615 616 spin_lock(&i915->irq_lock); 617 ilk_disable_display_irq(i915, DE_PCU_EVENT); 618 spin_unlock(&i915->irq_lock); 619 620 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); 621 622 /* Ack interrupts, disable EFC interrupt */ 623 intel_uncore_write(uncore, MEMINTREN, 624 intel_uncore_read(uncore, MEMINTREN) & 625 ~MEMINT_EVAL_CHG_EN); 626 intel_uncore_write(uncore, MEMINTRSTS, MEMINT_EVAL_CHG); 627 628 /* Go back to the starting frequency */ 629 __gen5_rps_set(rps, rps->idle_freq); 630 mdelay(1); 631 rgvswctl |= MEMCTL_CMD_STS; 632 intel_uncore_write(uncore, MEMSWCTL, rgvswctl); 633 mdelay(1); 634 635 spin_unlock_irq(&mchdev_lock); 636 } 637 638 static u32 rps_limits(struct intel_rps *rps, u8 val) 639 { 640 u32 limits; 641 642 /* 643 * Only set the down limit when we've reached the lowest level to avoid 644 * getting more interrupts, otherwise leave this clear. This prevents a 645 * race in the hw when coming out of rc6: There's a tiny window where 646 * the hw runs at the minimal clock before selecting the desired 647 * frequency, if the down threshold expires in that window we will not 648 * receive a down interrupt. 649 */ 650 if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) { 651 limits = rps->max_freq_softlimit << 23; 652 if (val <= rps->min_freq_softlimit) 653 limits |= rps->min_freq_softlimit << 14; 654 } else { 655 limits = rps->max_freq_softlimit << 24; 656 if (val <= rps->min_freq_softlimit) 657 limits |= rps->min_freq_softlimit << 16; 658 } 659 660 return limits; 661 } 662 663 static void rps_set_power(struct intel_rps *rps, int new_power) 664 { 665 struct intel_gt *gt = rps_to_gt(rps); 666 struct intel_uncore *uncore = gt->uncore; 667 u32 threshold_up = 0, threshold_down = 0; /* in % */ 668 u32 ei_up = 0, ei_down = 0; 669 670 lockdep_assert_held(&rps->power.mutex); 671 672 if (new_power == rps->power.mode) 673 return; 674 675 threshold_up = 95; 676 threshold_down = 85; 677 678 /* Note the units here are not exactly 1us, but 1280ns. */ 679 switch (new_power) { 680 case LOW_POWER: 681 ei_up = 16000; 682 ei_down = 32000; 683 break; 684 685 case BETWEEN: 686 ei_up = 13000; 687 ei_down = 32000; 688 break; 689 690 case HIGH_POWER: 691 ei_up = 10000; 692 ei_down = 32000; 693 break; 694 } 695 696 /* When byt can survive without system hang with dynamic 697 * sw freq adjustments, this restriction can be lifted. 698 */ 699 if (IS_VALLEYVIEW(gt->i915)) 700 goto skip_hw_write; 701 702 GT_TRACE(gt, 703 "changing power mode [%d], up %d%% @ %dus, down %d%% @ %dus\n", 704 new_power, threshold_up, ei_up, threshold_down, ei_down); 705 706 set(uncore, GEN6_RP_UP_EI, 707 intel_gt_ns_to_pm_interval(gt, ei_up * 1000)); 708 set(uncore, GEN6_RP_UP_THRESHOLD, 709 intel_gt_ns_to_pm_interval(gt, ei_up * threshold_up * 10)); 710 711 set(uncore, GEN6_RP_DOWN_EI, 712 intel_gt_ns_to_pm_interval(gt, ei_down * 1000)); 713 set(uncore, GEN6_RP_DOWN_THRESHOLD, 714 intel_gt_ns_to_pm_interval(gt, ei_down * threshold_down * 10)); 715 716 set(uncore, GEN6_RP_CONTROL, 717 (GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) | 718 GEN6_RP_MEDIA_HW_NORMAL_MODE | 719 GEN6_RP_MEDIA_IS_GFX | 720 GEN6_RP_ENABLE | 721 GEN6_RP_UP_BUSY_AVG | 722 GEN6_RP_DOWN_IDLE_AVG); 723 724 skip_hw_write: 725 rps->power.mode = new_power; 726 rps->power.up_threshold = threshold_up; 727 rps->power.down_threshold = threshold_down; 728 } 729 730 static void gen6_rps_set_thresholds(struct intel_rps *rps, u8 val) 731 { 732 int new_power; 733 734 new_power = rps->power.mode; 735 switch (rps->power.mode) { 736 case LOW_POWER: 737 if (val > rps->efficient_freq + 1 && 738 val > rps->cur_freq) 739 new_power = BETWEEN; 740 break; 741 742 case BETWEEN: 743 if (val <= rps->efficient_freq && 744 val < rps->cur_freq) 745 new_power = LOW_POWER; 746 else if (val >= rps->rp0_freq && 747 val > rps->cur_freq) 748 new_power = HIGH_POWER; 749 break; 750 751 case HIGH_POWER: 752 if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 && 753 val < rps->cur_freq) 754 new_power = BETWEEN; 755 break; 756 } 757 /* Max/min bins are special */ 758 if (val <= rps->min_freq_softlimit) 759 new_power = LOW_POWER; 760 if (val >= rps->max_freq_softlimit) 761 new_power = HIGH_POWER; 762 763 mutex_lock(&rps->power.mutex); 764 if (rps->power.interactive) 765 new_power = HIGH_POWER; 766 rps_set_power(rps, new_power); 767 mutex_unlock(&rps->power.mutex); 768 } 769 770 void intel_rps_mark_interactive(struct intel_rps *rps, bool interactive) 771 { 772 GT_TRACE(rps_to_gt(rps), "mark interactive: %s\n", yesno(interactive)); 773 774 mutex_lock(&rps->power.mutex); 775 if (interactive) { 776 if (!rps->power.interactive++ && intel_rps_is_active(rps)) 777 rps_set_power(rps, HIGH_POWER); 778 } else { 779 GEM_BUG_ON(!rps->power.interactive); 780 rps->power.interactive--; 781 } 782 mutex_unlock(&rps->power.mutex); 783 } 784 785 static int gen6_rps_set(struct intel_rps *rps, u8 val) 786 { 787 struct intel_uncore *uncore = rps_to_uncore(rps); 788 struct drm_i915_private *i915 = rps_to_i915(rps); 789 u32 swreq; 790 791 GEM_BUG_ON(rps_uses_slpc(rps)); 792 793 if (GRAPHICS_VER(i915) >= 9) 794 swreq = GEN9_FREQUENCY(val); 795 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 796 swreq = HSW_FREQUENCY(val); 797 else 798 swreq = (GEN6_FREQUENCY(val) | 799 GEN6_OFFSET(0) | 800 GEN6_AGGRESSIVE_TURBO); 801 set(uncore, GEN6_RPNSWREQ, swreq); 802 803 GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d, swreq:%x\n", 804 val, intel_gpu_freq(rps, val), swreq); 805 806 return 0; 807 } 808 809 static int vlv_rps_set(struct intel_rps *rps, u8 val) 810 { 811 struct drm_i915_private *i915 = rps_to_i915(rps); 812 int err; 813 814 vlv_punit_get(i915); 815 err = vlv_punit_write(i915, PUNIT_REG_GPU_FREQ_REQ, val); 816 vlv_punit_put(i915); 817 818 GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d\n", 819 val, intel_gpu_freq(rps, val)); 820 821 return err; 822 } 823 824 static int rps_set(struct intel_rps *rps, u8 val, bool update) 825 { 826 struct drm_i915_private *i915 = rps_to_i915(rps); 827 int err; 828 829 if (val == rps->last_freq) 830 return 0; 831 832 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 833 err = vlv_rps_set(rps, val); 834 else if (GRAPHICS_VER(i915) >= 6) 835 err = gen6_rps_set(rps, val); 836 else 837 err = gen5_rps_set(rps, val); 838 if (err) 839 return err; 840 841 if (update && GRAPHICS_VER(i915) >= 6) 842 gen6_rps_set_thresholds(rps, val); 843 rps->last_freq = val; 844 845 return 0; 846 } 847 848 void intel_rps_unpark(struct intel_rps *rps) 849 { 850 if (!intel_rps_is_enabled(rps)) 851 return; 852 853 GT_TRACE(rps_to_gt(rps), "unpark:%x\n", rps->cur_freq); 854 855 /* 856 * Use the user's desired frequency as a guide, but for better 857 * performance, jump directly to RPe as our starting frequency. 858 */ 859 mutex_lock(&rps->lock); 860 861 intel_rps_set_active(rps); 862 intel_rps_set(rps, 863 clamp(rps->cur_freq, 864 rps->min_freq_softlimit, 865 rps->max_freq_softlimit)); 866 867 mutex_unlock(&rps->lock); 868 869 rps->pm_iir = 0; 870 if (intel_rps_has_interrupts(rps)) 871 rps_enable_interrupts(rps); 872 if (intel_rps_uses_timer(rps)) 873 rps_start_timer(rps); 874 875 if (GRAPHICS_VER(rps_to_i915(rps)) == 5) 876 gen5_rps_update(rps); 877 } 878 879 void intel_rps_park(struct intel_rps *rps) 880 { 881 int adj; 882 883 if (!intel_rps_is_enabled(rps)) 884 return; 885 886 if (!intel_rps_clear_active(rps)) 887 return; 888 889 if (intel_rps_uses_timer(rps)) 890 rps_stop_timer(rps); 891 if (intel_rps_has_interrupts(rps)) 892 rps_disable_interrupts(rps); 893 894 if (rps->last_freq <= rps->idle_freq) 895 return; 896 897 /* 898 * The punit delays the write of the frequency and voltage until it 899 * determines the GPU is awake. During normal usage we don't want to 900 * waste power changing the frequency if the GPU is sleeping (rc6). 901 * However, the GPU and driver is now idle and we do not want to delay 902 * switching to minimum voltage (reducing power whilst idle) as we do 903 * not expect to be woken in the near future and so must flush the 904 * change by waking the device. 905 * 906 * We choose to take the media powerwell (either would do to trick the 907 * punit into committing the voltage change) as that takes a lot less 908 * power than the render powerwell. 909 */ 910 intel_uncore_forcewake_get(rps_to_uncore(rps), FORCEWAKE_MEDIA); 911 rps_set(rps, rps->idle_freq, false); 912 intel_uncore_forcewake_put(rps_to_uncore(rps), FORCEWAKE_MEDIA); 913 914 /* 915 * Since we will try and restart from the previously requested 916 * frequency on unparking, treat this idle point as a downclock 917 * interrupt and reduce the frequency for resume. If we park/unpark 918 * more frequently than the rps worker can run, we will not respond 919 * to any EI and never see a change in frequency. 920 * 921 * (Note we accommodate Cherryview's limitation of only using an 922 * even bin by applying it to all.) 923 */ 924 adj = rps->last_adj; 925 if (adj < 0) 926 adj *= 2; 927 else /* CHV needs even encode values */ 928 adj = -2; 929 rps->last_adj = adj; 930 rps->cur_freq = max_t(int, rps->cur_freq + adj, rps->min_freq); 931 if (rps->cur_freq < rps->efficient_freq) { 932 rps->cur_freq = rps->efficient_freq; 933 rps->last_adj = 0; 934 } 935 936 GT_TRACE(rps_to_gt(rps), "park:%x\n", rps->cur_freq); 937 } 938 939 u32 intel_rps_get_boost_frequency(struct intel_rps *rps) 940 { 941 struct intel_guc_slpc *slpc; 942 943 if (rps_uses_slpc(rps)) { 944 slpc = rps_to_slpc(rps); 945 946 return slpc->boost_freq; 947 } else { 948 return intel_gpu_freq(rps, rps->boost_freq); 949 } 950 } 951 952 static int rps_set_boost_freq(struct intel_rps *rps, u32 val) 953 { 954 bool boost = false; 955 956 /* Validate against (static) hardware limits */ 957 val = intel_freq_opcode(rps, val); 958 if (val < rps->min_freq || val > rps->max_freq) 959 return -EINVAL; 960 961 mutex_lock(&rps->lock); 962 if (val != rps->boost_freq) { 963 rps->boost_freq = val; 964 boost = atomic_read(&rps->num_waiters); 965 } 966 mutex_unlock(&rps->lock); 967 if (boost) 968 schedule_work(&rps->work); 969 970 return 0; 971 } 972 973 int intel_rps_set_boost_frequency(struct intel_rps *rps, u32 freq) 974 { 975 struct intel_guc_slpc *slpc; 976 977 if (rps_uses_slpc(rps)) { 978 slpc = rps_to_slpc(rps); 979 980 return intel_guc_slpc_set_boost_freq(slpc, freq); 981 } else { 982 return rps_set_boost_freq(rps, freq); 983 } 984 } 985 986 void intel_rps_dec_waiters(struct intel_rps *rps) 987 { 988 struct intel_guc_slpc *slpc; 989 990 if (rps_uses_slpc(rps)) { 991 slpc = rps_to_slpc(rps); 992 993 intel_guc_slpc_dec_waiters(slpc); 994 } else { 995 atomic_dec(&rps->num_waiters); 996 } 997 } 998 999 void intel_rps_boost(struct i915_request *rq) 1000 { 1001 struct intel_guc_slpc *slpc; 1002 1003 if (i915_request_signaled(rq) || i915_request_has_waitboost(rq)) 1004 return; 1005 1006 /* Serializes with i915_request_retire() */ 1007 if (!test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags)) { 1008 struct intel_rps *rps = &READ_ONCE(rq->engine)->gt->rps; 1009 1010 if (rps_uses_slpc(rps)) { 1011 slpc = rps_to_slpc(rps); 1012 1013 /* Return if old value is non zero */ 1014 if (!atomic_fetch_inc(&slpc->num_waiters)) 1015 schedule_work(&slpc->boost_work); 1016 1017 return; 1018 } 1019 1020 if (atomic_fetch_inc(&rps->num_waiters)) 1021 return; 1022 1023 if (!intel_rps_is_active(rps)) 1024 return; 1025 1026 GT_TRACE(rps_to_gt(rps), "boost fence:%llx:%llx\n", 1027 rq->fence.context, rq->fence.seqno); 1028 1029 if (READ_ONCE(rps->cur_freq) < rps->boost_freq) 1030 schedule_work(&rps->work); 1031 1032 WRITE_ONCE(rps->boosts, rps->boosts + 1); /* debug only */ 1033 } 1034 } 1035 1036 int intel_rps_set(struct intel_rps *rps, u8 val) 1037 { 1038 int err; 1039 1040 lockdep_assert_held(&rps->lock); 1041 GEM_BUG_ON(val > rps->max_freq); 1042 GEM_BUG_ON(val < rps->min_freq); 1043 1044 if (intel_rps_is_active(rps)) { 1045 err = rps_set(rps, val, true); 1046 if (err) 1047 return err; 1048 1049 /* 1050 * Make sure we continue to get interrupts 1051 * until we hit the minimum or maximum frequencies. 1052 */ 1053 if (intel_rps_has_interrupts(rps)) { 1054 struct intel_uncore *uncore = rps_to_uncore(rps); 1055 1056 set(uncore, 1057 GEN6_RP_INTERRUPT_LIMITS, rps_limits(rps, val)); 1058 1059 set(uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, val)); 1060 } 1061 } 1062 1063 rps->cur_freq = val; 1064 return 0; 1065 } 1066 1067 static void gen6_rps_init(struct intel_rps *rps) 1068 { 1069 struct drm_i915_private *i915 = rps_to_i915(rps); 1070 u32 rp_state_cap = intel_rps_read_state_cap(rps); 1071 1072 /* All of these values are in units of 50MHz */ 1073 1074 /* static values from HW: RP0 > RP1 > RPn (min_freq) */ 1075 if (IS_GEN9_LP(i915)) { 1076 rps->rp0_freq = (rp_state_cap >> 16) & 0xff; 1077 rps->rp1_freq = (rp_state_cap >> 8) & 0xff; 1078 rps->min_freq = (rp_state_cap >> 0) & 0xff; 1079 } else { 1080 rps->rp0_freq = (rp_state_cap >> 0) & 0xff; 1081 rps->rp1_freq = (rp_state_cap >> 8) & 0xff; 1082 rps->min_freq = (rp_state_cap >> 16) & 0xff; 1083 } 1084 1085 /* hw_max = RP0 until we check for overclocking */ 1086 rps->max_freq = rps->rp0_freq; 1087 1088 rps->efficient_freq = rps->rp1_freq; 1089 if (IS_HASWELL(i915) || IS_BROADWELL(i915) || 1090 IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { 1091 u32 ddcc_status = 0; 1092 1093 if (sandybridge_pcode_read(i915, 1094 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, 1095 &ddcc_status, NULL) == 0) 1096 rps->efficient_freq = 1097 clamp_t(u8, 1098 (ddcc_status >> 8) & 0xff, 1099 rps->min_freq, 1100 rps->max_freq); 1101 } 1102 1103 if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { 1104 /* Store the frequency values in 16.66 MHZ units, which is 1105 * the natural hardware unit for SKL 1106 */ 1107 rps->rp0_freq *= GEN9_FREQ_SCALER; 1108 rps->rp1_freq *= GEN9_FREQ_SCALER; 1109 rps->min_freq *= GEN9_FREQ_SCALER; 1110 rps->max_freq *= GEN9_FREQ_SCALER; 1111 rps->efficient_freq *= GEN9_FREQ_SCALER; 1112 } 1113 } 1114 1115 static bool rps_reset(struct intel_rps *rps) 1116 { 1117 struct drm_i915_private *i915 = rps_to_i915(rps); 1118 1119 /* force a reset */ 1120 rps->power.mode = -1; 1121 rps->last_freq = -1; 1122 1123 if (rps_set(rps, rps->min_freq, true)) { 1124 drm_err(&i915->drm, "Failed to reset RPS to initial values\n"); 1125 return false; 1126 } 1127 1128 rps->cur_freq = rps->min_freq; 1129 return true; 1130 } 1131 1132 /* See the Gen9_GT_PM_Programming_Guide doc for the below */ 1133 static bool gen9_rps_enable(struct intel_rps *rps) 1134 { 1135 struct intel_gt *gt = rps_to_gt(rps); 1136 struct intel_uncore *uncore = gt->uncore; 1137 1138 /* Program defaults and thresholds for RPS */ 1139 if (GRAPHICS_VER(gt->i915) == 9) 1140 intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ, 1141 GEN9_FREQUENCY(rps->rp1_freq)); 1142 1143 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 0xa); 1144 1145 rps->pm_events = GEN6_PM_RP_UP_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD; 1146 1147 return rps_reset(rps); 1148 } 1149 1150 static bool gen8_rps_enable(struct intel_rps *rps) 1151 { 1152 struct intel_uncore *uncore = rps_to_uncore(rps); 1153 1154 intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ, 1155 HSW_FREQUENCY(rps->rp1_freq)); 1156 1157 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); 1158 1159 rps->pm_events = GEN6_PM_RP_UP_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD; 1160 1161 return rps_reset(rps); 1162 } 1163 1164 static bool gen6_rps_enable(struct intel_rps *rps) 1165 { 1166 struct intel_uncore *uncore = rps_to_uncore(rps); 1167 1168 /* Power down if completely idle for over 50ms */ 1169 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 50000); 1170 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); 1171 1172 rps->pm_events = (GEN6_PM_RP_UP_THRESHOLD | 1173 GEN6_PM_RP_DOWN_THRESHOLD | 1174 GEN6_PM_RP_DOWN_TIMEOUT); 1175 1176 return rps_reset(rps); 1177 } 1178 1179 static int chv_rps_max_freq(struct intel_rps *rps) 1180 { 1181 struct drm_i915_private *i915 = rps_to_i915(rps); 1182 struct intel_gt *gt = rps_to_gt(rps); 1183 u32 val; 1184 1185 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); 1186 1187 switch (gt->info.sseu.eu_total) { 1188 case 8: 1189 /* (2 * 4) config */ 1190 val >>= FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT; 1191 break; 1192 case 12: 1193 /* (2 * 6) config */ 1194 val >>= FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT; 1195 break; 1196 case 16: 1197 /* (2 * 8) config */ 1198 default: 1199 /* Setting (2 * 8) Min RP0 for any other combination */ 1200 val >>= FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT; 1201 break; 1202 } 1203 1204 return val & FB_GFX_FREQ_FUSE_MASK; 1205 } 1206 1207 static int chv_rps_rpe_freq(struct intel_rps *rps) 1208 { 1209 struct drm_i915_private *i915 = rps_to_i915(rps); 1210 u32 val; 1211 1212 val = vlv_punit_read(i915, PUNIT_GPU_DUTYCYCLE_REG); 1213 val >>= PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT; 1214 1215 return val & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; 1216 } 1217 1218 static int chv_rps_guar_freq(struct intel_rps *rps) 1219 { 1220 struct drm_i915_private *i915 = rps_to_i915(rps); 1221 u32 val; 1222 1223 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); 1224 1225 return val & FB_GFX_FREQ_FUSE_MASK; 1226 } 1227 1228 static u32 chv_rps_min_freq(struct intel_rps *rps) 1229 { 1230 struct drm_i915_private *i915 = rps_to_i915(rps); 1231 u32 val; 1232 1233 val = vlv_punit_read(i915, FB_GFX_FMIN_AT_VMIN_FUSE); 1234 val >>= FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT; 1235 1236 return val & FB_GFX_FREQ_FUSE_MASK; 1237 } 1238 1239 static bool chv_rps_enable(struct intel_rps *rps) 1240 { 1241 struct intel_uncore *uncore = rps_to_uncore(rps); 1242 struct drm_i915_private *i915 = rps_to_i915(rps); 1243 u32 val; 1244 1245 /* 1: Program defaults and thresholds for RPS*/ 1246 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 1000000); 1247 intel_uncore_write_fw(uncore, GEN6_RP_UP_THRESHOLD, 59400); 1248 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_THRESHOLD, 245000); 1249 intel_uncore_write_fw(uncore, GEN6_RP_UP_EI, 66000); 1250 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_EI, 350000); 1251 1252 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); 1253 1254 /* 2: Enable RPS */ 1255 intel_uncore_write_fw(uncore, GEN6_RP_CONTROL, 1256 GEN6_RP_MEDIA_HW_NORMAL_MODE | 1257 GEN6_RP_MEDIA_IS_GFX | 1258 GEN6_RP_ENABLE | 1259 GEN6_RP_UP_BUSY_AVG | 1260 GEN6_RP_DOWN_IDLE_AVG); 1261 1262 rps->pm_events = (GEN6_PM_RP_UP_THRESHOLD | 1263 GEN6_PM_RP_DOWN_THRESHOLD | 1264 GEN6_PM_RP_DOWN_TIMEOUT); 1265 1266 /* Setting Fixed Bias */ 1267 vlv_punit_get(i915); 1268 1269 val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | CHV_BIAS_CPU_50_SOC_50; 1270 vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val); 1271 1272 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 1273 1274 vlv_punit_put(i915); 1275 1276 /* RPS code assumes GPLL is used */ 1277 drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0, 1278 "GPLL not enabled\n"); 1279 1280 drm_dbg(&i915->drm, "GPLL enabled? %s\n", yesno(val & GPLLENABLE)); 1281 drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val); 1282 1283 return rps_reset(rps); 1284 } 1285 1286 static int vlv_rps_guar_freq(struct intel_rps *rps) 1287 { 1288 struct drm_i915_private *i915 = rps_to_i915(rps); 1289 u32 val, rp1; 1290 1291 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE); 1292 1293 rp1 = val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK; 1294 rp1 >>= FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; 1295 1296 return rp1; 1297 } 1298 1299 static int vlv_rps_max_freq(struct intel_rps *rps) 1300 { 1301 struct drm_i915_private *i915 = rps_to_i915(rps); 1302 u32 val, rp0; 1303 1304 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE); 1305 1306 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; 1307 /* Clamp to max */ 1308 rp0 = min_t(u32, rp0, 0xea); 1309 1310 return rp0; 1311 } 1312 1313 static int vlv_rps_rpe_freq(struct intel_rps *rps) 1314 { 1315 struct drm_i915_private *i915 = rps_to_i915(rps); 1316 u32 val, rpe; 1317 1318 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_LO); 1319 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; 1320 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_HI); 1321 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; 1322 1323 return rpe; 1324 } 1325 1326 static int vlv_rps_min_freq(struct intel_rps *rps) 1327 { 1328 struct drm_i915_private *i915 = rps_to_i915(rps); 1329 u32 val; 1330 1331 val = vlv_punit_read(i915, PUNIT_REG_GPU_LFM) & 0xff; 1332 /* 1333 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value 1334 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on 1335 * a BYT-M B0 the above register contains 0xbf. Moreover when setting 1336 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0 1337 * to make sure it matches what Punit accepts. 1338 */ 1339 return max_t(u32, val, 0xc0); 1340 } 1341 1342 static bool vlv_rps_enable(struct intel_rps *rps) 1343 { 1344 struct intel_uncore *uncore = rps_to_uncore(rps); 1345 struct drm_i915_private *i915 = rps_to_i915(rps); 1346 u32 val; 1347 1348 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 1000000); 1349 intel_uncore_write_fw(uncore, GEN6_RP_UP_THRESHOLD, 59400); 1350 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_THRESHOLD, 245000); 1351 intel_uncore_write_fw(uncore, GEN6_RP_UP_EI, 66000); 1352 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_EI, 350000); 1353 1354 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); 1355 1356 intel_uncore_write_fw(uncore, GEN6_RP_CONTROL, 1357 GEN6_RP_MEDIA_TURBO | 1358 GEN6_RP_MEDIA_HW_NORMAL_MODE | 1359 GEN6_RP_MEDIA_IS_GFX | 1360 GEN6_RP_ENABLE | 1361 GEN6_RP_UP_BUSY_AVG | 1362 GEN6_RP_DOWN_IDLE_CONT); 1363 1364 /* WaGsvRC0ResidencyMethod:vlv */ 1365 rps->pm_events = GEN6_PM_RP_UP_EI_EXPIRED; 1366 1367 vlv_punit_get(i915); 1368 1369 /* Setting Fixed Bias */ 1370 val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | VLV_BIAS_CPU_125_SOC_875; 1371 vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val); 1372 1373 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 1374 1375 vlv_punit_put(i915); 1376 1377 /* RPS code assumes GPLL is used */ 1378 drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0, 1379 "GPLL not enabled\n"); 1380 1381 drm_dbg(&i915->drm, "GPLL enabled? %s\n", yesno(val & GPLLENABLE)); 1382 drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val); 1383 1384 return rps_reset(rps); 1385 } 1386 1387 static unsigned long __ips_gfx_val(struct intel_ips *ips) 1388 { 1389 struct intel_rps *rps = container_of(ips, typeof(*rps), ips); 1390 struct intel_uncore *uncore = rps_to_uncore(rps); 1391 unsigned int t, state1, state2; 1392 u32 pxvid, ext_v; 1393 u64 corr, corr2; 1394 1395 lockdep_assert_held(&mchdev_lock); 1396 1397 pxvid = intel_uncore_read(uncore, PXVFREQ(rps->cur_freq)); 1398 pxvid = (pxvid >> 24) & 0x7f; 1399 ext_v = pvid_to_extvid(rps_to_i915(rps), pxvid); 1400 1401 state1 = ext_v; 1402 1403 /* Revel in the empirically derived constants */ 1404 1405 /* Correction factor in 1/100000 units */ 1406 t = ips_mch_val(uncore); 1407 if (t > 80) 1408 corr = t * 2349 + 135940; 1409 else if (t >= 50) 1410 corr = t * 964 + 29317; 1411 else /* < 50 */ 1412 corr = t * 301 + 1004; 1413 1414 corr = div_u64(corr * 150142 * state1, 10000) - 78642; 1415 corr2 = div_u64(corr, 100000) * ips->corr; 1416 1417 state2 = div_u64(corr2 * state1, 10000); 1418 state2 /= 100; /* convert to mW */ 1419 1420 __gen5_ips_update(ips); 1421 1422 return ips->gfx_power + state2; 1423 } 1424 1425 static bool has_busy_stats(struct intel_rps *rps) 1426 { 1427 struct intel_engine_cs *engine; 1428 enum intel_engine_id id; 1429 1430 for_each_engine(engine, rps_to_gt(rps), id) { 1431 if (!intel_engine_supports_stats(engine)) 1432 return false; 1433 } 1434 1435 return true; 1436 } 1437 1438 void intel_rps_enable(struct intel_rps *rps) 1439 { 1440 struct drm_i915_private *i915 = rps_to_i915(rps); 1441 struct intel_uncore *uncore = rps_to_uncore(rps); 1442 bool enabled = false; 1443 1444 if (!HAS_RPS(i915)) 1445 return; 1446 1447 if (rps_uses_slpc(rps)) 1448 return; 1449 1450 intel_gt_check_clock_frequency(rps_to_gt(rps)); 1451 1452 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 1453 if (rps->max_freq <= rps->min_freq) 1454 /* leave disabled, no room for dynamic reclocking */; 1455 else if (IS_CHERRYVIEW(i915)) 1456 enabled = chv_rps_enable(rps); 1457 else if (IS_VALLEYVIEW(i915)) 1458 enabled = vlv_rps_enable(rps); 1459 else if (GRAPHICS_VER(i915) >= 9) 1460 enabled = gen9_rps_enable(rps); 1461 else if (GRAPHICS_VER(i915) >= 8) 1462 enabled = gen8_rps_enable(rps); 1463 else if (GRAPHICS_VER(i915) >= 6) 1464 enabled = gen6_rps_enable(rps); 1465 else if (IS_IRONLAKE_M(i915)) 1466 enabled = gen5_rps_enable(rps); 1467 else 1468 MISSING_CASE(GRAPHICS_VER(i915)); 1469 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 1470 if (!enabled) 1471 return; 1472 1473 GT_TRACE(rps_to_gt(rps), 1474 "min:%x, max:%x, freq:[%d, %d]\n", 1475 rps->min_freq, rps->max_freq, 1476 intel_gpu_freq(rps, rps->min_freq), 1477 intel_gpu_freq(rps, rps->max_freq)); 1478 1479 GEM_BUG_ON(rps->max_freq < rps->min_freq); 1480 GEM_BUG_ON(rps->idle_freq > rps->max_freq); 1481 1482 GEM_BUG_ON(rps->efficient_freq < rps->min_freq); 1483 GEM_BUG_ON(rps->efficient_freq > rps->max_freq); 1484 1485 if (has_busy_stats(rps)) 1486 intel_rps_set_timer(rps); 1487 else if (GRAPHICS_VER(i915) >= 6) 1488 intel_rps_set_interrupts(rps); 1489 else 1490 /* Ironlake currently uses intel_ips.ko */ {} 1491 1492 intel_rps_set_enabled(rps); 1493 } 1494 1495 static void gen6_rps_disable(struct intel_rps *rps) 1496 { 1497 set(rps_to_uncore(rps), GEN6_RP_CONTROL, 0); 1498 } 1499 1500 void intel_rps_disable(struct intel_rps *rps) 1501 { 1502 struct drm_i915_private *i915 = rps_to_i915(rps); 1503 1504 intel_rps_clear_enabled(rps); 1505 intel_rps_clear_interrupts(rps); 1506 intel_rps_clear_timer(rps); 1507 1508 if (GRAPHICS_VER(i915) >= 6) 1509 gen6_rps_disable(rps); 1510 else if (IS_IRONLAKE_M(i915)) 1511 gen5_rps_disable(rps); 1512 } 1513 1514 static int byt_gpu_freq(struct intel_rps *rps, int val) 1515 { 1516 /* 1517 * N = val - 0xb7 1518 * Slow = Fast = GPLL ref * N 1519 */ 1520 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000); 1521 } 1522 1523 static int byt_freq_opcode(struct intel_rps *rps, int val) 1524 { 1525 return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7; 1526 } 1527 1528 static int chv_gpu_freq(struct intel_rps *rps, int val) 1529 { 1530 /* 1531 * N = val / 2 1532 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2 1533 */ 1534 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000); 1535 } 1536 1537 static int chv_freq_opcode(struct intel_rps *rps, int val) 1538 { 1539 /* CHV needs even values */ 1540 return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2; 1541 } 1542 1543 int intel_gpu_freq(struct intel_rps *rps, int val) 1544 { 1545 struct drm_i915_private *i915 = rps_to_i915(rps); 1546 1547 if (GRAPHICS_VER(i915) >= 9) 1548 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, 1549 GEN9_FREQ_SCALER); 1550 else if (IS_CHERRYVIEW(i915)) 1551 return chv_gpu_freq(rps, val); 1552 else if (IS_VALLEYVIEW(i915)) 1553 return byt_gpu_freq(rps, val); 1554 else if (GRAPHICS_VER(i915) >= 6) 1555 return val * GT_FREQUENCY_MULTIPLIER; 1556 else 1557 return val; 1558 } 1559 1560 int intel_freq_opcode(struct intel_rps *rps, int val) 1561 { 1562 struct drm_i915_private *i915 = rps_to_i915(rps); 1563 1564 if (GRAPHICS_VER(i915) >= 9) 1565 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, 1566 GT_FREQUENCY_MULTIPLIER); 1567 else if (IS_CHERRYVIEW(i915)) 1568 return chv_freq_opcode(rps, val); 1569 else if (IS_VALLEYVIEW(i915)) 1570 return byt_freq_opcode(rps, val); 1571 else if (GRAPHICS_VER(i915) >= 6) 1572 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); 1573 else 1574 return val; 1575 } 1576 1577 static void vlv_init_gpll_ref_freq(struct intel_rps *rps) 1578 { 1579 struct drm_i915_private *i915 = rps_to_i915(rps); 1580 1581 rps->gpll_ref_freq = 1582 vlv_get_cck_clock(i915, "GPLL ref", 1583 CCK_GPLL_CLOCK_CONTROL, 1584 i915->czclk_freq); 1585 1586 drm_dbg(&i915->drm, "GPLL reference freq: %d kHz\n", 1587 rps->gpll_ref_freq); 1588 } 1589 1590 static void vlv_rps_init(struct intel_rps *rps) 1591 { 1592 struct drm_i915_private *i915 = rps_to_i915(rps); 1593 u32 val; 1594 1595 vlv_iosf_sb_get(i915, 1596 BIT(VLV_IOSF_SB_PUNIT) | 1597 BIT(VLV_IOSF_SB_NC) | 1598 BIT(VLV_IOSF_SB_CCK)); 1599 1600 vlv_init_gpll_ref_freq(rps); 1601 1602 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 1603 switch ((val >> 6) & 3) { 1604 case 0: 1605 case 1: 1606 i915->mem_freq = 800; 1607 break; 1608 case 2: 1609 i915->mem_freq = 1066; 1610 break; 1611 case 3: 1612 i915->mem_freq = 1333; 1613 break; 1614 } 1615 drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq); 1616 1617 rps->max_freq = vlv_rps_max_freq(rps); 1618 rps->rp0_freq = rps->max_freq; 1619 drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n", 1620 intel_gpu_freq(rps, rps->max_freq), rps->max_freq); 1621 1622 rps->efficient_freq = vlv_rps_rpe_freq(rps); 1623 drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n", 1624 intel_gpu_freq(rps, rps->efficient_freq), rps->efficient_freq); 1625 1626 rps->rp1_freq = vlv_rps_guar_freq(rps); 1627 drm_dbg(&i915->drm, "RP1(Guar Freq) GPU freq: %d MHz (%u)\n", 1628 intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq); 1629 1630 rps->min_freq = vlv_rps_min_freq(rps); 1631 drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n", 1632 intel_gpu_freq(rps, rps->min_freq), rps->min_freq); 1633 1634 vlv_iosf_sb_put(i915, 1635 BIT(VLV_IOSF_SB_PUNIT) | 1636 BIT(VLV_IOSF_SB_NC) | 1637 BIT(VLV_IOSF_SB_CCK)); 1638 } 1639 1640 static void chv_rps_init(struct intel_rps *rps) 1641 { 1642 struct drm_i915_private *i915 = rps_to_i915(rps); 1643 u32 val; 1644 1645 vlv_iosf_sb_get(i915, 1646 BIT(VLV_IOSF_SB_PUNIT) | 1647 BIT(VLV_IOSF_SB_NC) | 1648 BIT(VLV_IOSF_SB_CCK)); 1649 1650 vlv_init_gpll_ref_freq(rps); 1651 1652 val = vlv_cck_read(i915, CCK_FUSE_REG); 1653 1654 switch ((val >> 2) & 0x7) { 1655 case 3: 1656 i915->mem_freq = 2000; 1657 break; 1658 default: 1659 i915->mem_freq = 1600; 1660 break; 1661 } 1662 drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq); 1663 1664 rps->max_freq = chv_rps_max_freq(rps); 1665 rps->rp0_freq = rps->max_freq; 1666 drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n", 1667 intel_gpu_freq(rps, rps->max_freq), rps->max_freq); 1668 1669 rps->efficient_freq = chv_rps_rpe_freq(rps); 1670 drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n", 1671 intel_gpu_freq(rps, rps->efficient_freq), rps->efficient_freq); 1672 1673 rps->rp1_freq = chv_rps_guar_freq(rps); 1674 drm_dbg(&i915->drm, "RP1(Guar) GPU freq: %d MHz (%u)\n", 1675 intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq); 1676 1677 rps->min_freq = chv_rps_min_freq(rps); 1678 drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n", 1679 intel_gpu_freq(rps, rps->min_freq), rps->min_freq); 1680 1681 vlv_iosf_sb_put(i915, 1682 BIT(VLV_IOSF_SB_PUNIT) | 1683 BIT(VLV_IOSF_SB_NC) | 1684 BIT(VLV_IOSF_SB_CCK)); 1685 1686 drm_WARN_ONCE(&i915->drm, (rps->max_freq | rps->efficient_freq | 1687 rps->rp1_freq | rps->min_freq) & 1, 1688 "Odd GPU freq values\n"); 1689 } 1690 1691 static void vlv_c0_read(struct intel_uncore *uncore, struct intel_rps_ei *ei) 1692 { 1693 ei->ktime = ktime_get_raw(); 1694 ei->render_c0 = intel_uncore_read(uncore, VLV_RENDER_C0_COUNT); 1695 ei->media_c0 = intel_uncore_read(uncore, VLV_MEDIA_C0_COUNT); 1696 } 1697 1698 static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32 pm_iir) 1699 { 1700 struct intel_uncore *uncore = rps_to_uncore(rps); 1701 const struct intel_rps_ei *prev = &rps->ei; 1702 struct intel_rps_ei now; 1703 u32 events = 0; 1704 1705 if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0) 1706 return 0; 1707 1708 vlv_c0_read(uncore, &now); 1709 1710 if (prev->ktime) { 1711 u64 time, c0; 1712 u32 render, media; 1713 1714 time = ktime_us_delta(now.ktime, prev->ktime); 1715 1716 time *= rps_to_i915(rps)->czclk_freq; 1717 1718 /* Workload can be split between render + media, 1719 * e.g. SwapBuffers being blitted in X after being rendered in 1720 * mesa. To account for this we need to combine both engines 1721 * into our activity counter. 1722 */ 1723 render = now.render_c0 - prev->render_c0; 1724 media = now.media_c0 - prev->media_c0; 1725 c0 = max(render, media); 1726 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */ 1727 1728 if (c0 > time * rps->power.up_threshold) 1729 events = GEN6_PM_RP_UP_THRESHOLD; 1730 else if (c0 < time * rps->power.down_threshold) 1731 events = GEN6_PM_RP_DOWN_THRESHOLD; 1732 } 1733 1734 rps->ei = now; 1735 return events; 1736 } 1737 1738 static void rps_work(struct work_struct *work) 1739 { 1740 struct intel_rps *rps = container_of(work, typeof(*rps), work); 1741 struct intel_gt *gt = rps_to_gt(rps); 1742 struct drm_i915_private *i915 = rps_to_i915(rps); 1743 bool client_boost = false; 1744 int new_freq, adj, min, max; 1745 u32 pm_iir = 0; 1746 1747 spin_lock_irq(>->irq_lock); 1748 pm_iir = fetch_and_zero(&rps->pm_iir) & rps->pm_events; 1749 client_boost = atomic_read(&rps->num_waiters); 1750 spin_unlock_irq(>->irq_lock); 1751 1752 /* Make sure we didn't queue anything we're not going to process. */ 1753 if (!pm_iir && !client_boost) 1754 goto out; 1755 1756 mutex_lock(&rps->lock); 1757 if (!intel_rps_is_active(rps)) { 1758 mutex_unlock(&rps->lock); 1759 return; 1760 } 1761 1762 pm_iir |= vlv_wa_c0_ei(rps, pm_iir); 1763 1764 adj = rps->last_adj; 1765 new_freq = rps->cur_freq; 1766 min = rps->min_freq_softlimit; 1767 max = rps->max_freq_softlimit; 1768 if (client_boost) 1769 max = rps->max_freq; 1770 1771 GT_TRACE(gt, 1772 "pm_iir:%x, client_boost:%s, last:%d, cur:%x, min:%x, max:%x\n", 1773 pm_iir, yesno(client_boost), 1774 adj, new_freq, min, max); 1775 1776 if (client_boost && new_freq < rps->boost_freq) { 1777 new_freq = rps->boost_freq; 1778 adj = 0; 1779 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { 1780 if (adj > 0) 1781 adj *= 2; 1782 else /* CHV needs even encode values */ 1783 adj = IS_CHERRYVIEW(gt->i915) ? 2 : 1; 1784 1785 if (new_freq >= rps->max_freq_softlimit) 1786 adj = 0; 1787 } else if (client_boost) { 1788 adj = 0; 1789 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { 1790 if (rps->cur_freq > rps->efficient_freq) 1791 new_freq = rps->efficient_freq; 1792 else if (rps->cur_freq > rps->min_freq_softlimit) 1793 new_freq = rps->min_freq_softlimit; 1794 adj = 0; 1795 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { 1796 if (adj < 0) 1797 adj *= 2; 1798 else /* CHV needs even encode values */ 1799 adj = IS_CHERRYVIEW(gt->i915) ? -2 : -1; 1800 1801 if (new_freq <= rps->min_freq_softlimit) 1802 adj = 0; 1803 } else { /* unknown event */ 1804 adj = 0; 1805 } 1806 1807 /* 1808 * sysfs frequency limits may have snuck in while 1809 * servicing the interrupt 1810 */ 1811 new_freq += adj; 1812 new_freq = clamp_t(int, new_freq, min, max); 1813 1814 if (intel_rps_set(rps, new_freq)) { 1815 drm_dbg(&i915->drm, "Failed to set new GPU frequency\n"); 1816 adj = 0; 1817 } 1818 rps->last_adj = adj; 1819 1820 mutex_unlock(&rps->lock); 1821 1822 out: 1823 spin_lock_irq(>->irq_lock); 1824 gen6_gt_pm_unmask_irq(gt, rps->pm_events); 1825 spin_unlock_irq(>->irq_lock); 1826 } 1827 1828 void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) 1829 { 1830 struct intel_gt *gt = rps_to_gt(rps); 1831 const u32 events = rps->pm_events & pm_iir; 1832 1833 lockdep_assert_held(>->irq_lock); 1834 1835 if (unlikely(!events)) 1836 return; 1837 1838 GT_TRACE(gt, "irq events:%x\n", events); 1839 1840 gen6_gt_pm_mask_irq(gt, events); 1841 1842 rps->pm_iir |= events; 1843 schedule_work(&rps->work); 1844 } 1845 1846 void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) 1847 { 1848 struct intel_gt *gt = rps_to_gt(rps); 1849 u32 events; 1850 1851 events = pm_iir & rps->pm_events; 1852 if (events) { 1853 spin_lock(>->irq_lock); 1854 1855 GT_TRACE(gt, "irq events:%x\n", events); 1856 1857 gen6_gt_pm_mask_irq(gt, events); 1858 rps->pm_iir |= events; 1859 1860 schedule_work(&rps->work); 1861 spin_unlock(>->irq_lock); 1862 } 1863 1864 if (GRAPHICS_VER(gt->i915) >= 8) 1865 return; 1866 1867 if (pm_iir & PM_VEBOX_USER_INTERRUPT) 1868 intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10); 1869 1870 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) 1871 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); 1872 } 1873 1874 void gen5_rps_irq_handler(struct intel_rps *rps) 1875 { 1876 struct intel_uncore *uncore = rps_to_uncore(rps); 1877 u32 busy_up, busy_down, max_avg, min_avg; 1878 u8 new_freq; 1879 1880 spin_lock(&mchdev_lock); 1881 1882 intel_uncore_write16(uncore, 1883 MEMINTRSTS, 1884 intel_uncore_read(uncore, MEMINTRSTS)); 1885 1886 intel_uncore_write16(uncore, MEMINTRSTS, MEMINT_EVAL_CHG); 1887 busy_up = intel_uncore_read(uncore, RCPREVBSYTUPAVG); 1888 busy_down = intel_uncore_read(uncore, RCPREVBSYTDNAVG); 1889 max_avg = intel_uncore_read(uncore, RCBMAXAVG); 1890 min_avg = intel_uncore_read(uncore, RCBMINAVG); 1891 1892 /* Handle RCS change request from hw */ 1893 new_freq = rps->cur_freq; 1894 if (busy_up > max_avg) 1895 new_freq++; 1896 else if (busy_down < min_avg) 1897 new_freq--; 1898 new_freq = clamp(new_freq, 1899 rps->min_freq_softlimit, 1900 rps->max_freq_softlimit); 1901 1902 if (new_freq != rps->cur_freq && !__gen5_rps_set(rps, new_freq)) 1903 rps->cur_freq = new_freq; 1904 1905 spin_unlock(&mchdev_lock); 1906 } 1907 1908 void intel_rps_init_early(struct intel_rps *rps) 1909 { 1910 mutex_init(&rps->lock); 1911 mutex_init(&rps->power.mutex); 1912 1913 INIT_WORK(&rps->work, rps_work); 1914 timer_setup(&rps->timer, rps_timer, 0); 1915 1916 atomic_set(&rps->num_waiters, 0); 1917 } 1918 1919 void intel_rps_init(struct intel_rps *rps) 1920 { 1921 struct drm_i915_private *i915 = rps_to_i915(rps); 1922 1923 if (rps_uses_slpc(rps)) 1924 return; 1925 1926 if (IS_CHERRYVIEW(i915)) 1927 chv_rps_init(rps); 1928 else if (IS_VALLEYVIEW(i915)) 1929 vlv_rps_init(rps); 1930 else if (GRAPHICS_VER(i915) >= 6) 1931 gen6_rps_init(rps); 1932 else if (IS_IRONLAKE_M(i915)) 1933 gen5_rps_init(rps); 1934 1935 /* Derive initial user preferences/limits from the hardware limits */ 1936 rps->max_freq_softlimit = rps->max_freq; 1937 rps->min_freq_softlimit = rps->min_freq; 1938 1939 /* After setting max-softlimit, find the overclock max freq */ 1940 if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) { 1941 u32 params = 0; 1942 1943 sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS, 1944 ¶ms, NULL); 1945 if (params & BIT(31)) { /* OC supported */ 1946 drm_dbg(&i915->drm, 1947 "Overclocking supported, max: %dMHz, overclock: %dMHz\n", 1948 (rps->max_freq & 0xff) * 50, 1949 (params & 0xff) * 50); 1950 rps->max_freq = params & 0xff; 1951 } 1952 } 1953 1954 /* Finally allow us to boost to max by default */ 1955 rps->boost_freq = rps->max_freq; 1956 rps->idle_freq = rps->min_freq; 1957 1958 /* Start in the middle, from here we will autotune based on workload */ 1959 rps->cur_freq = rps->efficient_freq; 1960 1961 rps->pm_intrmsk_mbz = 0; 1962 1963 /* 1964 * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer 1965 * if GEN6_PM_UP_EI_EXPIRED is masked. 1966 * 1967 * TODO: verify if this can be reproduced on VLV,CHV. 1968 */ 1969 if (GRAPHICS_VER(i915) <= 7) 1970 rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; 1971 1972 if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) < 11) 1973 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; 1974 1975 /* GuC needs ARAT expired interrupt unmasked */ 1976 if (intel_uc_uses_guc_submission(&rps_to_gt(rps)->uc)) 1977 rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK; 1978 } 1979 1980 void intel_rps_sanitize(struct intel_rps *rps) 1981 { 1982 if (rps_uses_slpc(rps)) 1983 return; 1984 1985 if (GRAPHICS_VER(rps_to_i915(rps)) >= 6) 1986 rps_disable_interrupts(rps); 1987 } 1988 1989 u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) 1990 { 1991 struct drm_i915_private *i915 = rps_to_i915(rps); 1992 u32 cagf; 1993 1994 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 1995 cagf = (rpstat >> 8) & 0xff; 1996 else if (GRAPHICS_VER(i915) >= 9) 1997 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; 1998 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 1999 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; 2000 else if (GRAPHICS_VER(i915) >= 6) 2001 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; 2002 else 2003 cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >> 2004 MEMSTAT_PSTATE_SHIFT); 2005 2006 return cagf; 2007 } 2008 2009 static u32 read_cagf(struct intel_rps *rps) 2010 { 2011 struct drm_i915_private *i915 = rps_to_i915(rps); 2012 struct intel_uncore *uncore = rps_to_uncore(rps); 2013 u32 freq; 2014 2015 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 2016 vlv_punit_get(i915); 2017 freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 2018 vlv_punit_put(i915); 2019 } else if (GRAPHICS_VER(i915) >= 6) { 2020 freq = intel_uncore_read(uncore, GEN6_RPSTAT1); 2021 } else { 2022 freq = intel_uncore_read(uncore, MEMSTAT_ILK); 2023 } 2024 2025 return intel_rps_get_cagf(rps, freq); 2026 } 2027 2028 u32 intel_rps_read_actual_frequency(struct intel_rps *rps) 2029 { 2030 struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; 2031 intel_wakeref_t wakeref; 2032 u32 freq = 0; 2033 2034 with_intel_runtime_pm_if_in_use(rpm, wakeref) 2035 freq = intel_gpu_freq(rps, read_cagf(rps)); 2036 2037 return freq; 2038 } 2039 2040 u32 intel_rps_read_punit_req(struct intel_rps *rps) 2041 { 2042 struct intel_uncore *uncore = rps_to_uncore(rps); 2043 struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; 2044 intel_wakeref_t wakeref; 2045 u32 freq = 0; 2046 2047 with_intel_runtime_pm_if_in_use(rpm, wakeref) 2048 freq = intel_uncore_read(uncore, GEN6_RPNSWREQ); 2049 2050 return freq; 2051 } 2052 2053 static u32 intel_rps_get_req(u32 pureq) 2054 { 2055 u32 req = pureq >> GEN9_SW_REQ_UNSLICE_RATIO_SHIFT; 2056 2057 return req; 2058 } 2059 2060 u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps) 2061 { 2062 u32 freq = intel_rps_get_req(intel_rps_read_punit_req(rps)); 2063 2064 return intel_gpu_freq(rps, freq); 2065 } 2066 2067 u32 intel_rps_get_requested_frequency(struct intel_rps *rps) 2068 { 2069 if (rps_uses_slpc(rps)) 2070 return intel_rps_read_punit_req_frequency(rps); 2071 else 2072 return intel_gpu_freq(rps, rps->cur_freq); 2073 } 2074 2075 u32 intel_rps_get_max_frequency(struct intel_rps *rps) 2076 { 2077 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2078 2079 if (rps_uses_slpc(rps)) 2080 return slpc->max_freq_softlimit; 2081 else 2082 return intel_gpu_freq(rps, rps->max_freq_softlimit); 2083 } 2084 2085 u32 intel_rps_get_rp0_frequency(struct intel_rps *rps) 2086 { 2087 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2088 2089 if (rps_uses_slpc(rps)) 2090 return slpc->rp0_freq; 2091 else 2092 return intel_gpu_freq(rps, rps->rp0_freq); 2093 } 2094 2095 u32 intel_rps_get_rp1_frequency(struct intel_rps *rps) 2096 { 2097 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2098 2099 if (rps_uses_slpc(rps)) 2100 return slpc->rp1_freq; 2101 else 2102 return intel_gpu_freq(rps, rps->rp1_freq); 2103 } 2104 2105 u32 intel_rps_get_rpn_frequency(struct intel_rps *rps) 2106 { 2107 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2108 2109 if (rps_uses_slpc(rps)) 2110 return slpc->min_freq; 2111 else 2112 return intel_gpu_freq(rps, rps->min_freq); 2113 } 2114 2115 static int set_max_freq(struct intel_rps *rps, u32 val) 2116 { 2117 struct drm_i915_private *i915 = rps_to_i915(rps); 2118 int ret = 0; 2119 2120 mutex_lock(&rps->lock); 2121 2122 val = intel_freq_opcode(rps, val); 2123 if (val < rps->min_freq || 2124 val > rps->max_freq || 2125 val < rps->min_freq_softlimit) { 2126 ret = -EINVAL; 2127 goto unlock; 2128 } 2129 2130 if (val > rps->rp0_freq) 2131 drm_dbg(&i915->drm, "User requested overclocking to %d\n", 2132 intel_gpu_freq(rps, val)); 2133 2134 rps->max_freq_softlimit = val; 2135 2136 val = clamp_t(int, rps->cur_freq, 2137 rps->min_freq_softlimit, 2138 rps->max_freq_softlimit); 2139 2140 /* 2141 * We still need *_set_rps to process the new max_delay and 2142 * update the interrupt limits and PMINTRMSK even though 2143 * frequency request may be unchanged. 2144 */ 2145 intel_rps_set(rps, val); 2146 2147 unlock: 2148 mutex_unlock(&rps->lock); 2149 2150 return ret; 2151 } 2152 2153 int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val) 2154 { 2155 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2156 2157 if (rps_uses_slpc(rps)) 2158 return intel_guc_slpc_set_max_freq(slpc, val); 2159 else 2160 return set_max_freq(rps, val); 2161 } 2162 2163 u32 intel_rps_get_min_frequency(struct intel_rps *rps) 2164 { 2165 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2166 2167 if (rps_uses_slpc(rps)) 2168 return slpc->min_freq_softlimit; 2169 else 2170 return intel_gpu_freq(rps, rps->min_freq_softlimit); 2171 } 2172 2173 static int set_min_freq(struct intel_rps *rps, u32 val) 2174 { 2175 int ret = 0; 2176 2177 mutex_lock(&rps->lock); 2178 2179 val = intel_freq_opcode(rps, val); 2180 if (val < rps->min_freq || 2181 val > rps->max_freq || 2182 val > rps->max_freq_softlimit) { 2183 ret = -EINVAL; 2184 goto unlock; 2185 } 2186 2187 rps->min_freq_softlimit = val; 2188 2189 val = clamp_t(int, rps->cur_freq, 2190 rps->min_freq_softlimit, 2191 rps->max_freq_softlimit); 2192 2193 /* 2194 * We still need *_set_rps to process the new min_delay and 2195 * update the interrupt limits and PMINTRMSK even though 2196 * frequency request may be unchanged. 2197 */ 2198 intel_rps_set(rps, val); 2199 2200 unlock: 2201 mutex_unlock(&rps->lock); 2202 2203 return ret; 2204 } 2205 2206 int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val) 2207 { 2208 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2209 2210 if (rps_uses_slpc(rps)) 2211 return intel_guc_slpc_set_min_freq(slpc, val); 2212 else 2213 return set_min_freq(rps, val); 2214 } 2215 2216 u32 intel_rps_read_state_cap(struct intel_rps *rps) 2217 { 2218 struct drm_i915_private *i915 = rps_to_i915(rps); 2219 struct intel_uncore *uncore = rps_to_uncore(rps); 2220 2221 if (IS_XEHPSDV(i915)) 2222 return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP); 2223 else if (IS_GEN9_LP(i915)) 2224 return intel_uncore_read(uncore, BXT_RP_STATE_CAP); 2225 else 2226 return intel_uncore_read(uncore, GEN6_RP_STATE_CAP); 2227 } 2228 2229 static void intel_rps_set_manual(struct intel_rps *rps, bool enable) 2230 { 2231 struct intel_uncore *uncore = rps_to_uncore(rps); 2232 u32 state = enable ? GEN9_RPSWCTL_ENABLE : GEN9_RPSWCTL_DISABLE; 2233 2234 /* Allow punit to process software requests */ 2235 intel_uncore_write(uncore, GEN6_RP_CONTROL, state); 2236 } 2237 2238 void intel_rps_raise_unslice(struct intel_rps *rps) 2239 { 2240 struct intel_uncore *uncore = rps_to_uncore(rps); 2241 u32 rp0_unslice_req; 2242 2243 mutex_lock(&rps->lock); 2244 2245 if (rps_uses_slpc(rps)) { 2246 /* RP limits have not been initialized yet for SLPC path */ 2247 rp0_unslice_req = ((intel_rps_read_state_cap(rps) >> 0) 2248 & 0xff) * GEN9_FREQ_SCALER; 2249 2250 intel_rps_set_manual(rps, true); 2251 intel_uncore_write(uncore, GEN6_RPNSWREQ, 2252 ((rp0_unslice_req << 2253 GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) | 2254 GEN9_IGNORE_SLICE_RATIO)); 2255 intel_rps_set_manual(rps, false); 2256 } else { 2257 intel_rps_set(rps, rps->rp0_freq); 2258 } 2259 2260 mutex_unlock(&rps->lock); 2261 } 2262 2263 void intel_rps_lower_unslice(struct intel_rps *rps) 2264 { 2265 struct intel_uncore *uncore = rps_to_uncore(rps); 2266 u32 rpn_unslice_req; 2267 2268 mutex_lock(&rps->lock); 2269 2270 if (rps_uses_slpc(rps)) { 2271 /* RP limits have not been initialized yet for SLPC path */ 2272 rpn_unslice_req = ((intel_rps_read_state_cap(rps) >> 16) 2273 & 0xff) * GEN9_FREQ_SCALER; 2274 2275 intel_rps_set_manual(rps, true); 2276 intel_uncore_write(uncore, GEN6_RPNSWREQ, 2277 ((rpn_unslice_req << 2278 GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) | 2279 GEN9_IGNORE_SLICE_RATIO)); 2280 intel_rps_set_manual(rps, false); 2281 } else { 2282 intel_rps_set(rps, rps->min_freq); 2283 } 2284 2285 mutex_unlock(&rps->lock); 2286 } 2287 2288 /* External interface for intel_ips.ko */ 2289 2290 static struct drm_i915_private __rcu *ips_mchdev; 2291 2292 /** 2293 * Tells the intel_ips driver that the i915 driver is now loaded, if 2294 * IPS got loaded first. 2295 * 2296 * This awkward dance is so that neither module has to depend on the 2297 * other in order for IPS to do the appropriate communication of 2298 * GPU turbo limits to i915. 2299 */ 2300 static void 2301 ips_ping_for_i915_load(void) 2302 { 2303 void (*link)(void); 2304 2305 link = symbol_get(ips_link_to_i915_driver); 2306 if (link) { 2307 link(); 2308 symbol_put(ips_link_to_i915_driver); 2309 } 2310 } 2311 2312 void intel_rps_driver_register(struct intel_rps *rps) 2313 { 2314 struct intel_gt *gt = rps_to_gt(rps); 2315 2316 /* 2317 * We only register the i915 ips part with intel-ips once everything is 2318 * set up, to avoid intel-ips sneaking in and reading bogus values. 2319 */ 2320 if (GRAPHICS_VER(gt->i915) == 5) { 2321 GEM_BUG_ON(ips_mchdev); 2322 rcu_assign_pointer(ips_mchdev, gt->i915); 2323 ips_ping_for_i915_load(); 2324 } 2325 } 2326 2327 void intel_rps_driver_unregister(struct intel_rps *rps) 2328 { 2329 if (rcu_access_pointer(ips_mchdev) == rps_to_i915(rps)) 2330 rcu_assign_pointer(ips_mchdev, NULL); 2331 } 2332 2333 static struct drm_i915_private *mchdev_get(void) 2334 { 2335 struct drm_i915_private *i915; 2336 2337 rcu_read_lock(); 2338 i915 = rcu_dereference(ips_mchdev); 2339 if (i915 && !kref_get_unless_zero(&i915->drm.ref)) 2340 i915 = NULL; 2341 rcu_read_unlock(); 2342 2343 return i915; 2344 } 2345 2346 /** 2347 * i915_read_mch_val - return value for IPS use 2348 * 2349 * Calculate and return a value for the IPS driver to use when deciding whether 2350 * we have thermal and power headroom to increase CPU or GPU power budget. 2351 */ 2352 unsigned long i915_read_mch_val(void) 2353 { 2354 struct drm_i915_private *i915; 2355 unsigned long chipset_val = 0; 2356 unsigned long graphics_val = 0; 2357 intel_wakeref_t wakeref; 2358 2359 i915 = mchdev_get(); 2360 if (!i915) 2361 return 0; 2362 2363 with_intel_runtime_pm(&i915->runtime_pm, wakeref) { 2364 struct intel_ips *ips = &to_gt(i915)->rps.ips; 2365 2366 spin_lock_irq(&mchdev_lock); 2367 chipset_val = __ips_chipset_val(ips); 2368 graphics_val = __ips_gfx_val(ips); 2369 spin_unlock_irq(&mchdev_lock); 2370 } 2371 2372 drm_dev_put(&i915->drm); 2373 return chipset_val + graphics_val; 2374 } 2375 EXPORT_SYMBOL_GPL(i915_read_mch_val); 2376 2377 /** 2378 * i915_gpu_raise - raise GPU frequency limit 2379 * 2380 * Raise the limit; IPS indicates we have thermal headroom. 2381 */ 2382 bool i915_gpu_raise(void) 2383 { 2384 struct drm_i915_private *i915; 2385 struct intel_rps *rps; 2386 2387 i915 = mchdev_get(); 2388 if (!i915) 2389 return false; 2390 2391 rps = &to_gt(i915)->rps; 2392 2393 spin_lock_irq(&mchdev_lock); 2394 if (rps->max_freq_softlimit < rps->max_freq) 2395 rps->max_freq_softlimit++; 2396 spin_unlock_irq(&mchdev_lock); 2397 2398 drm_dev_put(&i915->drm); 2399 return true; 2400 } 2401 EXPORT_SYMBOL_GPL(i915_gpu_raise); 2402 2403 /** 2404 * i915_gpu_lower - lower GPU frequency limit 2405 * 2406 * IPS indicates we're close to a thermal limit, so throttle back the GPU 2407 * frequency maximum. 2408 */ 2409 bool i915_gpu_lower(void) 2410 { 2411 struct drm_i915_private *i915; 2412 struct intel_rps *rps; 2413 2414 i915 = mchdev_get(); 2415 if (!i915) 2416 return false; 2417 2418 rps = &to_gt(i915)->rps; 2419 2420 spin_lock_irq(&mchdev_lock); 2421 if (rps->max_freq_softlimit > rps->min_freq) 2422 rps->max_freq_softlimit--; 2423 spin_unlock_irq(&mchdev_lock); 2424 2425 drm_dev_put(&i915->drm); 2426 return true; 2427 } 2428 EXPORT_SYMBOL_GPL(i915_gpu_lower); 2429 2430 /** 2431 * i915_gpu_busy - indicate GPU business to IPS 2432 * 2433 * Tell the IPS driver whether or not the GPU is busy. 2434 */ 2435 bool i915_gpu_busy(void) 2436 { 2437 struct drm_i915_private *i915; 2438 bool ret; 2439 2440 i915 = mchdev_get(); 2441 if (!i915) 2442 return false; 2443 2444 ret = to_gt(i915)->awake; 2445 2446 drm_dev_put(&i915->drm); 2447 return ret; 2448 } 2449 EXPORT_SYMBOL_GPL(i915_gpu_busy); 2450 2451 /** 2452 * i915_gpu_turbo_disable - disable graphics turbo 2453 * 2454 * Disable graphics turbo by resetting the max frequency and setting the 2455 * current frequency to the default. 2456 */ 2457 bool i915_gpu_turbo_disable(void) 2458 { 2459 struct drm_i915_private *i915; 2460 struct intel_rps *rps; 2461 bool ret; 2462 2463 i915 = mchdev_get(); 2464 if (!i915) 2465 return false; 2466 2467 rps = &to_gt(i915)->rps; 2468 2469 spin_lock_irq(&mchdev_lock); 2470 rps->max_freq_softlimit = rps->min_freq; 2471 ret = !__gen5_rps_set(&to_gt(i915)->rps, rps->min_freq); 2472 spin_unlock_irq(&mchdev_lock); 2473 2474 drm_dev_put(&i915->drm); 2475 return ret; 2476 } 2477 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); 2478 2479 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2480 #include "selftest_rps.c" 2481 #include "selftest_slpc.c" 2482 #endif 2483