1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include <drm/i915_drm.h> 9 10 #include "i915_drv.h" 11 #include "i915_irq.h" 12 #include "intel_breadcrumbs.h" 13 #include "intel_gt.h" 14 #include "intel_gt_clock_utils.h" 15 #include "intel_gt_irq.h" 16 #include "intel_gt_pm_irq.h" 17 #include "intel_gt_regs.h" 18 #include "intel_mchbar_regs.h" 19 #include "intel_pcode.h" 20 #include "intel_rps.h" 21 #include "vlv_sideband.h" 22 #include "../../../platform/x86/intel_ips.h" 23 24 #define BUSY_MAX_EI 20u /* ms */ 25 26 /* 27 * Lock protecting IPS related data structures 28 */ 29 static DEFINE_SPINLOCK(mchdev_lock); 30 31 static struct intel_gt *rps_to_gt(struct intel_rps *rps) 32 { 33 return container_of(rps, struct intel_gt, rps); 34 } 35 36 static struct drm_i915_private *rps_to_i915(struct intel_rps *rps) 37 { 38 return rps_to_gt(rps)->i915; 39 } 40 41 static struct intel_uncore *rps_to_uncore(struct intel_rps *rps) 42 { 43 return rps_to_gt(rps)->uncore; 44 } 45 46 static struct intel_guc_slpc *rps_to_slpc(struct intel_rps *rps) 47 { 48 struct intel_gt *gt = rps_to_gt(rps); 49 50 return >->uc.guc.slpc; 51 } 52 53 static bool rps_uses_slpc(struct intel_rps *rps) 54 { 55 struct intel_gt *gt = rps_to_gt(rps); 56 57 return intel_uc_uses_guc_slpc(>->uc); 58 } 59 60 static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask) 61 { 62 return mask & ~rps->pm_intrmsk_mbz; 63 } 64 65 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) 66 { 67 intel_uncore_write_fw(uncore, reg, val); 68 } 69 70 static void rps_timer(struct timer_list *t) 71 { 72 struct intel_rps *rps = from_timer(rps, t, timer); 73 struct intel_engine_cs *engine; 74 ktime_t dt, last, timestamp; 75 enum intel_engine_id id; 76 s64 max_busy[3] = {}; 77 78 timestamp = 0; 79 for_each_engine(engine, rps_to_gt(rps), id) { 80 s64 busy; 81 int i; 82 83 dt = intel_engine_get_busy_time(engine, ×tamp); 84 last = engine->stats.rps; 85 engine->stats.rps = dt; 86 87 busy = ktime_to_ns(ktime_sub(dt, last)); 88 for (i = 0; i < ARRAY_SIZE(max_busy); i++) { 89 if (busy > max_busy[i]) 90 swap(busy, max_busy[i]); 91 } 92 } 93 last = rps->pm_timestamp; 94 rps->pm_timestamp = timestamp; 95 96 if (intel_rps_is_active(rps)) { 97 s64 busy; 98 int i; 99 100 dt = ktime_sub(timestamp, last); 101 102 /* 103 * Our goal is to evaluate each engine independently, so we run 104 * at the lowest clocks required to sustain the heaviest 105 * workload. However, a task may be split into sequential 106 * dependent operations across a set of engines, such that 107 * the independent contributions do not account for high load, 108 * but overall the task is GPU bound. For example, consider 109 * video decode on vcs followed by colour post-processing 110 * on vecs, followed by general post-processing on rcs. 111 * Since multi-engines being active does imply a single 112 * continuous workload across all engines, we hedge our 113 * bets by only contributing a factor of the distributed 114 * load into our busyness calculation. 115 */ 116 busy = max_busy[0]; 117 for (i = 1; i < ARRAY_SIZE(max_busy); i++) { 118 if (!max_busy[i]) 119 break; 120 121 busy += div_u64(max_busy[i], 1 << i); 122 } 123 GT_TRACE(rps_to_gt(rps), 124 "busy:%lld [%d%%], max:[%lld, %lld, %lld], interval:%d\n", 125 busy, (int)div64_u64(100 * busy, dt), 126 max_busy[0], max_busy[1], max_busy[2], 127 rps->pm_interval); 128 129 if (100 * busy > rps->power.up_threshold * dt && 130 rps->cur_freq < rps->max_freq_softlimit) { 131 rps->pm_iir |= GEN6_PM_RP_UP_THRESHOLD; 132 rps->pm_interval = 1; 133 schedule_work(&rps->work); 134 } else if (100 * busy < rps->power.down_threshold * dt && 135 rps->cur_freq > rps->min_freq_softlimit) { 136 rps->pm_iir |= GEN6_PM_RP_DOWN_THRESHOLD; 137 rps->pm_interval = 1; 138 schedule_work(&rps->work); 139 } else { 140 rps->last_adj = 0; 141 } 142 143 mod_timer(&rps->timer, 144 jiffies + msecs_to_jiffies(rps->pm_interval)); 145 rps->pm_interval = min(rps->pm_interval * 2, BUSY_MAX_EI); 146 } 147 } 148 149 static void rps_start_timer(struct intel_rps *rps) 150 { 151 rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp); 152 rps->pm_interval = 1; 153 mod_timer(&rps->timer, jiffies + 1); 154 } 155 156 static void rps_stop_timer(struct intel_rps *rps) 157 { 158 del_timer_sync(&rps->timer); 159 rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp); 160 cancel_work_sync(&rps->work); 161 } 162 163 static u32 rps_pm_mask(struct intel_rps *rps, u8 val) 164 { 165 u32 mask = 0; 166 167 /* We use UP_EI_EXPIRED interrupts for both up/down in manual mode */ 168 if (val > rps->min_freq_softlimit) 169 mask |= (GEN6_PM_RP_UP_EI_EXPIRED | 170 GEN6_PM_RP_DOWN_THRESHOLD | 171 GEN6_PM_RP_DOWN_TIMEOUT); 172 173 if (val < rps->max_freq_softlimit) 174 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; 175 176 mask &= rps->pm_events; 177 178 return rps_pm_sanitize_mask(rps, ~mask); 179 } 180 181 static void rps_reset_ei(struct intel_rps *rps) 182 { 183 memset(&rps->ei, 0, sizeof(rps->ei)); 184 } 185 186 static void rps_enable_interrupts(struct intel_rps *rps) 187 { 188 struct intel_gt *gt = rps_to_gt(rps); 189 190 GEM_BUG_ON(rps_uses_slpc(rps)); 191 192 GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n", 193 rps->pm_events, rps_pm_mask(rps, rps->last_freq)); 194 195 rps_reset_ei(rps); 196 197 spin_lock_irq(>->irq_lock); 198 gen6_gt_pm_enable_irq(gt, rps->pm_events); 199 spin_unlock_irq(>->irq_lock); 200 201 intel_uncore_write(gt->uncore, 202 GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq)); 203 } 204 205 static void gen6_rps_reset_interrupts(struct intel_rps *rps) 206 { 207 gen6_gt_pm_reset_iir(rps_to_gt(rps), GEN6_PM_RPS_EVENTS); 208 } 209 210 static void gen11_rps_reset_interrupts(struct intel_rps *rps) 211 { 212 while (gen11_gt_reset_one_iir(rps_to_gt(rps), 0, GEN11_GTPM)) 213 ; 214 } 215 216 static void rps_reset_interrupts(struct intel_rps *rps) 217 { 218 struct intel_gt *gt = rps_to_gt(rps); 219 220 spin_lock_irq(>->irq_lock); 221 if (GRAPHICS_VER(gt->i915) >= 11) 222 gen11_rps_reset_interrupts(rps); 223 else 224 gen6_rps_reset_interrupts(rps); 225 226 rps->pm_iir = 0; 227 spin_unlock_irq(>->irq_lock); 228 } 229 230 static void rps_disable_interrupts(struct intel_rps *rps) 231 { 232 struct intel_gt *gt = rps_to_gt(rps); 233 234 intel_uncore_write(gt->uncore, 235 GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u)); 236 237 spin_lock_irq(>->irq_lock); 238 gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS); 239 spin_unlock_irq(>->irq_lock); 240 241 intel_synchronize_irq(gt->i915); 242 243 /* 244 * Now that we will not be generating any more work, flush any 245 * outstanding tasks. As we are called on the RPS idle path, 246 * we will reset the GPU to minimum frequencies, so the current 247 * state of the worker can be discarded. 248 */ 249 cancel_work_sync(&rps->work); 250 251 rps_reset_interrupts(rps); 252 GT_TRACE(gt, "interrupts:off\n"); 253 } 254 255 static const struct cparams { 256 u16 i; 257 u16 t; 258 u16 m; 259 u16 c; 260 } cparams[] = { 261 { 1, 1333, 301, 28664 }, 262 { 1, 1066, 294, 24460 }, 263 { 1, 800, 294, 25192 }, 264 { 0, 1333, 276, 27605 }, 265 { 0, 1066, 276, 27605 }, 266 { 0, 800, 231, 23784 }, 267 }; 268 269 static void gen5_rps_init(struct intel_rps *rps) 270 { 271 struct drm_i915_private *i915 = rps_to_i915(rps); 272 struct intel_uncore *uncore = rps_to_uncore(rps); 273 u8 fmax, fmin, fstart; 274 u32 rgvmodectl; 275 int c_m, i; 276 277 if (i915->fsb_freq <= 3200) 278 c_m = 0; 279 else if (i915->fsb_freq <= 4800) 280 c_m = 1; 281 else 282 c_m = 2; 283 284 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 285 if (cparams[i].i == c_m && cparams[i].t == i915->mem_freq) { 286 rps->ips.m = cparams[i].m; 287 rps->ips.c = cparams[i].c; 288 break; 289 } 290 } 291 292 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); 293 294 /* Set up min, max, and cur for interrupt handling */ 295 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 296 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 297 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 298 MEMMODE_FSTART_SHIFT; 299 drm_dbg(&i915->drm, "fmax: %d, fmin: %d, fstart: %d\n", 300 fmax, fmin, fstart); 301 302 rps->min_freq = fmax; 303 rps->efficient_freq = fstart; 304 rps->max_freq = fmin; 305 } 306 307 static unsigned long 308 __ips_chipset_val(struct intel_ips *ips) 309 { 310 struct intel_uncore *uncore = 311 rps_to_uncore(container_of(ips, struct intel_rps, ips)); 312 unsigned long now = jiffies_to_msecs(jiffies), dt; 313 unsigned long result; 314 u64 total, delta; 315 316 lockdep_assert_held(&mchdev_lock); 317 318 /* 319 * Prevent division-by-zero if we are asking too fast. 320 * Also, we don't get interesting results if we are polling 321 * faster than once in 10ms, so just return the saved value 322 * in such cases. 323 */ 324 dt = now - ips->last_time1; 325 if (dt <= 10) 326 return ips->chipset_power; 327 328 /* FIXME: handle per-counter overflow */ 329 total = intel_uncore_read(uncore, DMIEC); 330 total += intel_uncore_read(uncore, DDREC); 331 total += intel_uncore_read(uncore, CSIEC); 332 333 delta = total - ips->last_count1; 334 335 result = div_u64(div_u64(ips->m * delta, dt) + ips->c, 10); 336 337 ips->last_count1 = total; 338 ips->last_time1 = now; 339 340 ips->chipset_power = result; 341 342 return result; 343 } 344 345 static unsigned long ips_mch_val(struct intel_uncore *uncore) 346 { 347 unsigned int m, x, b; 348 u32 tsfs; 349 350 tsfs = intel_uncore_read(uncore, TSFS); 351 x = intel_uncore_read8(uncore, TR1); 352 353 b = tsfs & TSFS_INTR_MASK; 354 m = (tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT; 355 356 return m * x / 127 - b; 357 } 358 359 static int _pxvid_to_vd(u8 pxvid) 360 { 361 if (pxvid == 0) 362 return 0; 363 364 if (pxvid >= 8 && pxvid < 31) 365 pxvid = 31; 366 367 return (pxvid + 2) * 125; 368 } 369 370 static u32 pvid_to_extvid(struct drm_i915_private *i915, u8 pxvid) 371 { 372 const int vd = _pxvid_to_vd(pxvid); 373 374 if (INTEL_INFO(i915)->is_mobile) 375 return max(vd - 1125, 0); 376 377 return vd; 378 } 379 380 static void __gen5_ips_update(struct intel_ips *ips) 381 { 382 struct intel_uncore *uncore = 383 rps_to_uncore(container_of(ips, struct intel_rps, ips)); 384 u64 now, delta, dt; 385 u32 count; 386 387 lockdep_assert_held(&mchdev_lock); 388 389 now = ktime_get_raw_ns(); 390 dt = now - ips->last_time2; 391 do_div(dt, NSEC_PER_MSEC); 392 393 /* Don't divide by 0 */ 394 if (dt <= 10) 395 return; 396 397 count = intel_uncore_read(uncore, GFXEC); 398 delta = count - ips->last_count2; 399 400 ips->last_count2 = count; 401 ips->last_time2 = now; 402 403 /* More magic constants... */ 404 ips->gfx_power = div_u64(delta * 1181, dt * 10); 405 } 406 407 static void gen5_rps_update(struct intel_rps *rps) 408 { 409 spin_lock_irq(&mchdev_lock); 410 __gen5_ips_update(&rps->ips); 411 spin_unlock_irq(&mchdev_lock); 412 } 413 414 static unsigned int gen5_invert_freq(struct intel_rps *rps, 415 unsigned int val) 416 { 417 /* Invert the frequency bin into an ips delay */ 418 val = rps->max_freq - val; 419 val = rps->min_freq + val; 420 421 return val; 422 } 423 424 static int __gen5_rps_set(struct intel_rps *rps, u8 val) 425 { 426 struct intel_uncore *uncore = rps_to_uncore(rps); 427 u16 rgvswctl; 428 429 lockdep_assert_held(&mchdev_lock); 430 431 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); 432 if (rgvswctl & MEMCTL_CMD_STS) { 433 DRM_DEBUG("gpu busy, RCS change rejected\n"); 434 return -EBUSY; /* still busy with another command */ 435 } 436 437 /* Invert the frequency bin into an ips delay */ 438 val = gen5_invert_freq(rps, val); 439 440 rgvswctl = 441 (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 442 (val << MEMCTL_FREQ_SHIFT) | 443 MEMCTL_SFCAVM; 444 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl); 445 intel_uncore_posting_read16(uncore, MEMSWCTL); 446 447 rgvswctl |= MEMCTL_CMD_STS; 448 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl); 449 450 return 0; 451 } 452 453 static int gen5_rps_set(struct intel_rps *rps, u8 val) 454 { 455 int err; 456 457 spin_lock_irq(&mchdev_lock); 458 err = __gen5_rps_set(rps, val); 459 spin_unlock_irq(&mchdev_lock); 460 461 return err; 462 } 463 464 static unsigned long intel_pxfreq(u32 vidfreq) 465 { 466 int div = (vidfreq & 0x3f0000) >> 16; 467 int post = (vidfreq & 0x3000) >> 12; 468 int pre = (vidfreq & 0x7); 469 470 if (!pre) 471 return 0; 472 473 return div * 133333 / (pre << post); 474 } 475 476 static unsigned int init_emon(struct intel_uncore *uncore) 477 { 478 u8 pxw[16]; 479 int i; 480 481 /* Disable to program */ 482 intel_uncore_write(uncore, ECR, 0); 483 intel_uncore_posting_read(uncore, ECR); 484 485 /* Program energy weights for various events */ 486 intel_uncore_write(uncore, SDEW, 0x15040d00); 487 intel_uncore_write(uncore, CSIEW0, 0x007f0000); 488 intel_uncore_write(uncore, CSIEW1, 0x1e220004); 489 intel_uncore_write(uncore, CSIEW2, 0x04000004); 490 491 for (i = 0; i < 5; i++) 492 intel_uncore_write(uncore, PEW(i), 0); 493 for (i = 0; i < 3; i++) 494 intel_uncore_write(uncore, DEW(i), 0); 495 496 /* Program P-state weights to account for frequency power adjustment */ 497 for (i = 0; i < 16; i++) { 498 u32 pxvidfreq = intel_uncore_read(uncore, PXVFREQ(i)); 499 unsigned int freq = intel_pxfreq(pxvidfreq); 500 unsigned int vid = 501 (pxvidfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT; 502 unsigned int val; 503 504 val = vid * vid * freq / 1000 * 255; 505 val /= 127 * 127 * 900; 506 507 pxw[i] = val; 508 } 509 /* Render standby states get 0 weight */ 510 pxw[14] = 0; 511 pxw[15] = 0; 512 513 for (i = 0; i < 4; i++) { 514 intel_uncore_write(uncore, PXW(i), 515 pxw[i * 4 + 0] << 24 | 516 pxw[i * 4 + 1] << 16 | 517 pxw[i * 4 + 2] << 8 | 518 pxw[i * 4 + 3] << 0); 519 } 520 521 /* Adjust magic regs to magic values (more experimental results) */ 522 intel_uncore_write(uncore, OGW0, 0); 523 intel_uncore_write(uncore, OGW1, 0); 524 intel_uncore_write(uncore, EG0, 0x00007f00); 525 intel_uncore_write(uncore, EG1, 0x0000000e); 526 intel_uncore_write(uncore, EG2, 0x000e0000); 527 intel_uncore_write(uncore, EG3, 0x68000300); 528 intel_uncore_write(uncore, EG4, 0x42000000); 529 intel_uncore_write(uncore, EG5, 0x00140031); 530 intel_uncore_write(uncore, EG6, 0); 531 intel_uncore_write(uncore, EG7, 0); 532 533 for (i = 0; i < 8; i++) 534 intel_uncore_write(uncore, PXWL(i), 0); 535 536 /* Enable PMON + select events */ 537 intel_uncore_write(uncore, ECR, 0x80000019); 538 539 return intel_uncore_read(uncore, LCFUSE02) & LCFUSE_HIV_MASK; 540 } 541 542 static bool gen5_rps_enable(struct intel_rps *rps) 543 { 544 struct drm_i915_private *i915 = rps_to_i915(rps); 545 struct intel_uncore *uncore = rps_to_uncore(rps); 546 u8 fstart, vstart; 547 u32 rgvmodectl; 548 549 spin_lock_irq(&mchdev_lock); 550 551 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); 552 553 /* Enable temp reporting */ 554 intel_uncore_write16(uncore, PMMISC, 555 intel_uncore_read16(uncore, PMMISC) | MCPPCE_EN); 556 intel_uncore_write16(uncore, TSC1, 557 intel_uncore_read16(uncore, TSC1) | TSE); 558 559 /* 100ms RC evaluation intervals */ 560 intel_uncore_write(uncore, RCUPEI, 100000); 561 intel_uncore_write(uncore, RCDNEI, 100000); 562 563 /* Set max/min thresholds to 90ms and 80ms respectively */ 564 intel_uncore_write(uncore, RCBMAXAVG, 90000); 565 intel_uncore_write(uncore, RCBMINAVG, 80000); 566 567 intel_uncore_write(uncore, MEMIHYST, 1); 568 569 /* Set up min, max, and cur for interrupt handling */ 570 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 571 MEMMODE_FSTART_SHIFT; 572 573 vstart = (intel_uncore_read(uncore, PXVFREQ(fstart)) & 574 PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT; 575 576 intel_uncore_write(uncore, 577 MEMINTREN, 578 MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 579 580 intel_uncore_write(uncore, VIDSTART, vstart); 581 intel_uncore_posting_read(uncore, VIDSTART); 582 583 rgvmodectl |= MEMMODE_SWMODE_EN; 584 intel_uncore_write(uncore, MEMMODECTL, rgvmodectl); 585 586 if (wait_for_atomic((intel_uncore_read(uncore, MEMSWCTL) & 587 MEMCTL_CMD_STS) == 0, 10)) 588 drm_err(&uncore->i915->drm, 589 "stuck trying to change perf mode\n"); 590 mdelay(1); 591 592 __gen5_rps_set(rps, rps->cur_freq); 593 594 rps->ips.last_count1 = intel_uncore_read(uncore, DMIEC); 595 rps->ips.last_count1 += intel_uncore_read(uncore, DDREC); 596 rps->ips.last_count1 += intel_uncore_read(uncore, CSIEC); 597 rps->ips.last_time1 = jiffies_to_msecs(jiffies); 598 599 rps->ips.last_count2 = intel_uncore_read(uncore, GFXEC); 600 rps->ips.last_time2 = ktime_get_raw_ns(); 601 602 spin_lock(&i915->irq_lock); 603 ilk_enable_display_irq(i915, DE_PCU_EVENT); 604 spin_unlock(&i915->irq_lock); 605 606 spin_unlock_irq(&mchdev_lock); 607 608 rps->ips.corr = init_emon(uncore); 609 610 return true; 611 } 612 613 static void gen5_rps_disable(struct intel_rps *rps) 614 { 615 struct drm_i915_private *i915 = rps_to_i915(rps); 616 struct intel_uncore *uncore = rps_to_uncore(rps); 617 u16 rgvswctl; 618 619 spin_lock_irq(&mchdev_lock); 620 621 spin_lock(&i915->irq_lock); 622 ilk_disable_display_irq(i915, DE_PCU_EVENT); 623 spin_unlock(&i915->irq_lock); 624 625 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); 626 627 /* Ack interrupts, disable EFC interrupt */ 628 intel_uncore_write(uncore, MEMINTREN, 629 intel_uncore_read(uncore, MEMINTREN) & 630 ~MEMINT_EVAL_CHG_EN); 631 intel_uncore_write(uncore, MEMINTRSTS, MEMINT_EVAL_CHG); 632 633 /* Go back to the starting frequency */ 634 __gen5_rps_set(rps, rps->idle_freq); 635 mdelay(1); 636 rgvswctl |= MEMCTL_CMD_STS; 637 intel_uncore_write(uncore, MEMSWCTL, rgvswctl); 638 mdelay(1); 639 640 spin_unlock_irq(&mchdev_lock); 641 } 642 643 static u32 rps_limits(struct intel_rps *rps, u8 val) 644 { 645 u32 limits; 646 647 /* 648 * Only set the down limit when we've reached the lowest level to avoid 649 * getting more interrupts, otherwise leave this clear. This prevents a 650 * race in the hw when coming out of rc6: There's a tiny window where 651 * the hw runs at the minimal clock before selecting the desired 652 * frequency, if the down threshold expires in that window we will not 653 * receive a down interrupt. 654 */ 655 if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) { 656 limits = rps->max_freq_softlimit << 23; 657 if (val <= rps->min_freq_softlimit) 658 limits |= rps->min_freq_softlimit << 14; 659 } else { 660 limits = rps->max_freq_softlimit << 24; 661 if (val <= rps->min_freq_softlimit) 662 limits |= rps->min_freq_softlimit << 16; 663 } 664 665 return limits; 666 } 667 668 static void rps_set_power(struct intel_rps *rps, int new_power) 669 { 670 struct intel_gt *gt = rps_to_gt(rps); 671 struct intel_uncore *uncore = gt->uncore; 672 u32 threshold_up = 0, threshold_down = 0; /* in % */ 673 u32 ei_up = 0, ei_down = 0; 674 675 lockdep_assert_held(&rps->power.mutex); 676 677 if (new_power == rps->power.mode) 678 return; 679 680 threshold_up = 95; 681 threshold_down = 85; 682 683 /* Note the units here are not exactly 1us, but 1280ns. */ 684 switch (new_power) { 685 case LOW_POWER: 686 ei_up = 16000; 687 ei_down = 32000; 688 break; 689 690 case BETWEEN: 691 ei_up = 13000; 692 ei_down = 32000; 693 break; 694 695 case HIGH_POWER: 696 ei_up = 10000; 697 ei_down = 32000; 698 break; 699 } 700 701 /* When byt can survive without system hang with dynamic 702 * sw freq adjustments, this restriction can be lifted. 703 */ 704 if (IS_VALLEYVIEW(gt->i915)) 705 goto skip_hw_write; 706 707 GT_TRACE(gt, 708 "changing power mode [%d], up %d%% @ %dus, down %d%% @ %dus\n", 709 new_power, threshold_up, ei_up, threshold_down, ei_down); 710 711 set(uncore, GEN6_RP_UP_EI, 712 intel_gt_ns_to_pm_interval(gt, ei_up * 1000)); 713 set(uncore, GEN6_RP_UP_THRESHOLD, 714 intel_gt_ns_to_pm_interval(gt, ei_up * threshold_up * 10)); 715 716 set(uncore, GEN6_RP_DOWN_EI, 717 intel_gt_ns_to_pm_interval(gt, ei_down * 1000)); 718 set(uncore, GEN6_RP_DOWN_THRESHOLD, 719 intel_gt_ns_to_pm_interval(gt, ei_down * threshold_down * 10)); 720 721 set(uncore, GEN6_RP_CONTROL, 722 (GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) | 723 GEN6_RP_MEDIA_HW_NORMAL_MODE | 724 GEN6_RP_MEDIA_IS_GFX | 725 GEN6_RP_ENABLE | 726 GEN6_RP_UP_BUSY_AVG | 727 GEN6_RP_DOWN_IDLE_AVG); 728 729 skip_hw_write: 730 rps->power.mode = new_power; 731 rps->power.up_threshold = threshold_up; 732 rps->power.down_threshold = threshold_down; 733 } 734 735 static void gen6_rps_set_thresholds(struct intel_rps *rps, u8 val) 736 { 737 int new_power; 738 739 new_power = rps->power.mode; 740 switch (rps->power.mode) { 741 case LOW_POWER: 742 if (val > rps->efficient_freq + 1 && 743 val > rps->cur_freq) 744 new_power = BETWEEN; 745 break; 746 747 case BETWEEN: 748 if (val <= rps->efficient_freq && 749 val < rps->cur_freq) 750 new_power = LOW_POWER; 751 else if (val >= rps->rp0_freq && 752 val > rps->cur_freq) 753 new_power = HIGH_POWER; 754 break; 755 756 case HIGH_POWER: 757 if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 && 758 val < rps->cur_freq) 759 new_power = BETWEEN; 760 break; 761 } 762 /* Max/min bins are special */ 763 if (val <= rps->min_freq_softlimit) 764 new_power = LOW_POWER; 765 if (val >= rps->max_freq_softlimit) 766 new_power = HIGH_POWER; 767 768 mutex_lock(&rps->power.mutex); 769 if (rps->power.interactive) 770 new_power = HIGH_POWER; 771 rps_set_power(rps, new_power); 772 mutex_unlock(&rps->power.mutex); 773 } 774 775 void intel_rps_mark_interactive(struct intel_rps *rps, bool interactive) 776 { 777 GT_TRACE(rps_to_gt(rps), "mark interactive: %s\n", 778 str_yes_no(interactive)); 779 780 mutex_lock(&rps->power.mutex); 781 if (interactive) { 782 if (!rps->power.interactive++ && intel_rps_is_active(rps)) 783 rps_set_power(rps, HIGH_POWER); 784 } else { 785 GEM_BUG_ON(!rps->power.interactive); 786 rps->power.interactive--; 787 } 788 mutex_unlock(&rps->power.mutex); 789 } 790 791 static int gen6_rps_set(struct intel_rps *rps, u8 val) 792 { 793 struct intel_uncore *uncore = rps_to_uncore(rps); 794 struct drm_i915_private *i915 = rps_to_i915(rps); 795 u32 swreq; 796 797 GEM_BUG_ON(rps_uses_slpc(rps)); 798 799 if (GRAPHICS_VER(i915) >= 9) 800 swreq = GEN9_FREQUENCY(val); 801 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 802 swreq = HSW_FREQUENCY(val); 803 else 804 swreq = (GEN6_FREQUENCY(val) | 805 GEN6_OFFSET(0) | 806 GEN6_AGGRESSIVE_TURBO); 807 set(uncore, GEN6_RPNSWREQ, swreq); 808 809 GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d, swreq:%x\n", 810 val, intel_gpu_freq(rps, val), swreq); 811 812 return 0; 813 } 814 815 static int vlv_rps_set(struct intel_rps *rps, u8 val) 816 { 817 struct drm_i915_private *i915 = rps_to_i915(rps); 818 int err; 819 820 vlv_punit_get(i915); 821 err = vlv_punit_write(i915, PUNIT_REG_GPU_FREQ_REQ, val); 822 vlv_punit_put(i915); 823 824 GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d\n", 825 val, intel_gpu_freq(rps, val)); 826 827 return err; 828 } 829 830 static int rps_set(struct intel_rps *rps, u8 val, bool update) 831 { 832 struct drm_i915_private *i915 = rps_to_i915(rps); 833 int err; 834 835 if (val == rps->last_freq) 836 return 0; 837 838 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 839 err = vlv_rps_set(rps, val); 840 else if (GRAPHICS_VER(i915) >= 6) 841 err = gen6_rps_set(rps, val); 842 else 843 err = gen5_rps_set(rps, val); 844 if (err) 845 return err; 846 847 if (update && GRAPHICS_VER(i915) >= 6) 848 gen6_rps_set_thresholds(rps, val); 849 rps->last_freq = val; 850 851 return 0; 852 } 853 854 void intel_rps_unpark(struct intel_rps *rps) 855 { 856 if (!intel_rps_is_enabled(rps)) 857 return; 858 859 GT_TRACE(rps_to_gt(rps), "unpark:%x\n", rps->cur_freq); 860 861 /* 862 * Use the user's desired frequency as a guide, but for better 863 * performance, jump directly to RPe as our starting frequency. 864 */ 865 mutex_lock(&rps->lock); 866 867 intel_rps_set_active(rps); 868 intel_rps_set(rps, 869 clamp(rps->cur_freq, 870 rps->min_freq_softlimit, 871 rps->max_freq_softlimit)); 872 873 mutex_unlock(&rps->lock); 874 875 rps->pm_iir = 0; 876 if (intel_rps_has_interrupts(rps)) 877 rps_enable_interrupts(rps); 878 if (intel_rps_uses_timer(rps)) 879 rps_start_timer(rps); 880 881 if (GRAPHICS_VER(rps_to_i915(rps)) == 5) 882 gen5_rps_update(rps); 883 } 884 885 void intel_rps_park(struct intel_rps *rps) 886 { 887 int adj; 888 889 if (!intel_rps_is_enabled(rps)) 890 return; 891 892 if (!intel_rps_clear_active(rps)) 893 return; 894 895 if (intel_rps_uses_timer(rps)) 896 rps_stop_timer(rps); 897 if (intel_rps_has_interrupts(rps)) 898 rps_disable_interrupts(rps); 899 900 if (rps->last_freq <= rps->idle_freq) 901 return; 902 903 /* 904 * The punit delays the write of the frequency and voltage until it 905 * determines the GPU is awake. During normal usage we don't want to 906 * waste power changing the frequency if the GPU is sleeping (rc6). 907 * However, the GPU and driver is now idle and we do not want to delay 908 * switching to minimum voltage (reducing power whilst idle) as we do 909 * not expect to be woken in the near future and so must flush the 910 * change by waking the device. 911 * 912 * We choose to take the media powerwell (either would do to trick the 913 * punit into committing the voltage change) as that takes a lot less 914 * power than the render powerwell. 915 */ 916 intel_uncore_forcewake_get(rps_to_uncore(rps), FORCEWAKE_MEDIA); 917 rps_set(rps, rps->idle_freq, false); 918 intel_uncore_forcewake_put(rps_to_uncore(rps), FORCEWAKE_MEDIA); 919 920 /* 921 * Since we will try and restart from the previously requested 922 * frequency on unparking, treat this idle point as a downclock 923 * interrupt and reduce the frequency for resume. If we park/unpark 924 * more frequently than the rps worker can run, we will not respond 925 * to any EI and never see a change in frequency. 926 * 927 * (Note we accommodate Cherryview's limitation of only using an 928 * even bin by applying it to all.) 929 */ 930 adj = rps->last_adj; 931 if (adj < 0) 932 adj *= 2; 933 else /* CHV needs even encode values */ 934 adj = -2; 935 rps->last_adj = adj; 936 rps->cur_freq = max_t(int, rps->cur_freq + adj, rps->min_freq); 937 if (rps->cur_freq < rps->efficient_freq) { 938 rps->cur_freq = rps->efficient_freq; 939 rps->last_adj = 0; 940 } 941 942 GT_TRACE(rps_to_gt(rps), "park:%x\n", rps->cur_freq); 943 } 944 945 u32 intel_rps_get_boost_frequency(struct intel_rps *rps) 946 { 947 struct intel_guc_slpc *slpc; 948 949 if (rps_uses_slpc(rps)) { 950 slpc = rps_to_slpc(rps); 951 952 return slpc->boost_freq; 953 } else { 954 return intel_gpu_freq(rps, rps->boost_freq); 955 } 956 } 957 958 static int rps_set_boost_freq(struct intel_rps *rps, u32 val) 959 { 960 bool boost = false; 961 962 /* Validate against (static) hardware limits */ 963 val = intel_freq_opcode(rps, val); 964 if (val < rps->min_freq || val > rps->max_freq) 965 return -EINVAL; 966 967 mutex_lock(&rps->lock); 968 if (val != rps->boost_freq) { 969 rps->boost_freq = val; 970 boost = atomic_read(&rps->num_waiters); 971 } 972 mutex_unlock(&rps->lock); 973 if (boost) 974 schedule_work(&rps->work); 975 976 return 0; 977 } 978 979 int intel_rps_set_boost_frequency(struct intel_rps *rps, u32 freq) 980 { 981 struct intel_guc_slpc *slpc; 982 983 if (rps_uses_slpc(rps)) { 984 slpc = rps_to_slpc(rps); 985 986 return intel_guc_slpc_set_boost_freq(slpc, freq); 987 } else { 988 return rps_set_boost_freq(rps, freq); 989 } 990 } 991 992 void intel_rps_dec_waiters(struct intel_rps *rps) 993 { 994 struct intel_guc_slpc *slpc; 995 996 if (rps_uses_slpc(rps)) { 997 slpc = rps_to_slpc(rps); 998 999 intel_guc_slpc_dec_waiters(slpc); 1000 } else { 1001 atomic_dec(&rps->num_waiters); 1002 } 1003 } 1004 1005 void intel_rps_boost(struct i915_request *rq) 1006 { 1007 struct intel_guc_slpc *slpc; 1008 1009 if (i915_request_signaled(rq) || i915_request_has_waitboost(rq)) 1010 return; 1011 1012 /* Serializes with i915_request_retire() */ 1013 if (!test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags)) { 1014 struct intel_rps *rps = &READ_ONCE(rq->engine)->gt->rps; 1015 1016 if (rps_uses_slpc(rps)) { 1017 slpc = rps_to_slpc(rps); 1018 1019 /* Return if old value is non zero */ 1020 if (!atomic_fetch_inc(&slpc->num_waiters)) 1021 schedule_work(&slpc->boost_work); 1022 1023 return; 1024 } 1025 1026 if (atomic_fetch_inc(&rps->num_waiters)) 1027 return; 1028 1029 if (!intel_rps_is_active(rps)) 1030 return; 1031 1032 GT_TRACE(rps_to_gt(rps), "boost fence:%llx:%llx\n", 1033 rq->fence.context, rq->fence.seqno); 1034 1035 if (READ_ONCE(rps->cur_freq) < rps->boost_freq) 1036 schedule_work(&rps->work); 1037 1038 WRITE_ONCE(rps->boosts, rps->boosts + 1); /* debug only */ 1039 } 1040 } 1041 1042 int intel_rps_set(struct intel_rps *rps, u8 val) 1043 { 1044 int err; 1045 1046 lockdep_assert_held(&rps->lock); 1047 GEM_BUG_ON(val > rps->max_freq); 1048 GEM_BUG_ON(val < rps->min_freq); 1049 1050 if (intel_rps_is_active(rps)) { 1051 err = rps_set(rps, val, true); 1052 if (err) 1053 return err; 1054 1055 /* 1056 * Make sure we continue to get interrupts 1057 * until we hit the minimum or maximum frequencies. 1058 */ 1059 if (intel_rps_has_interrupts(rps)) { 1060 struct intel_uncore *uncore = rps_to_uncore(rps); 1061 1062 set(uncore, 1063 GEN6_RP_INTERRUPT_LIMITS, rps_limits(rps, val)); 1064 1065 set(uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, val)); 1066 } 1067 } 1068 1069 rps->cur_freq = val; 1070 return 0; 1071 } 1072 1073 static void gen6_rps_init(struct intel_rps *rps) 1074 { 1075 struct drm_i915_private *i915 = rps_to_i915(rps); 1076 u32 rp_state_cap = intel_rps_read_state_cap(rps); 1077 1078 /* All of these values are in units of 50MHz */ 1079 1080 /* static values from HW: RP0 > RP1 > RPn (min_freq) */ 1081 if (IS_GEN9_LP(i915)) { 1082 rps->rp0_freq = (rp_state_cap >> 16) & 0xff; 1083 rps->rp1_freq = (rp_state_cap >> 8) & 0xff; 1084 rps->min_freq = (rp_state_cap >> 0) & 0xff; 1085 } else { 1086 rps->rp0_freq = (rp_state_cap >> 0) & 0xff; 1087 rps->rp1_freq = (rp_state_cap >> 8) & 0xff; 1088 rps->min_freq = (rp_state_cap >> 16) & 0xff; 1089 } 1090 1091 /* hw_max = RP0 until we check for overclocking */ 1092 rps->max_freq = rps->rp0_freq; 1093 1094 rps->efficient_freq = rps->rp1_freq; 1095 if (IS_HASWELL(i915) || IS_BROADWELL(i915) || 1096 IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { 1097 u32 ddcc_status = 0; 1098 1099 if (snb_pcode_read(i915, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, 1100 &ddcc_status, NULL) == 0) 1101 rps->efficient_freq = 1102 clamp_t(u8, 1103 (ddcc_status >> 8) & 0xff, 1104 rps->min_freq, 1105 rps->max_freq); 1106 } 1107 1108 if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { 1109 /* Store the frequency values in 16.66 MHZ units, which is 1110 * the natural hardware unit for SKL 1111 */ 1112 rps->rp0_freq *= GEN9_FREQ_SCALER; 1113 rps->rp1_freq *= GEN9_FREQ_SCALER; 1114 rps->min_freq *= GEN9_FREQ_SCALER; 1115 rps->max_freq *= GEN9_FREQ_SCALER; 1116 rps->efficient_freq *= GEN9_FREQ_SCALER; 1117 } 1118 } 1119 1120 static bool rps_reset(struct intel_rps *rps) 1121 { 1122 struct drm_i915_private *i915 = rps_to_i915(rps); 1123 1124 /* force a reset */ 1125 rps->power.mode = -1; 1126 rps->last_freq = -1; 1127 1128 if (rps_set(rps, rps->min_freq, true)) { 1129 drm_err(&i915->drm, "Failed to reset RPS to initial values\n"); 1130 return false; 1131 } 1132 1133 rps->cur_freq = rps->min_freq; 1134 return true; 1135 } 1136 1137 /* See the Gen9_GT_PM_Programming_Guide doc for the below */ 1138 static bool gen9_rps_enable(struct intel_rps *rps) 1139 { 1140 struct intel_gt *gt = rps_to_gt(rps); 1141 struct intel_uncore *uncore = gt->uncore; 1142 1143 /* Program defaults and thresholds for RPS */ 1144 if (GRAPHICS_VER(gt->i915) == 9) 1145 intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ, 1146 GEN9_FREQUENCY(rps->rp1_freq)); 1147 1148 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 0xa); 1149 1150 rps->pm_events = GEN6_PM_RP_UP_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD; 1151 1152 return rps_reset(rps); 1153 } 1154 1155 static bool gen8_rps_enable(struct intel_rps *rps) 1156 { 1157 struct intel_uncore *uncore = rps_to_uncore(rps); 1158 1159 intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ, 1160 HSW_FREQUENCY(rps->rp1_freq)); 1161 1162 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); 1163 1164 rps->pm_events = GEN6_PM_RP_UP_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD; 1165 1166 return rps_reset(rps); 1167 } 1168 1169 static bool gen6_rps_enable(struct intel_rps *rps) 1170 { 1171 struct intel_uncore *uncore = rps_to_uncore(rps); 1172 1173 /* Power down if completely idle for over 50ms */ 1174 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 50000); 1175 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); 1176 1177 rps->pm_events = (GEN6_PM_RP_UP_THRESHOLD | 1178 GEN6_PM_RP_DOWN_THRESHOLD | 1179 GEN6_PM_RP_DOWN_TIMEOUT); 1180 1181 return rps_reset(rps); 1182 } 1183 1184 static int chv_rps_max_freq(struct intel_rps *rps) 1185 { 1186 struct drm_i915_private *i915 = rps_to_i915(rps); 1187 struct intel_gt *gt = rps_to_gt(rps); 1188 u32 val; 1189 1190 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); 1191 1192 switch (gt->info.sseu.eu_total) { 1193 case 8: 1194 /* (2 * 4) config */ 1195 val >>= FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT; 1196 break; 1197 case 12: 1198 /* (2 * 6) config */ 1199 val >>= FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT; 1200 break; 1201 case 16: 1202 /* (2 * 8) config */ 1203 default: 1204 /* Setting (2 * 8) Min RP0 for any other combination */ 1205 val >>= FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT; 1206 break; 1207 } 1208 1209 return val & FB_GFX_FREQ_FUSE_MASK; 1210 } 1211 1212 static int chv_rps_rpe_freq(struct intel_rps *rps) 1213 { 1214 struct drm_i915_private *i915 = rps_to_i915(rps); 1215 u32 val; 1216 1217 val = vlv_punit_read(i915, PUNIT_GPU_DUTYCYCLE_REG); 1218 val >>= PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT; 1219 1220 return val & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; 1221 } 1222 1223 static int chv_rps_guar_freq(struct intel_rps *rps) 1224 { 1225 struct drm_i915_private *i915 = rps_to_i915(rps); 1226 u32 val; 1227 1228 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); 1229 1230 return val & FB_GFX_FREQ_FUSE_MASK; 1231 } 1232 1233 static u32 chv_rps_min_freq(struct intel_rps *rps) 1234 { 1235 struct drm_i915_private *i915 = rps_to_i915(rps); 1236 u32 val; 1237 1238 val = vlv_punit_read(i915, FB_GFX_FMIN_AT_VMIN_FUSE); 1239 val >>= FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT; 1240 1241 return val & FB_GFX_FREQ_FUSE_MASK; 1242 } 1243 1244 static bool chv_rps_enable(struct intel_rps *rps) 1245 { 1246 struct intel_uncore *uncore = rps_to_uncore(rps); 1247 struct drm_i915_private *i915 = rps_to_i915(rps); 1248 u32 val; 1249 1250 /* 1: Program defaults and thresholds for RPS*/ 1251 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 1000000); 1252 intel_uncore_write_fw(uncore, GEN6_RP_UP_THRESHOLD, 59400); 1253 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_THRESHOLD, 245000); 1254 intel_uncore_write_fw(uncore, GEN6_RP_UP_EI, 66000); 1255 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_EI, 350000); 1256 1257 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); 1258 1259 /* 2: Enable RPS */ 1260 intel_uncore_write_fw(uncore, GEN6_RP_CONTROL, 1261 GEN6_RP_MEDIA_HW_NORMAL_MODE | 1262 GEN6_RP_MEDIA_IS_GFX | 1263 GEN6_RP_ENABLE | 1264 GEN6_RP_UP_BUSY_AVG | 1265 GEN6_RP_DOWN_IDLE_AVG); 1266 1267 rps->pm_events = (GEN6_PM_RP_UP_THRESHOLD | 1268 GEN6_PM_RP_DOWN_THRESHOLD | 1269 GEN6_PM_RP_DOWN_TIMEOUT); 1270 1271 /* Setting Fixed Bias */ 1272 vlv_punit_get(i915); 1273 1274 val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | CHV_BIAS_CPU_50_SOC_50; 1275 vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val); 1276 1277 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 1278 1279 vlv_punit_put(i915); 1280 1281 /* RPS code assumes GPLL is used */ 1282 drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0, 1283 "GPLL not enabled\n"); 1284 1285 drm_dbg(&i915->drm, "GPLL enabled? %s\n", 1286 str_yes_no(val & GPLLENABLE)); 1287 drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val); 1288 1289 return rps_reset(rps); 1290 } 1291 1292 static int vlv_rps_guar_freq(struct intel_rps *rps) 1293 { 1294 struct drm_i915_private *i915 = rps_to_i915(rps); 1295 u32 val, rp1; 1296 1297 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE); 1298 1299 rp1 = val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK; 1300 rp1 >>= FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; 1301 1302 return rp1; 1303 } 1304 1305 static int vlv_rps_max_freq(struct intel_rps *rps) 1306 { 1307 struct drm_i915_private *i915 = rps_to_i915(rps); 1308 u32 val, rp0; 1309 1310 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE); 1311 1312 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; 1313 /* Clamp to max */ 1314 rp0 = min_t(u32, rp0, 0xea); 1315 1316 return rp0; 1317 } 1318 1319 static int vlv_rps_rpe_freq(struct intel_rps *rps) 1320 { 1321 struct drm_i915_private *i915 = rps_to_i915(rps); 1322 u32 val, rpe; 1323 1324 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_LO); 1325 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; 1326 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_HI); 1327 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; 1328 1329 return rpe; 1330 } 1331 1332 static int vlv_rps_min_freq(struct intel_rps *rps) 1333 { 1334 struct drm_i915_private *i915 = rps_to_i915(rps); 1335 u32 val; 1336 1337 val = vlv_punit_read(i915, PUNIT_REG_GPU_LFM) & 0xff; 1338 /* 1339 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value 1340 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on 1341 * a BYT-M B0 the above register contains 0xbf. Moreover when setting 1342 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0 1343 * to make sure it matches what Punit accepts. 1344 */ 1345 return max_t(u32, val, 0xc0); 1346 } 1347 1348 static bool vlv_rps_enable(struct intel_rps *rps) 1349 { 1350 struct intel_uncore *uncore = rps_to_uncore(rps); 1351 struct drm_i915_private *i915 = rps_to_i915(rps); 1352 u32 val; 1353 1354 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 1000000); 1355 intel_uncore_write_fw(uncore, GEN6_RP_UP_THRESHOLD, 59400); 1356 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_THRESHOLD, 245000); 1357 intel_uncore_write_fw(uncore, GEN6_RP_UP_EI, 66000); 1358 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_EI, 350000); 1359 1360 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); 1361 1362 intel_uncore_write_fw(uncore, GEN6_RP_CONTROL, 1363 GEN6_RP_MEDIA_TURBO | 1364 GEN6_RP_MEDIA_HW_NORMAL_MODE | 1365 GEN6_RP_MEDIA_IS_GFX | 1366 GEN6_RP_ENABLE | 1367 GEN6_RP_UP_BUSY_AVG | 1368 GEN6_RP_DOWN_IDLE_CONT); 1369 1370 /* WaGsvRC0ResidencyMethod:vlv */ 1371 rps->pm_events = GEN6_PM_RP_UP_EI_EXPIRED; 1372 1373 vlv_punit_get(i915); 1374 1375 /* Setting Fixed Bias */ 1376 val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | VLV_BIAS_CPU_125_SOC_875; 1377 vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val); 1378 1379 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 1380 1381 vlv_punit_put(i915); 1382 1383 /* RPS code assumes GPLL is used */ 1384 drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0, 1385 "GPLL not enabled\n"); 1386 1387 drm_dbg(&i915->drm, "GPLL enabled? %s\n", 1388 str_yes_no(val & GPLLENABLE)); 1389 drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val); 1390 1391 return rps_reset(rps); 1392 } 1393 1394 static unsigned long __ips_gfx_val(struct intel_ips *ips) 1395 { 1396 struct intel_rps *rps = container_of(ips, typeof(*rps), ips); 1397 struct intel_uncore *uncore = rps_to_uncore(rps); 1398 unsigned int t, state1, state2; 1399 u32 pxvid, ext_v; 1400 u64 corr, corr2; 1401 1402 lockdep_assert_held(&mchdev_lock); 1403 1404 pxvid = intel_uncore_read(uncore, PXVFREQ(rps->cur_freq)); 1405 pxvid = (pxvid >> 24) & 0x7f; 1406 ext_v = pvid_to_extvid(rps_to_i915(rps), pxvid); 1407 1408 state1 = ext_v; 1409 1410 /* Revel in the empirically derived constants */ 1411 1412 /* Correction factor in 1/100000 units */ 1413 t = ips_mch_val(uncore); 1414 if (t > 80) 1415 corr = t * 2349 + 135940; 1416 else if (t >= 50) 1417 corr = t * 964 + 29317; 1418 else /* < 50 */ 1419 corr = t * 301 + 1004; 1420 1421 corr = div_u64(corr * 150142 * state1, 10000) - 78642; 1422 corr2 = div_u64(corr, 100000) * ips->corr; 1423 1424 state2 = div_u64(corr2 * state1, 10000); 1425 state2 /= 100; /* convert to mW */ 1426 1427 __gen5_ips_update(ips); 1428 1429 return ips->gfx_power + state2; 1430 } 1431 1432 static bool has_busy_stats(struct intel_rps *rps) 1433 { 1434 struct intel_engine_cs *engine; 1435 enum intel_engine_id id; 1436 1437 for_each_engine(engine, rps_to_gt(rps), id) { 1438 if (!intel_engine_supports_stats(engine)) 1439 return false; 1440 } 1441 1442 return true; 1443 } 1444 1445 void intel_rps_enable(struct intel_rps *rps) 1446 { 1447 struct drm_i915_private *i915 = rps_to_i915(rps); 1448 struct intel_uncore *uncore = rps_to_uncore(rps); 1449 bool enabled = false; 1450 1451 if (!HAS_RPS(i915)) 1452 return; 1453 1454 if (rps_uses_slpc(rps)) 1455 return; 1456 1457 intel_gt_check_clock_frequency(rps_to_gt(rps)); 1458 1459 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 1460 if (rps->max_freq <= rps->min_freq) 1461 /* leave disabled, no room for dynamic reclocking */; 1462 else if (IS_CHERRYVIEW(i915)) 1463 enabled = chv_rps_enable(rps); 1464 else if (IS_VALLEYVIEW(i915)) 1465 enabled = vlv_rps_enable(rps); 1466 else if (GRAPHICS_VER(i915) >= 9) 1467 enabled = gen9_rps_enable(rps); 1468 else if (GRAPHICS_VER(i915) >= 8) 1469 enabled = gen8_rps_enable(rps); 1470 else if (GRAPHICS_VER(i915) >= 6) 1471 enabled = gen6_rps_enable(rps); 1472 else if (IS_IRONLAKE_M(i915)) 1473 enabled = gen5_rps_enable(rps); 1474 else 1475 MISSING_CASE(GRAPHICS_VER(i915)); 1476 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 1477 if (!enabled) 1478 return; 1479 1480 GT_TRACE(rps_to_gt(rps), 1481 "min:%x, max:%x, freq:[%d, %d]\n", 1482 rps->min_freq, rps->max_freq, 1483 intel_gpu_freq(rps, rps->min_freq), 1484 intel_gpu_freq(rps, rps->max_freq)); 1485 1486 GEM_BUG_ON(rps->max_freq < rps->min_freq); 1487 GEM_BUG_ON(rps->idle_freq > rps->max_freq); 1488 1489 GEM_BUG_ON(rps->efficient_freq < rps->min_freq); 1490 GEM_BUG_ON(rps->efficient_freq > rps->max_freq); 1491 1492 if (has_busy_stats(rps)) 1493 intel_rps_set_timer(rps); 1494 else if (GRAPHICS_VER(i915) >= 6 && GRAPHICS_VER(i915) <= 11) 1495 intel_rps_set_interrupts(rps); 1496 else 1497 /* Ironlake currently uses intel_ips.ko */ {} 1498 1499 intel_rps_set_enabled(rps); 1500 } 1501 1502 static void gen6_rps_disable(struct intel_rps *rps) 1503 { 1504 set(rps_to_uncore(rps), GEN6_RP_CONTROL, 0); 1505 } 1506 1507 void intel_rps_disable(struct intel_rps *rps) 1508 { 1509 struct drm_i915_private *i915 = rps_to_i915(rps); 1510 1511 intel_rps_clear_enabled(rps); 1512 intel_rps_clear_interrupts(rps); 1513 intel_rps_clear_timer(rps); 1514 1515 if (GRAPHICS_VER(i915) >= 6) 1516 gen6_rps_disable(rps); 1517 else if (IS_IRONLAKE_M(i915)) 1518 gen5_rps_disable(rps); 1519 } 1520 1521 static int byt_gpu_freq(struct intel_rps *rps, int val) 1522 { 1523 /* 1524 * N = val - 0xb7 1525 * Slow = Fast = GPLL ref * N 1526 */ 1527 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000); 1528 } 1529 1530 static int byt_freq_opcode(struct intel_rps *rps, int val) 1531 { 1532 return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7; 1533 } 1534 1535 static int chv_gpu_freq(struct intel_rps *rps, int val) 1536 { 1537 /* 1538 * N = val / 2 1539 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2 1540 */ 1541 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000); 1542 } 1543 1544 static int chv_freq_opcode(struct intel_rps *rps, int val) 1545 { 1546 /* CHV needs even values */ 1547 return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2; 1548 } 1549 1550 int intel_gpu_freq(struct intel_rps *rps, int val) 1551 { 1552 struct drm_i915_private *i915 = rps_to_i915(rps); 1553 1554 if (GRAPHICS_VER(i915) >= 9) 1555 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, 1556 GEN9_FREQ_SCALER); 1557 else if (IS_CHERRYVIEW(i915)) 1558 return chv_gpu_freq(rps, val); 1559 else if (IS_VALLEYVIEW(i915)) 1560 return byt_gpu_freq(rps, val); 1561 else if (GRAPHICS_VER(i915) >= 6) 1562 return val * GT_FREQUENCY_MULTIPLIER; 1563 else 1564 return val; 1565 } 1566 1567 int intel_freq_opcode(struct intel_rps *rps, int val) 1568 { 1569 struct drm_i915_private *i915 = rps_to_i915(rps); 1570 1571 if (GRAPHICS_VER(i915) >= 9) 1572 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, 1573 GT_FREQUENCY_MULTIPLIER); 1574 else if (IS_CHERRYVIEW(i915)) 1575 return chv_freq_opcode(rps, val); 1576 else if (IS_VALLEYVIEW(i915)) 1577 return byt_freq_opcode(rps, val); 1578 else if (GRAPHICS_VER(i915) >= 6) 1579 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); 1580 else 1581 return val; 1582 } 1583 1584 static void vlv_init_gpll_ref_freq(struct intel_rps *rps) 1585 { 1586 struct drm_i915_private *i915 = rps_to_i915(rps); 1587 1588 rps->gpll_ref_freq = 1589 vlv_get_cck_clock(i915, "GPLL ref", 1590 CCK_GPLL_CLOCK_CONTROL, 1591 i915->czclk_freq); 1592 1593 drm_dbg(&i915->drm, "GPLL reference freq: %d kHz\n", 1594 rps->gpll_ref_freq); 1595 } 1596 1597 static void vlv_rps_init(struct intel_rps *rps) 1598 { 1599 struct drm_i915_private *i915 = rps_to_i915(rps); 1600 u32 val; 1601 1602 vlv_iosf_sb_get(i915, 1603 BIT(VLV_IOSF_SB_PUNIT) | 1604 BIT(VLV_IOSF_SB_NC) | 1605 BIT(VLV_IOSF_SB_CCK)); 1606 1607 vlv_init_gpll_ref_freq(rps); 1608 1609 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 1610 switch ((val >> 6) & 3) { 1611 case 0: 1612 case 1: 1613 i915->mem_freq = 800; 1614 break; 1615 case 2: 1616 i915->mem_freq = 1066; 1617 break; 1618 case 3: 1619 i915->mem_freq = 1333; 1620 break; 1621 } 1622 drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq); 1623 1624 rps->max_freq = vlv_rps_max_freq(rps); 1625 rps->rp0_freq = rps->max_freq; 1626 drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n", 1627 intel_gpu_freq(rps, rps->max_freq), rps->max_freq); 1628 1629 rps->efficient_freq = vlv_rps_rpe_freq(rps); 1630 drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n", 1631 intel_gpu_freq(rps, rps->efficient_freq), rps->efficient_freq); 1632 1633 rps->rp1_freq = vlv_rps_guar_freq(rps); 1634 drm_dbg(&i915->drm, "RP1(Guar Freq) GPU freq: %d MHz (%u)\n", 1635 intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq); 1636 1637 rps->min_freq = vlv_rps_min_freq(rps); 1638 drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n", 1639 intel_gpu_freq(rps, rps->min_freq), rps->min_freq); 1640 1641 vlv_iosf_sb_put(i915, 1642 BIT(VLV_IOSF_SB_PUNIT) | 1643 BIT(VLV_IOSF_SB_NC) | 1644 BIT(VLV_IOSF_SB_CCK)); 1645 } 1646 1647 static void chv_rps_init(struct intel_rps *rps) 1648 { 1649 struct drm_i915_private *i915 = rps_to_i915(rps); 1650 u32 val; 1651 1652 vlv_iosf_sb_get(i915, 1653 BIT(VLV_IOSF_SB_PUNIT) | 1654 BIT(VLV_IOSF_SB_NC) | 1655 BIT(VLV_IOSF_SB_CCK)); 1656 1657 vlv_init_gpll_ref_freq(rps); 1658 1659 val = vlv_cck_read(i915, CCK_FUSE_REG); 1660 1661 switch ((val >> 2) & 0x7) { 1662 case 3: 1663 i915->mem_freq = 2000; 1664 break; 1665 default: 1666 i915->mem_freq = 1600; 1667 break; 1668 } 1669 drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq); 1670 1671 rps->max_freq = chv_rps_max_freq(rps); 1672 rps->rp0_freq = rps->max_freq; 1673 drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n", 1674 intel_gpu_freq(rps, rps->max_freq), rps->max_freq); 1675 1676 rps->efficient_freq = chv_rps_rpe_freq(rps); 1677 drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n", 1678 intel_gpu_freq(rps, rps->efficient_freq), rps->efficient_freq); 1679 1680 rps->rp1_freq = chv_rps_guar_freq(rps); 1681 drm_dbg(&i915->drm, "RP1(Guar) GPU freq: %d MHz (%u)\n", 1682 intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq); 1683 1684 rps->min_freq = chv_rps_min_freq(rps); 1685 drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n", 1686 intel_gpu_freq(rps, rps->min_freq), rps->min_freq); 1687 1688 vlv_iosf_sb_put(i915, 1689 BIT(VLV_IOSF_SB_PUNIT) | 1690 BIT(VLV_IOSF_SB_NC) | 1691 BIT(VLV_IOSF_SB_CCK)); 1692 1693 drm_WARN_ONCE(&i915->drm, (rps->max_freq | rps->efficient_freq | 1694 rps->rp1_freq | rps->min_freq) & 1, 1695 "Odd GPU freq values\n"); 1696 } 1697 1698 static void vlv_c0_read(struct intel_uncore *uncore, struct intel_rps_ei *ei) 1699 { 1700 ei->ktime = ktime_get_raw(); 1701 ei->render_c0 = intel_uncore_read(uncore, VLV_RENDER_C0_COUNT); 1702 ei->media_c0 = intel_uncore_read(uncore, VLV_MEDIA_C0_COUNT); 1703 } 1704 1705 static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32 pm_iir) 1706 { 1707 struct intel_uncore *uncore = rps_to_uncore(rps); 1708 const struct intel_rps_ei *prev = &rps->ei; 1709 struct intel_rps_ei now; 1710 u32 events = 0; 1711 1712 if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0) 1713 return 0; 1714 1715 vlv_c0_read(uncore, &now); 1716 1717 if (prev->ktime) { 1718 u64 time, c0; 1719 u32 render, media; 1720 1721 time = ktime_us_delta(now.ktime, prev->ktime); 1722 1723 time *= rps_to_i915(rps)->czclk_freq; 1724 1725 /* Workload can be split between render + media, 1726 * e.g. SwapBuffers being blitted in X after being rendered in 1727 * mesa. To account for this we need to combine both engines 1728 * into our activity counter. 1729 */ 1730 render = now.render_c0 - prev->render_c0; 1731 media = now.media_c0 - prev->media_c0; 1732 c0 = max(render, media); 1733 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */ 1734 1735 if (c0 > time * rps->power.up_threshold) 1736 events = GEN6_PM_RP_UP_THRESHOLD; 1737 else if (c0 < time * rps->power.down_threshold) 1738 events = GEN6_PM_RP_DOWN_THRESHOLD; 1739 } 1740 1741 rps->ei = now; 1742 return events; 1743 } 1744 1745 static void rps_work(struct work_struct *work) 1746 { 1747 struct intel_rps *rps = container_of(work, typeof(*rps), work); 1748 struct intel_gt *gt = rps_to_gt(rps); 1749 struct drm_i915_private *i915 = rps_to_i915(rps); 1750 bool client_boost = false; 1751 int new_freq, adj, min, max; 1752 u32 pm_iir = 0; 1753 1754 spin_lock_irq(>->irq_lock); 1755 pm_iir = fetch_and_zero(&rps->pm_iir) & rps->pm_events; 1756 client_boost = atomic_read(&rps->num_waiters); 1757 spin_unlock_irq(>->irq_lock); 1758 1759 /* Make sure we didn't queue anything we're not going to process. */ 1760 if (!pm_iir && !client_boost) 1761 goto out; 1762 1763 mutex_lock(&rps->lock); 1764 if (!intel_rps_is_active(rps)) { 1765 mutex_unlock(&rps->lock); 1766 return; 1767 } 1768 1769 pm_iir |= vlv_wa_c0_ei(rps, pm_iir); 1770 1771 adj = rps->last_adj; 1772 new_freq = rps->cur_freq; 1773 min = rps->min_freq_softlimit; 1774 max = rps->max_freq_softlimit; 1775 if (client_boost) 1776 max = rps->max_freq; 1777 1778 GT_TRACE(gt, 1779 "pm_iir:%x, client_boost:%s, last:%d, cur:%x, min:%x, max:%x\n", 1780 pm_iir, str_yes_no(client_boost), 1781 adj, new_freq, min, max); 1782 1783 if (client_boost && new_freq < rps->boost_freq) { 1784 new_freq = rps->boost_freq; 1785 adj = 0; 1786 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { 1787 if (adj > 0) 1788 adj *= 2; 1789 else /* CHV needs even encode values */ 1790 adj = IS_CHERRYVIEW(gt->i915) ? 2 : 1; 1791 1792 if (new_freq >= rps->max_freq_softlimit) 1793 adj = 0; 1794 } else if (client_boost) { 1795 adj = 0; 1796 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { 1797 if (rps->cur_freq > rps->efficient_freq) 1798 new_freq = rps->efficient_freq; 1799 else if (rps->cur_freq > rps->min_freq_softlimit) 1800 new_freq = rps->min_freq_softlimit; 1801 adj = 0; 1802 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { 1803 if (adj < 0) 1804 adj *= 2; 1805 else /* CHV needs even encode values */ 1806 adj = IS_CHERRYVIEW(gt->i915) ? -2 : -1; 1807 1808 if (new_freq <= rps->min_freq_softlimit) 1809 adj = 0; 1810 } else { /* unknown event */ 1811 adj = 0; 1812 } 1813 1814 /* 1815 * sysfs frequency limits may have snuck in while 1816 * servicing the interrupt 1817 */ 1818 new_freq += adj; 1819 new_freq = clamp_t(int, new_freq, min, max); 1820 1821 if (intel_rps_set(rps, new_freq)) { 1822 drm_dbg(&i915->drm, "Failed to set new GPU frequency\n"); 1823 adj = 0; 1824 } 1825 rps->last_adj = adj; 1826 1827 mutex_unlock(&rps->lock); 1828 1829 out: 1830 spin_lock_irq(>->irq_lock); 1831 gen6_gt_pm_unmask_irq(gt, rps->pm_events); 1832 spin_unlock_irq(>->irq_lock); 1833 } 1834 1835 void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) 1836 { 1837 struct intel_gt *gt = rps_to_gt(rps); 1838 const u32 events = rps->pm_events & pm_iir; 1839 1840 lockdep_assert_held(>->irq_lock); 1841 1842 if (unlikely(!events)) 1843 return; 1844 1845 GT_TRACE(gt, "irq events:%x\n", events); 1846 1847 gen6_gt_pm_mask_irq(gt, events); 1848 1849 rps->pm_iir |= events; 1850 schedule_work(&rps->work); 1851 } 1852 1853 void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) 1854 { 1855 struct intel_gt *gt = rps_to_gt(rps); 1856 u32 events; 1857 1858 events = pm_iir & rps->pm_events; 1859 if (events) { 1860 spin_lock(>->irq_lock); 1861 1862 GT_TRACE(gt, "irq events:%x\n", events); 1863 1864 gen6_gt_pm_mask_irq(gt, events); 1865 rps->pm_iir |= events; 1866 1867 schedule_work(&rps->work); 1868 spin_unlock(>->irq_lock); 1869 } 1870 1871 if (GRAPHICS_VER(gt->i915) >= 8) 1872 return; 1873 1874 if (pm_iir & PM_VEBOX_USER_INTERRUPT) 1875 intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10); 1876 1877 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) 1878 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); 1879 } 1880 1881 void gen5_rps_irq_handler(struct intel_rps *rps) 1882 { 1883 struct intel_uncore *uncore = rps_to_uncore(rps); 1884 u32 busy_up, busy_down, max_avg, min_avg; 1885 u8 new_freq; 1886 1887 spin_lock(&mchdev_lock); 1888 1889 intel_uncore_write16(uncore, 1890 MEMINTRSTS, 1891 intel_uncore_read(uncore, MEMINTRSTS)); 1892 1893 intel_uncore_write16(uncore, MEMINTRSTS, MEMINT_EVAL_CHG); 1894 busy_up = intel_uncore_read(uncore, RCPREVBSYTUPAVG); 1895 busy_down = intel_uncore_read(uncore, RCPREVBSYTDNAVG); 1896 max_avg = intel_uncore_read(uncore, RCBMAXAVG); 1897 min_avg = intel_uncore_read(uncore, RCBMINAVG); 1898 1899 /* Handle RCS change request from hw */ 1900 new_freq = rps->cur_freq; 1901 if (busy_up > max_avg) 1902 new_freq++; 1903 else if (busy_down < min_avg) 1904 new_freq--; 1905 new_freq = clamp(new_freq, 1906 rps->min_freq_softlimit, 1907 rps->max_freq_softlimit); 1908 1909 if (new_freq != rps->cur_freq && !__gen5_rps_set(rps, new_freq)) 1910 rps->cur_freq = new_freq; 1911 1912 spin_unlock(&mchdev_lock); 1913 } 1914 1915 void intel_rps_init_early(struct intel_rps *rps) 1916 { 1917 mutex_init(&rps->lock); 1918 mutex_init(&rps->power.mutex); 1919 1920 INIT_WORK(&rps->work, rps_work); 1921 timer_setup(&rps->timer, rps_timer, 0); 1922 1923 atomic_set(&rps->num_waiters, 0); 1924 } 1925 1926 void intel_rps_init(struct intel_rps *rps) 1927 { 1928 struct drm_i915_private *i915 = rps_to_i915(rps); 1929 1930 if (rps_uses_slpc(rps)) 1931 return; 1932 1933 if (IS_CHERRYVIEW(i915)) 1934 chv_rps_init(rps); 1935 else if (IS_VALLEYVIEW(i915)) 1936 vlv_rps_init(rps); 1937 else if (GRAPHICS_VER(i915) >= 6) 1938 gen6_rps_init(rps); 1939 else if (IS_IRONLAKE_M(i915)) 1940 gen5_rps_init(rps); 1941 1942 /* Derive initial user preferences/limits from the hardware limits */ 1943 rps->max_freq_softlimit = rps->max_freq; 1944 rps->min_freq_softlimit = rps->min_freq; 1945 1946 /* After setting max-softlimit, find the overclock max freq */ 1947 if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) { 1948 u32 params = 0; 1949 1950 snb_pcode_read(i915, GEN6_READ_OC_PARAMS, ¶ms, NULL); 1951 if (params & BIT(31)) { /* OC supported */ 1952 drm_dbg(&i915->drm, 1953 "Overclocking supported, max: %dMHz, overclock: %dMHz\n", 1954 (rps->max_freq & 0xff) * 50, 1955 (params & 0xff) * 50); 1956 rps->max_freq = params & 0xff; 1957 } 1958 } 1959 1960 /* Finally allow us to boost to max by default */ 1961 rps->boost_freq = rps->max_freq; 1962 rps->idle_freq = rps->min_freq; 1963 1964 /* Start in the middle, from here we will autotune based on workload */ 1965 rps->cur_freq = rps->efficient_freq; 1966 1967 rps->pm_intrmsk_mbz = 0; 1968 1969 /* 1970 * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer 1971 * if GEN6_PM_UP_EI_EXPIRED is masked. 1972 * 1973 * TODO: verify if this can be reproduced on VLV,CHV. 1974 */ 1975 if (GRAPHICS_VER(i915) <= 7) 1976 rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; 1977 1978 if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) < 11) 1979 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; 1980 1981 /* GuC needs ARAT expired interrupt unmasked */ 1982 if (intel_uc_uses_guc_submission(&rps_to_gt(rps)->uc)) 1983 rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK; 1984 } 1985 1986 void intel_rps_sanitize(struct intel_rps *rps) 1987 { 1988 if (rps_uses_slpc(rps)) 1989 return; 1990 1991 if (GRAPHICS_VER(rps_to_i915(rps)) >= 6) 1992 rps_disable_interrupts(rps); 1993 } 1994 1995 u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) 1996 { 1997 struct drm_i915_private *i915 = rps_to_i915(rps); 1998 u32 cagf; 1999 2000 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 2001 cagf = (rpstat >> 8) & 0xff; 2002 else if (GRAPHICS_VER(i915) >= 9) 2003 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; 2004 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 2005 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; 2006 else if (GRAPHICS_VER(i915) >= 6) 2007 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; 2008 else 2009 cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >> 2010 MEMSTAT_PSTATE_SHIFT); 2011 2012 return cagf; 2013 } 2014 2015 static u32 read_cagf(struct intel_rps *rps) 2016 { 2017 struct drm_i915_private *i915 = rps_to_i915(rps); 2018 struct intel_uncore *uncore = rps_to_uncore(rps); 2019 u32 freq; 2020 2021 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 2022 vlv_punit_get(i915); 2023 freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 2024 vlv_punit_put(i915); 2025 } else if (GRAPHICS_VER(i915) >= 6) { 2026 freq = intel_uncore_read(uncore, GEN6_RPSTAT1); 2027 } else { 2028 freq = intel_uncore_read(uncore, MEMSTAT_ILK); 2029 } 2030 2031 return intel_rps_get_cagf(rps, freq); 2032 } 2033 2034 u32 intel_rps_read_actual_frequency(struct intel_rps *rps) 2035 { 2036 struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; 2037 intel_wakeref_t wakeref; 2038 u32 freq = 0; 2039 2040 with_intel_runtime_pm_if_in_use(rpm, wakeref) 2041 freq = intel_gpu_freq(rps, read_cagf(rps)); 2042 2043 return freq; 2044 } 2045 2046 u32 intel_rps_read_punit_req(struct intel_rps *rps) 2047 { 2048 struct intel_uncore *uncore = rps_to_uncore(rps); 2049 struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; 2050 intel_wakeref_t wakeref; 2051 u32 freq = 0; 2052 2053 with_intel_runtime_pm_if_in_use(rpm, wakeref) 2054 freq = intel_uncore_read(uncore, GEN6_RPNSWREQ); 2055 2056 return freq; 2057 } 2058 2059 static u32 intel_rps_get_req(u32 pureq) 2060 { 2061 u32 req = pureq >> GEN9_SW_REQ_UNSLICE_RATIO_SHIFT; 2062 2063 return req; 2064 } 2065 2066 u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps) 2067 { 2068 u32 freq = intel_rps_get_req(intel_rps_read_punit_req(rps)); 2069 2070 return intel_gpu_freq(rps, freq); 2071 } 2072 2073 u32 intel_rps_get_requested_frequency(struct intel_rps *rps) 2074 { 2075 if (rps_uses_slpc(rps)) 2076 return intel_rps_read_punit_req_frequency(rps); 2077 else 2078 return intel_gpu_freq(rps, rps->cur_freq); 2079 } 2080 2081 u32 intel_rps_get_max_frequency(struct intel_rps *rps) 2082 { 2083 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2084 2085 if (rps_uses_slpc(rps)) 2086 return slpc->max_freq_softlimit; 2087 else 2088 return intel_gpu_freq(rps, rps->max_freq_softlimit); 2089 } 2090 2091 u32 intel_rps_get_rp0_frequency(struct intel_rps *rps) 2092 { 2093 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2094 2095 if (rps_uses_slpc(rps)) 2096 return slpc->rp0_freq; 2097 else 2098 return intel_gpu_freq(rps, rps->rp0_freq); 2099 } 2100 2101 u32 intel_rps_get_rp1_frequency(struct intel_rps *rps) 2102 { 2103 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2104 2105 if (rps_uses_slpc(rps)) 2106 return slpc->rp1_freq; 2107 else 2108 return intel_gpu_freq(rps, rps->rp1_freq); 2109 } 2110 2111 u32 intel_rps_get_rpn_frequency(struct intel_rps *rps) 2112 { 2113 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2114 2115 if (rps_uses_slpc(rps)) 2116 return slpc->min_freq; 2117 else 2118 return intel_gpu_freq(rps, rps->min_freq); 2119 } 2120 2121 static int set_max_freq(struct intel_rps *rps, u32 val) 2122 { 2123 struct drm_i915_private *i915 = rps_to_i915(rps); 2124 int ret = 0; 2125 2126 mutex_lock(&rps->lock); 2127 2128 val = intel_freq_opcode(rps, val); 2129 if (val < rps->min_freq || 2130 val > rps->max_freq || 2131 val < rps->min_freq_softlimit) { 2132 ret = -EINVAL; 2133 goto unlock; 2134 } 2135 2136 if (val > rps->rp0_freq) 2137 drm_dbg(&i915->drm, "User requested overclocking to %d\n", 2138 intel_gpu_freq(rps, val)); 2139 2140 rps->max_freq_softlimit = val; 2141 2142 val = clamp_t(int, rps->cur_freq, 2143 rps->min_freq_softlimit, 2144 rps->max_freq_softlimit); 2145 2146 /* 2147 * We still need *_set_rps to process the new max_delay and 2148 * update the interrupt limits and PMINTRMSK even though 2149 * frequency request may be unchanged. 2150 */ 2151 intel_rps_set(rps, val); 2152 2153 unlock: 2154 mutex_unlock(&rps->lock); 2155 2156 return ret; 2157 } 2158 2159 int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val) 2160 { 2161 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2162 2163 if (rps_uses_slpc(rps)) 2164 return intel_guc_slpc_set_max_freq(slpc, val); 2165 else 2166 return set_max_freq(rps, val); 2167 } 2168 2169 u32 intel_rps_get_min_frequency(struct intel_rps *rps) 2170 { 2171 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2172 2173 if (rps_uses_slpc(rps)) 2174 return slpc->min_freq_softlimit; 2175 else 2176 return intel_gpu_freq(rps, rps->min_freq_softlimit); 2177 } 2178 2179 static int set_min_freq(struct intel_rps *rps, u32 val) 2180 { 2181 int ret = 0; 2182 2183 mutex_lock(&rps->lock); 2184 2185 val = intel_freq_opcode(rps, val); 2186 if (val < rps->min_freq || 2187 val > rps->max_freq || 2188 val > rps->max_freq_softlimit) { 2189 ret = -EINVAL; 2190 goto unlock; 2191 } 2192 2193 rps->min_freq_softlimit = val; 2194 2195 val = clamp_t(int, rps->cur_freq, 2196 rps->min_freq_softlimit, 2197 rps->max_freq_softlimit); 2198 2199 /* 2200 * We still need *_set_rps to process the new min_delay and 2201 * update the interrupt limits and PMINTRMSK even though 2202 * frequency request may be unchanged. 2203 */ 2204 intel_rps_set(rps, val); 2205 2206 unlock: 2207 mutex_unlock(&rps->lock); 2208 2209 return ret; 2210 } 2211 2212 int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val) 2213 { 2214 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2215 2216 if (rps_uses_slpc(rps)) 2217 return intel_guc_slpc_set_min_freq(slpc, val); 2218 else 2219 return set_min_freq(rps, val); 2220 } 2221 2222 u32 intel_rps_read_state_cap(struct intel_rps *rps) 2223 { 2224 struct drm_i915_private *i915 = rps_to_i915(rps); 2225 struct intel_uncore *uncore = rps_to_uncore(rps); 2226 2227 if (IS_XEHPSDV(i915)) 2228 return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP); 2229 else if (IS_GEN9_LP(i915)) 2230 return intel_uncore_read(uncore, BXT_RP_STATE_CAP); 2231 else 2232 return intel_uncore_read(uncore, GEN6_RP_STATE_CAP); 2233 } 2234 2235 static void intel_rps_set_manual(struct intel_rps *rps, bool enable) 2236 { 2237 struct intel_uncore *uncore = rps_to_uncore(rps); 2238 u32 state = enable ? GEN9_RPSWCTL_ENABLE : GEN9_RPSWCTL_DISABLE; 2239 2240 /* Allow punit to process software requests */ 2241 intel_uncore_write(uncore, GEN6_RP_CONTROL, state); 2242 } 2243 2244 void intel_rps_raise_unslice(struct intel_rps *rps) 2245 { 2246 struct intel_uncore *uncore = rps_to_uncore(rps); 2247 u32 rp0_unslice_req; 2248 2249 mutex_lock(&rps->lock); 2250 2251 if (rps_uses_slpc(rps)) { 2252 /* RP limits have not been initialized yet for SLPC path */ 2253 rp0_unslice_req = ((intel_rps_read_state_cap(rps) >> 0) 2254 & 0xff) * GEN9_FREQ_SCALER; 2255 2256 intel_rps_set_manual(rps, true); 2257 intel_uncore_write(uncore, GEN6_RPNSWREQ, 2258 ((rp0_unslice_req << 2259 GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) | 2260 GEN9_IGNORE_SLICE_RATIO)); 2261 intel_rps_set_manual(rps, false); 2262 } else { 2263 intel_rps_set(rps, rps->rp0_freq); 2264 } 2265 2266 mutex_unlock(&rps->lock); 2267 } 2268 2269 void intel_rps_lower_unslice(struct intel_rps *rps) 2270 { 2271 struct intel_uncore *uncore = rps_to_uncore(rps); 2272 u32 rpn_unslice_req; 2273 2274 mutex_lock(&rps->lock); 2275 2276 if (rps_uses_slpc(rps)) { 2277 /* RP limits have not been initialized yet for SLPC path */ 2278 rpn_unslice_req = ((intel_rps_read_state_cap(rps) >> 16) 2279 & 0xff) * GEN9_FREQ_SCALER; 2280 2281 intel_rps_set_manual(rps, true); 2282 intel_uncore_write(uncore, GEN6_RPNSWREQ, 2283 ((rpn_unslice_req << 2284 GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) | 2285 GEN9_IGNORE_SLICE_RATIO)); 2286 intel_rps_set_manual(rps, false); 2287 } else { 2288 intel_rps_set(rps, rps->min_freq); 2289 } 2290 2291 mutex_unlock(&rps->lock); 2292 } 2293 2294 /* External interface for intel_ips.ko */ 2295 2296 static struct drm_i915_private __rcu *ips_mchdev; 2297 2298 /** 2299 * Tells the intel_ips driver that the i915 driver is now loaded, if 2300 * IPS got loaded first. 2301 * 2302 * This awkward dance is so that neither module has to depend on the 2303 * other in order for IPS to do the appropriate communication of 2304 * GPU turbo limits to i915. 2305 */ 2306 static void 2307 ips_ping_for_i915_load(void) 2308 { 2309 void (*link)(void); 2310 2311 link = symbol_get(ips_link_to_i915_driver); 2312 if (link) { 2313 link(); 2314 symbol_put(ips_link_to_i915_driver); 2315 } 2316 } 2317 2318 void intel_rps_driver_register(struct intel_rps *rps) 2319 { 2320 struct intel_gt *gt = rps_to_gt(rps); 2321 2322 /* 2323 * We only register the i915 ips part with intel-ips once everything is 2324 * set up, to avoid intel-ips sneaking in and reading bogus values. 2325 */ 2326 if (GRAPHICS_VER(gt->i915) == 5) { 2327 GEM_BUG_ON(ips_mchdev); 2328 rcu_assign_pointer(ips_mchdev, gt->i915); 2329 ips_ping_for_i915_load(); 2330 } 2331 } 2332 2333 void intel_rps_driver_unregister(struct intel_rps *rps) 2334 { 2335 if (rcu_access_pointer(ips_mchdev) == rps_to_i915(rps)) 2336 rcu_assign_pointer(ips_mchdev, NULL); 2337 } 2338 2339 static struct drm_i915_private *mchdev_get(void) 2340 { 2341 struct drm_i915_private *i915; 2342 2343 rcu_read_lock(); 2344 i915 = rcu_dereference(ips_mchdev); 2345 if (i915 && !kref_get_unless_zero(&i915->drm.ref)) 2346 i915 = NULL; 2347 rcu_read_unlock(); 2348 2349 return i915; 2350 } 2351 2352 /** 2353 * i915_read_mch_val - return value for IPS use 2354 * 2355 * Calculate and return a value for the IPS driver to use when deciding whether 2356 * we have thermal and power headroom to increase CPU or GPU power budget. 2357 */ 2358 unsigned long i915_read_mch_val(void) 2359 { 2360 struct drm_i915_private *i915; 2361 unsigned long chipset_val = 0; 2362 unsigned long graphics_val = 0; 2363 intel_wakeref_t wakeref; 2364 2365 i915 = mchdev_get(); 2366 if (!i915) 2367 return 0; 2368 2369 with_intel_runtime_pm(&i915->runtime_pm, wakeref) { 2370 struct intel_ips *ips = &to_gt(i915)->rps.ips; 2371 2372 spin_lock_irq(&mchdev_lock); 2373 chipset_val = __ips_chipset_val(ips); 2374 graphics_val = __ips_gfx_val(ips); 2375 spin_unlock_irq(&mchdev_lock); 2376 } 2377 2378 drm_dev_put(&i915->drm); 2379 return chipset_val + graphics_val; 2380 } 2381 EXPORT_SYMBOL_GPL(i915_read_mch_val); 2382 2383 /** 2384 * i915_gpu_raise - raise GPU frequency limit 2385 * 2386 * Raise the limit; IPS indicates we have thermal headroom. 2387 */ 2388 bool i915_gpu_raise(void) 2389 { 2390 struct drm_i915_private *i915; 2391 struct intel_rps *rps; 2392 2393 i915 = mchdev_get(); 2394 if (!i915) 2395 return false; 2396 2397 rps = &to_gt(i915)->rps; 2398 2399 spin_lock_irq(&mchdev_lock); 2400 if (rps->max_freq_softlimit < rps->max_freq) 2401 rps->max_freq_softlimit++; 2402 spin_unlock_irq(&mchdev_lock); 2403 2404 drm_dev_put(&i915->drm); 2405 return true; 2406 } 2407 EXPORT_SYMBOL_GPL(i915_gpu_raise); 2408 2409 /** 2410 * i915_gpu_lower - lower GPU frequency limit 2411 * 2412 * IPS indicates we're close to a thermal limit, so throttle back the GPU 2413 * frequency maximum. 2414 */ 2415 bool i915_gpu_lower(void) 2416 { 2417 struct drm_i915_private *i915; 2418 struct intel_rps *rps; 2419 2420 i915 = mchdev_get(); 2421 if (!i915) 2422 return false; 2423 2424 rps = &to_gt(i915)->rps; 2425 2426 spin_lock_irq(&mchdev_lock); 2427 if (rps->max_freq_softlimit > rps->min_freq) 2428 rps->max_freq_softlimit--; 2429 spin_unlock_irq(&mchdev_lock); 2430 2431 drm_dev_put(&i915->drm); 2432 return true; 2433 } 2434 EXPORT_SYMBOL_GPL(i915_gpu_lower); 2435 2436 /** 2437 * i915_gpu_busy - indicate GPU business to IPS 2438 * 2439 * Tell the IPS driver whether or not the GPU is busy. 2440 */ 2441 bool i915_gpu_busy(void) 2442 { 2443 struct drm_i915_private *i915; 2444 bool ret; 2445 2446 i915 = mchdev_get(); 2447 if (!i915) 2448 return false; 2449 2450 ret = to_gt(i915)->awake; 2451 2452 drm_dev_put(&i915->drm); 2453 return ret; 2454 } 2455 EXPORT_SYMBOL_GPL(i915_gpu_busy); 2456 2457 /** 2458 * i915_gpu_turbo_disable - disable graphics turbo 2459 * 2460 * Disable graphics turbo by resetting the max frequency and setting the 2461 * current frequency to the default. 2462 */ 2463 bool i915_gpu_turbo_disable(void) 2464 { 2465 struct drm_i915_private *i915; 2466 struct intel_rps *rps; 2467 bool ret; 2468 2469 i915 = mchdev_get(); 2470 if (!i915) 2471 return false; 2472 2473 rps = &to_gt(i915)->rps; 2474 2475 spin_lock_irq(&mchdev_lock); 2476 rps->max_freq_softlimit = rps->min_freq; 2477 ret = !__gen5_rps_set(&to_gt(i915)->rps, rps->min_freq); 2478 spin_unlock_irq(&mchdev_lock); 2479 2480 drm_dev_put(&i915->drm); 2481 return ret; 2482 } 2483 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); 2484 2485 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2486 #include "selftest_rps.c" 2487 #include "selftest_slpc.c" 2488 #endif 2489