1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2008-2021 Intel Corporation 4 */ 5 6 #include "gen2_engine_cs.h" 7 #include "gen6_engine_cs.h" 8 #include "gen6_ppgtt.h" 9 #include "gen7_renderclear.h" 10 #include "i915_drv.h" 11 #include "i915_mitigations.h" 12 #include "intel_breadcrumbs.h" 13 #include "intel_context.h" 14 #include "intel_gt.h" 15 #include "intel_gt_irq.h" 16 #include "intel_reset.h" 17 #include "intel_ring.h" 18 #include "shmem_utils.h" 19 20 /* Rough estimate of the typical request size, performing a flush, 21 * set-context and then emitting the batch. 22 */ 23 #define LEGACY_REQUEST_SIZE 200 24 25 static void set_hwstam(struct intel_engine_cs *engine, u32 mask) 26 { 27 /* 28 * Keep the render interrupt unmasked as this papers over 29 * lost interrupts following a reset. 30 */ 31 if (engine->class == RENDER_CLASS) { 32 if (GRAPHICS_VER(engine->i915) >= 6) 33 mask &= ~BIT(0); 34 else 35 mask &= ~I915_USER_INTERRUPT; 36 } 37 38 intel_engine_set_hwsp_writemask(engine, mask); 39 } 40 41 static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys) 42 { 43 u32 addr; 44 45 addr = lower_32_bits(phys); 46 if (GRAPHICS_VER(engine->i915) >= 4) 47 addr |= (phys >> 28) & 0xf0; 48 49 intel_uncore_write(engine->uncore, HWS_PGA, addr); 50 } 51 52 static struct page *status_page(struct intel_engine_cs *engine) 53 { 54 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; 55 56 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); 57 return sg_page(obj->mm.pages->sgl); 58 } 59 60 static void ring_setup_phys_status_page(struct intel_engine_cs *engine) 61 { 62 set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine)))); 63 set_hwstam(engine, ~0u); 64 } 65 66 static void set_hwsp(struct intel_engine_cs *engine, u32 offset) 67 { 68 i915_reg_t hwsp; 69 70 /* 71 * The ring status page addresses are no longer next to the rest of 72 * the ring registers as of gen7. 73 */ 74 if (GRAPHICS_VER(engine->i915) == 7) { 75 switch (engine->id) { 76 /* 77 * No more rings exist on Gen7. Default case is only to shut up 78 * gcc switch check warning. 79 */ 80 default: 81 GEM_BUG_ON(engine->id); 82 fallthrough; 83 case RCS0: 84 hwsp = RENDER_HWS_PGA_GEN7; 85 break; 86 case BCS0: 87 hwsp = BLT_HWS_PGA_GEN7; 88 break; 89 case VCS0: 90 hwsp = BSD_HWS_PGA_GEN7; 91 break; 92 case VECS0: 93 hwsp = VEBOX_HWS_PGA_GEN7; 94 break; 95 } 96 } else if (GRAPHICS_VER(engine->i915) == 6) { 97 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); 98 } else { 99 hwsp = RING_HWS_PGA(engine->mmio_base); 100 } 101 102 intel_uncore_write_fw(engine->uncore, hwsp, offset); 103 intel_uncore_posting_read_fw(engine->uncore, hwsp); 104 } 105 106 static void flush_cs_tlb(struct intel_engine_cs *engine) 107 { 108 if (!IS_GRAPHICS_VER(engine->i915, 6, 7)) 109 return; 110 111 /* ring should be idle before issuing a sync flush*/ 112 GEM_DEBUG_WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); 113 114 ENGINE_WRITE_FW(engine, RING_INSTPM, 115 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | 116 INSTPM_SYNC_FLUSH)); 117 if (__intel_wait_for_register_fw(engine->uncore, 118 RING_INSTPM(engine->mmio_base), 119 INSTPM_SYNC_FLUSH, 0, 120 2000, 0, NULL)) 121 ENGINE_TRACE(engine, 122 "wait for SyncFlush to complete for TLB invalidation timed out\n"); 123 } 124 125 static void ring_setup_status_page(struct intel_engine_cs *engine) 126 { 127 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); 128 set_hwstam(engine, ~0u); 129 130 flush_cs_tlb(engine); 131 } 132 133 static struct i915_address_space *vm_alias(struct i915_address_space *vm) 134 { 135 if (i915_is_ggtt(vm)) 136 vm = &i915_vm_to_ggtt(vm)->alias->vm; 137 138 return vm; 139 } 140 141 static u32 pp_dir(struct i915_address_space *vm) 142 { 143 return to_gen6_ppgtt(i915_vm_to_ppgtt(vm))->pp_dir; 144 } 145 146 static void set_pp_dir(struct intel_engine_cs *engine) 147 { 148 struct i915_address_space *vm = vm_alias(engine->gt->vm); 149 150 if (!vm) 151 return; 152 153 ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G); 154 ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm)); 155 156 if (GRAPHICS_VER(engine->i915) >= 7) { 157 ENGINE_WRITE_FW(engine, 158 RING_MODE_GEN7, 159 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); 160 } 161 } 162 163 static bool stop_ring(struct intel_engine_cs *engine) 164 { 165 /* Empty the ring by skipping to the end */ 166 ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL)); 167 ENGINE_POSTING_READ(engine, RING_HEAD); 168 169 /* The ring must be empty before it is disabled */ 170 ENGINE_WRITE_FW(engine, RING_CTL, 0); 171 ENGINE_POSTING_READ(engine, RING_CTL); 172 173 /* Then reset the disabled ring */ 174 ENGINE_WRITE_FW(engine, RING_HEAD, 0); 175 ENGINE_WRITE_FW(engine, RING_TAIL, 0); 176 177 return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0; 178 } 179 180 static int xcs_resume(struct intel_engine_cs *engine) 181 { 182 struct intel_ring *ring = engine->legacy.ring; 183 184 ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n", 185 ring->head, ring->tail); 186 187 /* Double check the ring is empty & disabled before we resume */ 188 synchronize_hardirq(engine->i915->drm.irq); 189 if (!stop_ring(engine)) 190 goto err; 191 192 if (HWS_NEEDS_PHYSICAL(engine->i915)) 193 ring_setup_phys_status_page(engine); 194 else 195 ring_setup_status_page(engine); 196 197 intel_breadcrumbs_reset(engine->breadcrumbs); 198 199 /* Enforce ordering by reading HEAD register back */ 200 ENGINE_POSTING_READ(engine, RING_HEAD); 201 202 /* 203 * Initialize the ring. This must happen _after_ we've cleared the ring 204 * registers with the above sequence (the readback of the HEAD registers 205 * also enforces ordering), otherwise the hw might lose the new ring 206 * register values. 207 */ 208 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma)); 209 210 /* Check that the ring offsets point within the ring! */ 211 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); 212 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); 213 intel_ring_update_space(ring); 214 215 set_pp_dir(engine); 216 217 /* First wake the ring up to an empty/idle ring */ 218 ENGINE_WRITE_FW(engine, RING_HEAD, ring->head); 219 ENGINE_WRITE_FW(engine, RING_TAIL, ring->head); 220 ENGINE_POSTING_READ(engine, RING_TAIL); 221 222 ENGINE_WRITE_FW(engine, RING_CTL, 223 RING_CTL_SIZE(ring->size) | RING_VALID); 224 225 /* If the head is still not zero, the ring is dead */ 226 if (__intel_wait_for_register_fw(engine->uncore, 227 RING_CTL(engine->mmio_base), 228 RING_VALID, RING_VALID, 229 5000, 0, NULL)) 230 goto err; 231 232 if (GRAPHICS_VER(engine->i915) > 2) 233 ENGINE_WRITE_FW(engine, 234 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 235 236 /* Now awake, let it get started */ 237 if (ring->tail != ring->head) { 238 ENGINE_WRITE_FW(engine, RING_TAIL, ring->tail); 239 ENGINE_POSTING_READ(engine, RING_TAIL); 240 } 241 242 /* Papering over lost _interrupts_ immediately following the restart */ 243 intel_engine_signal_breadcrumbs(engine); 244 return 0; 245 246 err: 247 drm_err(&engine->i915->drm, 248 "%s initialization failed; " 249 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", 250 engine->name, 251 ENGINE_READ(engine, RING_CTL), 252 ENGINE_READ(engine, RING_CTL) & RING_VALID, 253 ENGINE_READ(engine, RING_HEAD), ring->head, 254 ENGINE_READ(engine, RING_TAIL), ring->tail, 255 ENGINE_READ(engine, RING_START), 256 i915_ggtt_offset(ring->vma)); 257 return -EIO; 258 } 259 260 static void sanitize_hwsp(struct intel_engine_cs *engine) 261 { 262 struct intel_timeline *tl; 263 264 list_for_each_entry(tl, &engine->status_page.timelines, engine_link) 265 intel_timeline_reset_seqno(tl); 266 } 267 268 static void xcs_sanitize(struct intel_engine_cs *engine) 269 { 270 /* 271 * Poison residual state on resume, in case the suspend didn't! 272 * 273 * We have to assume that across suspend/resume (or other loss 274 * of control) that the contents of our pinned buffers has been 275 * lost, replaced by garbage. Since this doesn't always happen, 276 * let's poison such state so that we more quickly spot when 277 * we falsely assume it has been preserved. 278 */ 279 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 280 memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE); 281 282 /* 283 * The kernel_context HWSP is stored in the status_page. As above, 284 * that may be lost on resume/initialisation, and so we need to 285 * reset the value in the HWSP. 286 */ 287 sanitize_hwsp(engine); 288 289 /* And scrub the dirty cachelines for the HWSP */ 290 clflush_cache_range(engine->status_page.addr, PAGE_SIZE); 291 } 292 293 static void reset_prepare(struct intel_engine_cs *engine) 294 { 295 /* 296 * We stop engines, otherwise we might get failed reset and a 297 * dead gpu (on elk). Also as modern gpu as kbl can suffer 298 * from system hang if batchbuffer is progressing when 299 * the reset is issued, regardless of READY_TO_RESET ack. 300 * Thus assume it is best to stop engines on all gens 301 * where we have a gpu reset. 302 * 303 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES) 304 * 305 * WaMediaResetMainRingCleanup:ctg,elk (presumably) 306 * WaClearRingBufHeadRegAtInit:ctg,elk 307 * 308 * FIXME: Wa for more modern gens needs to be validated 309 */ 310 ENGINE_TRACE(engine, "\n"); 311 intel_engine_stop_cs(engine); 312 313 if (!stop_ring(engine)) { 314 /* G45 ring initialization often fails to reset head to zero */ 315 ENGINE_TRACE(engine, 316 "HEAD not reset to zero, " 317 "{ CTL:%08x, HEAD:%08x, TAIL:%08x, START:%08x }\n", 318 ENGINE_READ_FW(engine, RING_CTL), 319 ENGINE_READ_FW(engine, RING_HEAD), 320 ENGINE_READ_FW(engine, RING_TAIL), 321 ENGINE_READ_FW(engine, RING_START)); 322 if (!stop_ring(engine)) { 323 drm_err(&engine->i915->drm, 324 "failed to set %s head to zero " 325 "ctl %08x head %08x tail %08x start %08x\n", 326 engine->name, 327 ENGINE_READ_FW(engine, RING_CTL), 328 ENGINE_READ_FW(engine, RING_HEAD), 329 ENGINE_READ_FW(engine, RING_TAIL), 330 ENGINE_READ_FW(engine, RING_START)); 331 } 332 } 333 } 334 335 static void reset_rewind(struct intel_engine_cs *engine, bool stalled) 336 { 337 struct i915_request *pos, *rq; 338 unsigned long flags; 339 u32 head; 340 341 rq = NULL; 342 spin_lock_irqsave(&engine->active.lock, flags); 343 rcu_read_lock(); 344 list_for_each_entry(pos, &engine->active.requests, sched.link) { 345 if (!__i915_request_is_complete(pos)) { 346 rq = pos; 347 break; 348 } 349 } 350 rcu_read_unlock(); 351 352 /* 353 * The guilty request will get skipped on a hung engine. 354 * 355 * Users of client default contexts do not rely on logical 356 * state preserved between batches so it is safe to execute 357 * queued requests following the hang. Non default contexts 358 * rely on preserved state, so skipping a batch loses the 359 * evolution of the state and it needs to be considered corrupted. 360 * Executing more queued batches on top of corrupted state is 361 * risky. But we take the risk by trying to advance through 362 * the queued requests in order to make the client behaviour 363 * more predictable around resets, by not throwing away random 364 * amount of batches it has prepared for execution. Sophisticated 365 * clients can use gem_reset_stats_ioctl and dma fence status 366 * (exported via sync_file info ioctl on explicit fences) to observe 367 * when it loses the context state and should rebuild accordingly. 368 * 369 * The context ban, and ultimately the client ban, mechanism are safety 370 * valves if client submission ends up resulting in nothing more than 371 * subsequent hangs. 372 */ 373 374 if (rq) { 375 /* 376 * Try to restore the logical GPU state to match the 377 * continuation of the request queue. If we skip the 378 * context/PD restore, then the next request may try to execute 379 * assuming that its context is valid and loaded on the GPU and 380 * so may try to access invalid memory, prompting repeated GPU 381 * hangs. 382 * 383 * If the request was guilty, we still restore the logical 384 * state in case the next request requires it (e.g. the 385 * aliasing ppgtt), but skip over the hung batch. 386 * 387 * If the request was innocent, we try to replay the request 388 * with the restored context. 389 */ 390 __i915_request_reset(rq, stalled); 391 392 GEM_BUG_ON(rq->ring != engine->legacy.ring); 393 head = rq->head; 394 } else { 395 head = engine->legacy.ring->tail; 396 } 397 engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head); 398 399 spin_unlock_irqrestore(&engine->active.lock, flags); 400 } 401 402 static void reset_finish(struct intel_engine_cs *engine) 403 { 404 } 405 406 static void reset_cancel(struct intel_engine_cs *engine) 407 { 408 struct i915_request *request; 409 unsigned long flags; 410 411 spin_lock_irqsave(&engine->active.lock, flags); 412 413 /* Mark all submitted requests as skipped. */ 414 list_for_each_entry(request, &engine->active.requests, sched.link) 415 i915_request_put(i915_request_mark_eio(request)); 416 intel_engine_signal_breadcrumbs(engine); 417 418 /* Remaining _unready_ requests will be nop'ed when submitted */ 419 420 spin_unlock_irqrestore(&engine->active.lock, flags); 421 } 422 423 static void i9xx_submit_request(struct i915_request *request) 424 { 425 i915_request_submit(request); 426 wmb(); /* paranoid flush writes out of the WCB before mmio */ 427 428 ENGINE_WRITE(request->engine, RING_TAIL, 429 intel_ring_set_tail(request->ring, request->tail)); 430 } 431 432 static void __ring_context_fini(struct intel_context *ce) 433 { 434 i915_vma_put(ce->state); 435 } 436 437 static void ring_context_destroy(struct kref *ref) 438 { 439 struct intel_context *ce = container_of(ref, typeof(*ce), ref); 440 441 GEM_BUG_ON(intel_context_is_pinned(ce)); 442 443 if (ce->state) 444 __ring_context_fini(ce); 445 446 intel_context_fini(ce); 447 intel_context_free(ce); 448 } 449 450 static int ring_context_init_default_state(struct intel_context *ce, 451 struct i915_gem_ww_ctx *ww) 452 { 453 struct drm_i915_gem_object *obj = ce->state->obj; 454 void *vaddr; 455 456 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 457 if (IS_ERR(vaddr)) 458 return PTR_ERR(vaddr); 459 460 shmem_read(ce->engine->default_state, 0, 461 vaddr, ce->engine->context_size); 462 463 i915_gem_object_flush_map(obj); 464 __i915_gem_object_release_map(obj); 465 466 __set_bit(CONTEXT_VALID_BIT, &ce->flags); 467 return 0; 468 } 469 470 static int ring_context_pre_pin(struct intel_context *ce, 471 struct i915_gem_ww_ctx *ww, 472 void **unused) 473 { 474 struct i915_address_space *vm; 475 int err = 0; 476 477 if (ce->engine->default_state && 478 !test_bit(CONTEXT_VALID_BIT, &ce->flags)) { 479 err = ring_context_init_default_state(ce, ww); 480 if (err) 481 return err; 482 } 483 484 vm = vm_alias(ce->vm); 485 if (vm) 486 err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)), ww); 487 488 return err; 489 } 490 491 static void __context_unpin_ppgtt(struct intel_context *ce) 492 { 493 struct i915_address_space *vm; 494 495 vm = vm_alias(ce->vm); 496 if (vm) 497 gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm)); 498 } 499 500 static void ring_context_unpin(struct intel_context *ce) 501 { 502 } 503 504 static void ring_context_post_unpin(struct intel_context *ce) 505 { 506 __context_unpin_ppgtt(ce); 507 } 508 509 static struct i915_vma * 510 alloc_context_vma(struct intel_engine_cs *engine) 511 { 512 struct drm_i915_private *i915 = engine->i915; 513 struct drm_i915_gem_object *obj; 514 struct i915_vma *vma; 515 int err; 516 517 obj = i915_gem_object_create_shmem(i915, engine->context_size); 518 if (IS_ERR(obj)) 519 return ERR_CAST(obj); 520 521 /* 522 * Try to make the context utilize L3 as well as LLC. 523 * 524 * On VLV we don't have L3 controls in the PTEs so we 525 * shouldn't touch the cache level, especially as that 526 * would make the object snooped which might have a 527 * negative performance impact. 528 * 529 * Snooping is required on non-llc platforms in execlist 530 * mode, but since all GGTT accesses use PAT entry 0 we 531 * get snooping anyway regardless of cache_level. 532 * 533 * This is only applicable for Ivy Bridge devices since 534 * later platforms don't have L3 control bits in the PTE. 535 */ 536 if (IS_IVYBRIDGE(i915)) 537 i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC); 538 539 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 540 if (IS_ERR(vma)) { 541 err = PTR_ERR(vma); 542 goto err_obj; 543 } 544 545 return vma; 546 547 err_obj: 548 i915_gem_object_put(obj); 549 return ERR_PTR(err); 550 } 551 552 static int ring_context_alloc(struct intel_context *ce) 553 { 554 struct intel_engine_cs *engine = ce->engine; 555 556 /* One ringbuffer to rule them all */ 557 GEM_BUG_ON(!engine->legacy.ring); 558 ce->ring = engine->legacy.ring; 559 ce->timeline = intel_timeline_get(engine->legacy.timeline); 560 561 GEM_BUG_ON(ce->state); 562 if (engine->context_size) { 563 struct i915_vma *vma; 564 565 vma = alloc_context_vma(engine); 566 if (IS_ERR(vma)) 567 return PTR_ERR(vma); 568 569 ce->state = vma; 570 } 571 572 return 0; 573 } 574 575 static int ring_context_pin(struct intel_context *ce, void *unused) 576 { 577 return 0; 578 } 579 580 static void ring_context_reset(struct intel_context *ce) 581 { 582 intel_ring_reset(ce->ring, ce->ring->emit); 583 clear_bit(CONTEXT_VALID_BIT, &ce->flags); 584 } 585 586 static const struct intel_context_ops ring_context_ops = { 587 .alloc = ring_context_alloc, 588 589 .pre_pin = ring_context_pre_pin, 590 .pin = ring_context_pin, 591 .unpin = ring_context_unpin, 592 .post_unpin = ring_context_post_unpin, 593 594 .enter = intel_context_enter_engine, 595 .exit = intel_context_exit_engine, 596 597 .reset = ring_context_reset, 598 .destroy = ring_context_destroy, 599 }; 600 601 static int load_pd_dir(struct i915_request *rq, 602 struct i915_address_space *vm, 603 u32 valid) 604 { 605 const struct intel_engine_cs * const engine = rq->engine; 606 u32 *cs; 607 608 cs = intel_ring_begin(rq, 12); 609 if (IS_ERR(cs)) 610 return PTR_ERR(cs); 611 612 *cs++ = MI_LOAD_REGISTER_IMM(1); 613 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); 614 *cs++ = valid; 615 616 *cs++ = MI_LOAD_REGISTER_IMM(1); 617 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); 618 *cs++ = pp_dir(vm); 619 620 /* Stall until the page table load is complete? */ 621 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 622 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); 623 *cs++ = intel_gt_scratch_offset(engine->gt, 624 INTEL_GT_SCRATCH_FIELD_DEFAULT); 625 626 *cs++ = MI_LOAD_REGISTER_IMM(1); 627 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); 628 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); 629 630 intel_ring_advance(rq, cs); 631 632 return rq->engine->emit_flush(rq, EMIT_FLUSH); 633 } 634 635 static int mi_set_context(struct i915_request *rq, 636 struct intel_context *ce, 637 u32 flags) 638 { 639 struct intel_engine_cs *engine = rq->engine; 640 struct drm_i915_private *i915 = engine->i915; 641 enum intel_engine_id id; 642 const int num_engines = 643 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; 644 bool force_restore = false; 645 int len; 646 u32 *cs; 647 648 len = 4; 649 if (GRAPHICS_VER(i915) == 7) 650 len += 2 + (num_engines ? 4 * num_engines + 6 : 0); 651 else if (GRAPHICS_VER(i915) == 5) 652 len += 2; 653 if (flags & MI_FORCE_RESTORE) { 654 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); 655 flags &= ~MI_FORCE_RESTORE; 656 force_restore = true; 657 len += 2; 658 } 659 660 cs = intel_ring_begin(rq, len); 661 if (IS_ERR(cs)) 662 return PTR_ERR(cs); 663 664 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ 665 if (GRAPHICS_VER(i915) == 7) { 666 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 667 if (num_engines) { 668 struct intel_engine_cs *signaller; 669 670 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); 671 for_each_engine(signaller, engine->gt, id) { 672 if (signaller == engine) 673 continue; 674 675 *cs++ = i915_mmio_reg_offset( 676 RING_PSMI_CTL(signaller->mmio_base)); 677 *cs++ = _MASKED_BIT_ENABLE( 678 GEN6_PSMI_SLEEP_MSG_DISABLE); 679 } 680 } 681 } else if (GRAPHICS_VER(i915) == 5) { 682 /* 683 * This w/a is only listed for pre-production ilk a/b steppings, 684 * but is also mentioned for programming the powerctx. To be 685 * safe, just apply the workaround; we do not use SyncFlush so 686 * this should never take effect and so be a no-op! 687 */ 688 *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN; 689 } 690 691 if (force_restore) { 692 /* 693 * The HW doesn't handle being told to restore the current 694 * context very well. Quite often it likes goes to go off and 695 * sulk, especially when it is meant to be reloading PP_DIR. 696 * A very simple fix to force the reload is to simply switch 697 * away from the current context and back again. 698 * 699 * Note that the kernel_context will contain random state 700 * following the INHIBIT_RESTORE. We accept this since we 701 * never use the kernel_context state; it is merely a 702 * placeholder we use to flush other contexts. 703 */ 704 *cs++ = MI_SET_CONTEXT; 705 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | 706 MI_MM_SPACE_GTT | 707 MI_RESTORE_INHIBIT; 708 } 709 710 *cs++ = MI_NOOP; 711 *cs++ = MI_SET_CONTEXT; 712 *cs++ = i915_ggtt_offset(ce->state) | flags; 713 /* 714 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP 715 * WaMiSetContext_Hang:snb,ivb,vlv 716 */ 717 *cs++ = MI_NOOP; 718 719 if (GRAPHICS_VER(i915) == 7) { 720 if (num_engines) { 721 struct intel_engine_cs *signaller; 722 i915_reg_t last_reg = {}; /* keep gcc quiet */ 723 724 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); 725 for_each_engine(signaller, engine->gt, id) { 726 if (signaller == engine) 727 continue; 728 729 last_reg = RING_PSMI_CTL(signaller->mmio_base); 730 *cs++ = i915_mmio_reg_offset(last_reg); 731 *cs++ = _MASKED_BIT_DISABLE( 732 GEN6_PSMI_SLEEP_MSG_DISABLE); 733 } 734 735 /* Insert a delay before the next switch! */ 736 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 737 *cs++ = i915_mmio_reg_offset(last_reg); 738 *cs++ = intel_gt_scratch_offset(engine->gt, 739 INTEL_GT_SCRATCH_FIELD_DEFAULT); 740 *cs++ = MI_NOOP; 741 } 742 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 743 } else if (GRAPHICS_VER(i915) == 5) { 744 *cs++ = MI_SUSPEND_FLUSH; 745 } 746 747 intel_ring_advance(rq, cs); 748 749 return 0; 750 } 751 752 static int remap_l3_slice(struct i915_request *rq, int slice) 753 { 754 #define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32)) 755 u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice]; 756 int i; 757 758 if (!remap_info) 759 return 0; 760 761 cs = intel_ring_begin(rq, L3LOG_DW * 2 + 2); 762 if (IS_ERR(cs)) 763 return PTR_ERR(cs); 764 765 /* 766 * Note: We do not worry about the concurrent register cacheline hang 767 * here because no other code should access these registers other than 768 * at initialization time. 769 */ 770 *cs++ = MI_LOAD_REGISTER_IMM(L3LOG_DW); 771 for (i = 0; i < L3LOG_DW; i++) { 772 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); 773 *cs++ = remap_info[i]; 774 } 775 *cs++ = MI_NOOP; 776 intel_ring_advance(rq, cs); 777 778 return 0; 779 #undef L3LOG_DW 780 } 781 782 static int remap_l3(struct i915_request *rq) 783 { 784 struct i915_gem_context *ctx = i915_request_gem_context(rq); 785 int i, err; 786 787 if (!ctx || !ctx->remap_slice) 788 return 0; 789 790 for (i = 0; i < MAX_L3_SLICES; i++) { 791 if (!(ctx->remap_slice & BIT(i))) 792 continue; 793 794 err = remap_l3_slice(rq, i); 795 if (err) 796 return err; 797 } 798 799 ctx->remap_slice = 0; 800 return 0; 801 } 802 803 static int switch_mm(struct i915_request *rq, struct i915_address_space *vm) 804 { 805 int ret; 806 807 if (!vm) 808 return 0; 809 810 ret = rq->engine->emit_flush(rq, EMIT_FLUSH); 811 if (ret) 812 return ret; 813 814 /* 815 * Not only do we need a full barrier (post-sync write) after 816 * invalidating the TLBs, but we need to wait a little bit 817 * longer. Whether this is merely delaying us, or the 818 * subsequent flush is a key part of serialising with the 819 * post-sync op, this extra pass appears vital before a 820 * mm switch! 821 */ 822 ret = load_pd_dir(rq, vm, PP_DIR_DCLV_2G); 823 if (ret) 824 return ret; 825 826 return rq->engine->emit_flush(rq, EMIT_INVALIDATE); 827 } 828 829 static int clear_residuals(struct i915_request *rq) 830 { 831 struct intel_engine_cs *engine = rq->engine; 832 int ret; 833 834 ret = switch_mm(rq, vm_alias(engine->kernel_context->vm)); 835 if (ret) 836 return ret; 837 838 if (engine->kernel_context->state) { 839 ret = mi_set_context(rq, 840 engine->kernel_context, 841 MI_MM_SPACE_GTT | MI_RESTORE_INHIBIT); 842 if (ret) 843 return ret; 844 } 845 846 ret = engine->emit_bb_start(rq, 847 engine->wa_ctx.vma->node.start, 0, 848 0); 849 if (ret) 850 return ret; 851 852 ret = engine->emit_flush(rq, EMIT_FLUSH); 853 if (ret) 854 return ret; 855 856 /* Always invalidate before the next switch_mm() */ 857 return engine->emit_flush(rq, EMIT_INVALIDATE); 858 } 859 860 static int switch_context(struct i915_request *rq) 861 { 862 struct intel_engine_cs *engine = rq->engine; 863 struct intel_context *ce = rq->context; 864 void **residuals = NULL; 865 int ret; 866 867 GEM_BUG_ON(HAS_EXECLISTS(engine->i915)); 868 869 if (engine->wa_ctx.vma && ce != engine->kernel_context) { 870 if (engine->wa_ctx.vma->private != ce && 871 i915_mitigate_clear_residuals()) { 872 ret = clear_residuals(rq); 873 if (ret) 874 return ret; 875 876 residuals = &engine->wa_ctx.vma->private; 877 } 878 } 879 880 ret = switch_mm(rq, vm_alias(ce->vm)); 881 if (ret) 882 return ret; 883 884 if (ce->state) { 885 u32 flags; 886 887 GEM_BUG_ON(engine->id != RCS0); 888 889 /* For resource streamer on HSW+ and power context elsewhere */ 890 BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN != MI_SAVE_EXT_STATE_EN); 891 BUILD_BUG_ON(HSW_MI_RS_RESTORE_STATE_EN != MI_RESTORE_EXT_STATE_EN); 892 893 flags = MI_SAVE_EXT_STATE_EN | MI_MM_SPACE_GTT; 894 if (test_bit(CONTEXT_VALID_BIT, &ce->flags)) 895 flags |= MI_RESTORE_EXT_STATE_EN; 896 else 897 flags |= MI_RESTORE_INHIBIT; 898 899 ret = mi_set_context(rq, ce, flags); 900 if (ret) 901 return ret; 902 } 903 904 ret = remap_l3(rq); 905 if (ret) 906 return ret; 907 908 /* 909 * Now past the point of no return, this request _will_ be emitted. 910 * 911 * Or at least this preamble will be emitted, the request may be 912 * interrupted prior to submitting the user payload. If so, we 913 * still submit the "empty" request in order to preserve global 914 * state tracking such as this, our tracking of the current 915 * dirty context. 916 */ 917 if (residuals) { 918 intel_context_put(*residuals); 919 *residuals = intel_context_get(ce); 920 } 921 922 return 0; 923 } 924 925 static int ring_request_alloc(struct i915_request *request) 926 { 927 int ret; 928 929 GEM_BUG_ON(!intel_context_is_pinned(request->context)); 930 GEM_BUG_ON(i915_request_timeline(request)->has_initial_breadcrumb); 931 932 /* 933 * Flush enough space to reduce the likelihood of waiting after 934 * we start building the request - in which case we will just 935 * have to repeat work. 936 */ 937 request->reserved_space += LEGACY_REQUEST_SIZE; 938 939 /* Unconditionally invalidate GPU caches and TLBs. */ 940 ret = request->engine->emit_flush(request, EMIT_INVALIDATE); 941 if (ret) 942 return ret; 943 944 ret = switch_context(request); 945 if (ret) 946 return ret; 947 948 request->reserved_space -= LEGACY_REQUEST_SIZE; 949 return 0; 950 } 951 952 static void gen6_bsd_submit_request(struct i915_request *request) 953 { 954 struct intel_uncore *uncore = request->engine->uncore; 955 956 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 957 958 /* Every tail move must follow the sequence below */ 959 960 /* Disable notification that the ring is IDLE. The GT 961 * will then assume that it is busy and bring it out of rc6. 962 */ 963 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL, 964 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); 965 966 /* Clear the context id. Here be magic! */ 967 intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0); 968 969 /* Wait for the ring not to be idle, i.e. for it to wake up. */ 970 if (__intel_wait_for_register_fw(uncore, 971 GEN6_BSD_SLEEP_PSMI_CONTROL, 972 GEN6_BSD_SLEEP_INDICATOR, 973 0, 974 1000, 0, NULL)) 975 drm_err(&uncore->i915->drm, 976 "timed out waiting for the BSD ring to wake up\n"); 977 978 /* Now that the ring is fully powered up, update the tail */ 979 i9xx_submit_request(request); 980 981 /* Let the ring send IDLE messages to the GT again, 982 * and so let it sleep to conserve power when idle. 983 */ 984 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL, 985 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); 986 987 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 988 } 989 990 static void i9xx_set_default_submission(struct intel_engine_cs *engine) 991 { 992 engine->submit_request = i9xx_submit_request; 993 } 994 995 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) 996 { 997 engine->submit_request = gen6_bsd_submit_request; 998 } 999 1000 static void ring_release(struct intel_engine_cs *engine) 1001 { 1002 struct drm_i915_private *dev_priv = engine->i915; 1003 1004 drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) > 2 && 1005 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); 1006 1007 intel_engine_cleanup_common(engine); 1008 1009 if (engine->wa_ctx.vma) { 1010 intel_context_put(engine->wa_ctx.vma->private); 1011 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); 1012 } 1013 1014 intel_ring_unpin(engine->legacy.ring); 1015 intel_ring_put(engine->legacy.ring); 1016 1017 intel_timeline_unpin(engine->legacy.timeline); 1018 intel_timeline_put(engine->legacy.timeline); 1019 } 1020 1021 static void irq_handler(struct intel_engine_cs *engine, u16 iir) 1022 { 1023 intel_engine_signal_breadcrumbs(engine); 1024 } 1025 1026 static void setup_irq(struct intel_engine_cs *engine) 1027 { 1028 struct drm_i915_private *i915 = engine->i915; 1029 1030 intel_engine_set_irq_handler(engine, irq_handler); 1031 1032 if (GRAPHICS_VER(i915) >= 6) { 1033 engine->irq_enable = gen6_irq_enable; 1034 engine->irq_disable = gen6_irq_disable; 1035 } else if (GRAPHICS_VER(i915) >= 5) { 1036 engine->irq_enable = gen5_irq_enable; 1037 engine->irq_disable = gen5_irq_disable; 1038 } else if (GRAPHICS_VER(i915) >= 3) { 1039 engine->irq_enable = gen3_irq_enable; 1040 engine->irq_disable = gen3_irq_disable; 1041 } else { 1042 engine->irq_enable = gen2_irq_enable; 1043 engine->irq_disable = gen2_irq_disable; 1044 } 1045 } 1046 1047 static void setup_common(struct intel_engine_cs *engine) 1048 { 1049 struct drm_i915_private *i915 = engine->i915; 1050 1051 /* gen8+ are only supported with execlists */ 1052 GEM_BUG_ON(GRAPHICS_VER(i915) >= 8); 1053 1054 setup_irq(engine); 1055 1056 engine->resume = xcs_resume; 1057 engine->sanitize = xcs_sanitize; 1058 1059 engine->reset.prepare = reset_prepare; 1060 engine->reset.rewind = reset_rewind; 1061 engine->reset.cancel = reset_cancel; 1062 engine->reset.finish = reset_finish; 1063 1064 engine->cops = &ring_context_ops; 1065 engine->request_alloc = ring_request_alloc; 1066 1067 /* 1068 * Using a global execution timeline; the previous final breadcrumb is 1069 * equivalent to our next initial bread so we can elide 1070 * engine->emit_init_breadcrumb(). 1071 */ 1072 engine->emit_fini_breadcrumb = gen3_emit_breadcrumb; 1073 if (GRAPHICS_VER(i915) == 5) 1074 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; 1075 1076 engine->set_default_submission = i9xx_set_default_submission; 1077 1078 if (GRAPHICS_VER(i915) >= 6) 1079 engine->emit_bb_start = gen6_emit_bb_start; 1080 else if (GRAPHICS_VER(i915) >= 4) 1081 engine->emit_bb_start = gen4_emit_bb_start; 1082 else if (IS_I830(i915) || IS_I845G(i915)) 1083 engine->emit_bb_start = i830_emit_bb_start; 1084 else 1085 engine->emit_bb_start = gen3_emit_bb_start; 1086 } 1087 1088 static void setup_rcs(struct intel_engine_cs *engine) 1089 { 1090 struct drm_i915_private *i915 = engine->i915; 1091 1092 if (HAS_L3_DPF(i915)) 1093 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; 1094 1095 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; 1096 1097 if (GRAPHICS_VER(i915) >= 7) { 1098 engine->emit_flush = gen7_emit_flush_rcs; 1099 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs; 1100 } else if (GRAPHICS_VER(i915) == 6) { 1101 engine->emit_flush = gen6_emit_flush_rcs; 1102 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs; 1103 } else if (GRAPHICS_VER(i915) == 5) { 1104 engine->emit_flush = gen4_emit_flush_rcs; 1105 } else { 1106 if (GRAPHICS_VER(i915) < 4) 1107 engine->emit_flush = gen2_emit_flush; 1108 else 1109 engine->emit_flush = gen4_emit_flush_rcs; 1110 engine->irq_enable_mask = I915_USER_INTERRUPT; 1111 } 1112 1113 if (IS_HASWELL(i915)) 1114 engine->emit_bb_start = hsw_emit_bb_start; 1115 } 1116 1117 static void setup_vcs(struct intel_engine_cs *engine) 1118 { 1119 struct drm_i915_private *i915 = engine->i915; 1120 1121 if (GRAPHICS_VER(i915) >= 6) { 1122 /* gen6 bsd needs a special wa for tail updates */ 1123 if (GRAPHICS_VER(i915) == 6) 1124 engine->set_default_submission = gen6_bsd_set_default_submission; 1125 engine->emit_flush = gen6_emit_flush_vcs; 1126 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; 1127 1128 if (GRAPHICS_VER(i915) == 6) 1129 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; 1130 else 1131 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; 1132 } else { 1133 engine->emit_flush = gen4_emit_flush_vcs; 1134 if (GRAPHICS_VER(i915) == 5) 1135 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; 1136 else 1137 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; 1138 } 1139 } 1140 1141 static void setup_bcs(struct intel_engine_cs *engine) 1142 { 1143 struct drm_i915_private *i915 = engine->i915; 1144 1145 engine->emit_flush = gen6_emit_flush_xcs; 1146 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; 1147 1148 if (GRAPHICS_VER(i915) == 6) 1149 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; 1150 else 1151 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; 1152 } 1153 1154 static void setup_vecs(struct intel_engine_cs *engine) 1155 { 1156 struct drm_i915_private *i915 = engine->i915; 1157 1158 GEM_BUG_ON(GRAPHICS_VER(i915) < 7); 1159 1160 engine->emit_flush = gen6_emit_flush_xcs; 1161 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; 1162 engine->irq_enable = hsw_irq_enable_vecs; 1163 engine->irq_disable = hsw_irq_disable_vecs; 1164 1165 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; 1166 } 1167 1168 static int gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine, 1169 struct i915_vma * const vma) 1170 { 1171 return gen7_setup_clear_gpr_bb(engine, vma); 1172 } 1173 1174 static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine, 1175 struct i915_gem_ww_ctx *ww, 1176 struct i915_vma *vma) 1177 { 1178 int err; 1179 1180 err = i915_vma_pin_ww(vma, ww, 0, 0, PIN_USER | PIN_HIGH); 1181 if (err) 1182 return err; 1183 1184 err = i915_vma_sync(vma); 1185 if (err) 1186 goto err_unpin; 1187 1188 err = gen7_ctx_switch_bb_setup(engine, vma); 1189 if (err) 1190 goto err_unpin; 1191 1192 engine->wa_ctx.vma = vma; 1193 return 0; 1194 1195 err_unpin: 1196 i915_vma_unpin(vma); 1197 return err; 1198 } 1199 1200 static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine) 1201 { 1202 struct drm_i915_gem_object *obj; 1203 struct i915_vma *vma; 1204 int size, err; 1205 1206 if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS) 1207 return 0; 1208 1209 err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */); 1210 if (err < 0) 1211 return ERR_PTR(err); 1212 if (!err) 1213 return NULL; 1214 1215 size = ALIGN(err, PAGE_SIZE); 1216 1217 obj = i915_gem_object_create_internal(engine->i915, size); 1218 if (IS_ERR(obj)) 1219 return ERR_CAST(obj); 1220 1221 vma = i915_vma_instance(obj, engine->gt->vm, NULL); 1222 if (IS_ERR(vma)) { 1223 i915_gem_object_put(obj); 1224 return ERR_CAST(vma); 1225 } 1226 1227 vma->private = intel_context_create(engine); /* dummy residuals */ 1228 if (IS_ERR(vma->private)) { 1229 err = PTR_ERR(vma->private); 1230 vma->private = NULL; 1231 i915_gem_object_put(obj); 1232 return ERR_PTR(err); 1233 } 1234 1235 return vma; 1236 } 1237 1238 int intel_ring_submission_setup(struct intel_engine_cs *engine) 1239 { 1240 struct i915_gem_ww_ctx ww; 1241 struct intel_timeline *timeline; 1242 struct intel_ring *ring; 1243 struct i915_vma *gen7_wa_vma; 1244 int err; 1245 1246 setup_common(engine); 1247 1248 switch (engine->class) { 1249 case RENDER_CLASS: 1250 setup_rcs(engine); 1251 break; 1252 case VIDEO_DECODE_CLASS: 1253 setup_vcs(engine); 1254 break; 1255 case COPY_ENGINE_CLASS: 1256 setup_bcs(engine); 1257 break; 1258 case VIDEO_ENHANCEMENT_CLASS: 1259 setup_vecs(engine); 1260 break; 1261 default: 1262 MISSING_CASE(engine->class); 1263 return -ENODEV; 1264 } 1265 1266 timeline = intel_timeline_create_from_engine(engine, 1267 I915_GEM_HWS_SEQNO_ADDR); 1268 if (IS_ERR(timeline)) { 1269 err = PTR_ERR(timeline); 1270 goto err; 1271 } 1272 GEM_BUG_ON(timeline->has_initial_breadcrumb); 1273 1274 ring = intel_engine_create_ring(engine, SZ_16K); 1275 if (IS_ERR(ring)) { 1276 err = PTR_ERR(ring); 1277 goto err_timeline; 1278 } 1279 1280 GEM_BUG_ON(engine->legacy.ring); 1281 engine->legacy.ring = ring; 1282 engine->legacy.timeline = timeline; 1283 1284 gen7_wa_vma = gen7_ctx_vma(engine); 1285 if (IS_ERR(gen7_wa_vma)) { 1286 err = PTR_ERR(gen7_wa_vma); 1287 goto err_ring; 1288 } 1289 1290 i915_gem_ww_ctx_init(&ww, false); 1291 1292 retry: 1293 err = i915_gem_object_lock(timeline->hwsp_ggtt->obj, &ww); 1294 if (!err && gen7_wa_vma) 1295 err = i915_gem_object_lock(gen7_wa_vma->obj, &ww); 1296 if (!err && engine->legacy.ring->vma->obj) 1297 err = i915_gem_object_lock(engine->legacy.ring->vma->obj, &ww); 1298 if (!err) 1299 err = intel_timeline_pin(timeline, &ww); 1300 if (!err) { 1301 err = intel_ring_pin(ring, &ww); 1302 if (err) 1303 intel_timeline_unpin(timeline); 1304 } 1305 if (err) 1306 goto out; 1307 1308 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma); 1309 1310 if (gen7_wa_vma) { 1311 err = gen7_ctx_switch_bb_init(engine, &ww, gen7_wa_vma); 1312 if (err) { 1313 intel_ring_unpin(ring); 1314 intel_timeline_unpin(timeline); 1315 } 1316 } 1317 1318 out: 1319 if (err == -EDEADLK) { 1320 err = i915_gem_ww_ctx_backoff(&ww); 1321 if (!err) 1322 goto retry; 1323 } 1324 i915_gem_ww_ctx_fini(&ww); 1325 if (err) 1326 goto err_gen7_put; 1327 1328 /* Finally, take ownership and responsibility for cleanup! */ 1329 engine->release = ring_release; 1330 1331 return 0; 1332 1333 err_gen7_put: 1334 if (gen7_wa_vma) { 1335 intel_context_put(gen7_wa_vma->private); 1336 i915_gem_object_put(gen7_wa_vma->obj); 1337 } 1338 err_ring: 1339 intel_ring_put(ring); 1340 err_timeline: 1341 intel_timeline_put(timeline); 1342 err: 1343 intel_engine_cleanup_common(engine); 1344 return err; 1345 } 1346 1347 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1348 #include "selftest_ring_submission.c" 1349 #endif 1350