1 /* 2 * Copyright © 2008-2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Zou Nan hai <nanhai.zou@intel.com> 26 * Xiang Hai hao<haihao.xiang@intel.com> 27 * 28 */ 29 30 #include "gen2_engine_cs.h" 31 #include "gen6_engine_cs.h" 32 #include "gen6_ppgtt.h" 33 #include "gen7_renderclear.h" 34 #include "i915_drv.h" 35 #include "intel_breadcrumbs.h" 36 #include "intel_context.h" 37 #include "intel_gt.h" 38 #include "intel_reset.h" 39 #include "intel_ring.h" 40 #include "shmem_utils.h" 41 42 /* Rough estimate of the typical request size, performing a flush, 43 * set-context and then emitting the batch. 44 */ 45 #define LEGACY_REQUEST_SIZE 200 46 47 static void set_hwstam(struct intel_engine_cs *engine, u32 mask) 48 { 49 /* 50 * Keep the render interrupt unmasked as this papers over 51 * lost interrupts following a reset. 52 */ 53 if (engine->class == RENDER_CLASS) { 54 if (INTEL_GEN(engine->i915) >= 6) 55 mask &= ~BIT(0); 56 else 57 mask &= ~I915_USER_INTERRUPT; 58 } 59 60 intel_engine_set_hwsp_writemask(engine, mask); 61 } 62 63 static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys) 64 { 65 u32 addr; 66 67 addr = lower_32_bits(phys); 68 if (INTEL_GEN(engine->i915) >= 4) 69 addr |= (phys >> 28) & 0xf0; 70 71 intel_uncore_write(engine->uncore, HWS_PGA, addr); 72 } 73 74 static struct page *status_page(struct intel_engine_cs *engine) 75 { 76 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; 77 78 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); 79 return sg_page(obj->mm.pages->sgl); 80 } 81 82 static void ring_setup_phys_status_page(struct intel_engine_cs *engine) 83 { 84 set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine)))); 85 set_hwstam(engine, ~0u); 86 } 87 88 static void set_hwsp(struct intel_engine_cs *engine, u32 offset) 89 { 90 i915_reg_t hwsp; 91 92 /* 93 * The ring status page addresses are no longer next to the rest of 94 * the ring registers as of gen7. 95 */ 96 if (IS_GEN(engine->i915, 7)) { 97 switch (engine->id) { 98 /* 99 * No more rings exist on Gen7. Default case is only to shut up 100 * gcc switch check warning. 101 */ 102 default: 103 GEM_BUG_ON(engine->id); 104 /* fallthrough */ 105 case RCS0: 106 hwsp = RENDER_HWS_PGA_GEN7; 107 break; 108 case BCS0: 109 hwsp = BLT_HWS_PGA_GEN7; 110 break; 111 case VCS0: 112 hwsp = BSD_HWS_PGA_GEN7; 113 break; 114 case VECS0: 115 hwsp = VEBOX_HWS_PGA_GEN7; 116 break; 117 } 118 } else if (IS_GEN(engine->i915, 6)) { 119 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); 120 } else { 121 hwsp = RING_HWS_PGA(engine->mmio_base); 122 } 123 124 intel_uncore_write(engine->uncore, hwsp, offset); 125 intel_uncore_posting_read(engine->uncore, hwsp); 126 } 127 128 static void flush_cs_tlb(struct intel_engine_cs *engine) 129 { 130 struct drm_i915_private *dev_priv = engine->i915; 131 132 if (!IS_GEN_RANGE(dev_priv, 6, 7)) 133 return; 134 135 /* ring should be idle before issuing a sync flush*/ 136 drm_WARN_ON(&dev_priv->drm, 137 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); 138 139 ENGINE_WRITE(engine, RING_INSTPM, 140 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | 141 INSTPM_SYNC_FLUSH)); 142 if (intel_wait_for_register(engine->uncore, 143 RING_INSTPM(engine->mmio_base), 144 INSTPM_SYNC_FLUSH, 0, 145 1000)) 146 drm_err(&dev_priv->drm, 147 "%s: wait for SyncFlush to complete for TLB invalidation timed out\n", 148 engine->name); 149 } 150 151 static void ring_setup_status_page(struct intel_engine_cs *engine) 152 { 153 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); 154 set_hwstam(engine, ~0u); 155 156 flush_cs_tlb(engine); 157 } 158 159 static bool stop_ring(struct intel_engine_cs *engine) 160 { 161 struct drm_i915_private *dev_priv = engine->i915; 162 163 if (INTEL_GEN(dev_priv) > 2) { 164 ENGINE_WRITE(engine, 165 RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING)); 166 if (intel_wait_for_register(engine->uncore, 167 RING_MI_MODE(engine->mmio_base), 168 MODE_IDLE, 169 MODE_IDLE, 170 1000)) { 171 drm_err(&dev_priv->drm, 172 "%s : timed out trying to stop ring\n", 173 engine->name); 174 175 /* 176 * Sometimes we observe that the idle flag is not 177 * set even though the ring is empty. So double 178 * check before giving up. 179 */ 180 if (ENGINE_READ(engine, RING_HEAD) != 181 ENGINE_READ(engine, RING_TAIL)) 182 return false; 183 } 184 } 185 186 ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL)); 187 188 ENGINE_WRITE(engine, RING_HEAD, 0); 189 ENGINE_WRITE(engine, RING_TAIL, 0); 190 191 /* The ring must be empty before it is disabled */ 192 ENGINE_WRITE(engine, RING_CTL, 0); 193 194 return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0; 195 } 196 197 static struct i915_address_space *vm_alias(struct i915_address_space *vm) 198 { 199 if (i915_is_ggtt(vm)) 200 vm = &i915_vm_to_ggtt(vm)->alias->vm; 201 202 return vm; 203 } 204 205 static u32 pp_dir(struct i915_address_space *vm) 206 { 207 return to_gen6_ppgtt(i915_vm_to_ppgtt(vm))->pp_dir; 208 } 209 210 static void set_pp_dir(struct intel_engine_cs *engine) 211 { 212 struct i915_address_space *vm = vm_alias(engine->gt->vm); 213 214 if (vm) { 215 ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G); 216 ENGINE_WRITE(engine, RING_PP_DIR_BASE, pp_dir(vm)); 217 } 218 } 219 220 static int xcs_resume(struct intel_engine_cs *engine) 221 { 222 struct drm_i915_private *dev_priv = engine->i915; 223 struct intel_ring *ring = engine->legacy.ring; 224 int ret = 0; 225 226 ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n", 227 ring->head, ring->tail); 228 229 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); 230 231 /* WaClearRingBufHeadRegAtInit:ctg,elk */ 232 if (!stop_ring(engine)) { 233 /* G45 ring initialization often fails to reset head to zero */ 234 drm_dbg(&dev_priv->drm, "%s head not reset to zero " 235 "ctl %08x head %08x tail %08x start %08x\n", 236 engine->name, 237 ENGINE_READ(engine, RING_CTL), 238 ENGINE_READ(engine, RING_HEAD), 239 ENGINE_READ(engine, RING_TAIL), 240 ENGINE_READ(engine, RING_START)); 241 242 if (!stop_ring(engine)) { 243 drm_err(&dev_priv->drm, 244 "failed to set %s head to zero " 245 "ctl %08x head %08x tail %08x start %08x\n", 246 engine->name, 247 ENGINE_READ(engine, RING_CTL), 248 ENGINE_READ(engine, RING_HEAD), 249 ENGINE_READ(engine, RING_TAIL), 250 ENGINE_READ(engine, RING_START)); 251 ret = -EIO; 252 goto out; 253 } 254 } 255 256 if (HWS_NEEDS_PHYSICAL(dev_priv)) 257 ring_setup_phys_status_page(engine); 258 else 259 ring_setup_status_page(engine); 260 261 intel_breadcrumbs_reset(engine->breadcrumbs); 262 263 /* Enforce ordering by reading HEAD register back */ 264 ENGINE_POSTING_READ(engine, RING_HEAD); 265 266 /* 267 * Initialize the ring. This must happen _after_ we've cleared the ring 268 * registers with the above sequence (the readback of the HEAD registers 269 * also enforces ordering), otherwise the hw might lose the new ring 270 * register values. 271 */ 272 ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma)); 273 274 /* Check that the ring offsets point within the ring! */ 275 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); 276 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); 277 intel_ring_update_space(ring); 278 279 set_pp_dir(engine); 280 281 /* First wake the ring up to an empty/idle ring */ 282 ENGINE_WRITE(engine, RING_HEAD, ring->head); 283 ENGINE_WRITE(engine, RING_TAIL, ring->head); 284 ENGINE_POSTING_READ(engine, RING_TAIL); 285 286 ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID); 287 288 /* If the head is still not zero, the ring is dead */ 289 if (intel_wait_for_register(engine->uncore, 290 RING_CTL(engine->mmio_base), 291 RING_VALID, RING_VALID, 292 50)) { 293 drm_err(&dev_priv->drm, "%s initialization failed " 294 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", 295 engine->name, 296 ENGINE_READ(engine, RING_CTL), 297 ENGINE_READ(engine, RING_CTL) & RING_VALID, 298 ENGINE_READ(engine, RING_HEAD), ring->head, 299 ENGINE_READ(engine, RING_TAIL), ring->tail, 300 ENGINE_READ(engine, RING_START), 301 i915_ggtt_offset(ring->vma)); 302 ret = -EIO; 303 goto out; 304 } 305 306 if (INTEL_GEN(dev_priv) > 2) 307 ENGINE_WRITE(engine, 308 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 309 310 /* Now awake, let it get started */ 311 if (ring->tail != ring->head) { 312 ENGINE_WRITE(engine, RING_TAIL, ring->tail); 313 ENGINE_POSTING_READ(engine, RING_TAIL); 314 } 315 316 /* Papering over lost _interrupts_ immediately following the restart */ 317 intel_engine_signal_breadcrumbs(engine); 318 out: 319 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); 320 321 return ret; 322 } 323 324 static void reset_prepare(struct intel_engine_cs *engine) 325 { 326 struct intel_uncore *uncore = engine->uncore; 327 const u32 base = engine->mmio_base; 328 329 /* 330 * We stop engines, otherwise we might get failed reset and a 331 * dead gpu (on elk). Also as modern gpu as kbl can suffer 332 * from system hang if batchbuffer is progressing when 333 * the reset is issued, regardless of READY_TO_RESET ack. 334 * Thus assume it is best to stop engines on all gens 335 * where we have a gpu reset. 336 * 337 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES) 338 * 339 * WaMediaResetMainRingCleanup:ctg,elk (presumably) 340 * 341 * FIXME: Wa for more modern gens needs to be validated 342 */ 343 ENGINE_TRACE(engine, "\n"); 344 345 if (intel_engine_stop_cs(engine)) 346 ENGINE_TRACE(engine, "timed out on STOP_RING\n"); 347 348 intel_uncore_write_fw(uncore, 349 RING_HEAD(base), 350 intel_uncore_read_fw(uncore, RING_TAIL(base))); 351 intel_uncore_posting_read_fw(uncore, RING_HEAD(base)); /* paranoia */ 352 353 intel_uncore_write_fw(uncore, RING_HEAD(base), 0); 354 intel_uncore_write_fw(uncore, RING_TAIL(base), 0); 355 intel_uncore_posting_read_fw(uncore, RING_TAIL(base)); 356 357 /* The ring must be empty before it is disabled */ 358 intel_uncore_write_fw(uncore, RING_CTL(base), 0); 359 360 /* Check acts as a post */ 361 if (intel_uncore_read_fw(uncore, RING_HEAD(base))) 362 ENGINE_TRACE(engine, "ring head [%x] not parked\n", 363 intel_uncore_read_fw(uncore, RING_HEAD(base))); 364 } 365 366 static void reset_rewind(struct intel_engine_cs *engine, bool stalled) 367 { 368 struct i915_request *pos, *rq; 369 unsigned long flags; 370 u32 head; 371 372 rq = NULL; 373 spin_lock_irqsave(&engine->active.lock, flags); 374 list_for_each_entry(pos, &engine->active.requests, sched.link) { 375 if (!i915_request_completed(pos)) { 376 rq = pos; 377 break; 378 } 379 } 380 381 /* 382 * The guilty request will get skipped on a hung engine. 383 * 384 * Users of client default contexts do not rely on logical 385 * state preserved between batches so it is safe to execute 386 * queued requests following the hang. Non default contexts 387 * rely on preserved state, so skipping a batch loses the 388 * evolution of the state and it needs to be considered corrupted. 389 * Executing more queued batches on top of corrupted state is 390 * risky. But we take the risk by trying to advance through 391 * the queued requests in order to make the client behaviour 392 * more predictable around resets, by not throwing away random 393 * amount of batches it has prepared for execution. Sophisticated 394 * clients can use gem_reset_stats_ioctl and dma fence status 395 * (exported via sync_file info ioctl on explicit fences) to observe 396 * when it loses the context state and should rebuild accordingly. 397 * 398 * The context ban, and ultimately the client ban, mechanism are safety 399 * valves if client submission ends up resulting in nothing more than 400 * subsequent hangs. 401 */ 402 403 if (rq) { 404 /* 405 * Try to restore the logical GPU state to match the 406 * continuation of the request queue. If we skip the 407 * context/PD restore, then the next request may try to execute 408 * assuming that its context is valid and loaded on the GPU and 409 * so may try to access invalid memory, prompting repeated GPU 410 * hangs. 411 * 412 * If the request was guilty, we still restore the logical 413 * state in case the next request requires it (e.g. the 414 * aliasing ppgtt), but skip over the hung batch. 415 * 416 * If the request was innocent, we try to replay the request 417 * with the restored context. 418 */ 419 __i915_request_reset(rq, stalled); 420 421 GEM_BUG_ON(rq->ring != engine->legacy.ring); 422 head = rq->head; 423 } else { 424 head = engine->legacy.ring->tail; 425 } 426 engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head); 427 428 spin_unlock_irqrestore(&engine->active.lock, flags); 429 } 430 431 static void reset_finish(struct intel_engine_cs *engine) 432 { 433 } 434 435 static void reset_cancel(struct intel_engine_cs *engine) 436 { 437 struct i915_request *request; 438 unsigned long flags; 439 440 spin_lock_irqsave(&engine->active.lock, flags); 441 442 /* Mark all submitted requests as skipped. */ 443 list_for_each_entry(request, &engine->active.requests, sched.link) { 444 i915_request_set_error_once(request, -EIO); 445 i915_request_mark_complete(request); 446 } 447 448 /* Remaining _unready_ requests will be nop'ed when submitted */ 449 450 spin_unlock_irqrestore(&engine->active.lock, flags); 451 } 452 453 static void i9xx_submit_request(struct i915_request *request) 454 { 455 i915_request_submit(request); 456 wmb(); /* paranoid flush writes out of the WCB before mmio */ 457 458 ENGINE_WRITE(request->engine, RING_TAIL, 459 intel_ring_set_tail(request->ring, request->tail)); 460 } 461 462 static void __ring_context_fini(struct intel_context *ce) 463 { 464 i915_vma_put(ce->state); 465 } 466 467 static void ring_context_destroy(struct kref *ref) 468 { 469 struct intel_context *ce = container_of(ref, typeof(*ce), ref); 470 471 GEM_BUG_ON(intel_context_is_pinned(ce)); 472 473 if (ce->state) 474 __ring_context_fini(ce); 475 476 intel_context_fini(ce); 477 intel_context_free(ce); 478 } 479 480 static int __context_pin_ppgtt(struct intel_context *ce) 481 { 482 struct i915_address_space *vm; 483 int err = 0; 484 485 vm = vm_alias(ce->vm); 486 if (vm) 487 err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm))); 488 489 return err; 490 } 491 492 static void __context_unpin_ppgtt(struct intel_context *ce) 493 { 494 struct i915_address_space *vm; 495 496 vm = vm_alias(ce->vm); 497 if (vm) 498 gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm)); 499 } 500 501 static void ring_context_unpin(struct intel_context *ce) 502 { 503 __context_unpin_ppgtt(ce); 504 } 505 506 static struct i915_vma * 507 alloc_context_vma(struct intel_engine_cs *engine) 508 { 509 struct drm_i915_private *i915 = engine->i915; 510 struct drm_i915_gem_object *obj; 511 struct i915_vma *vma; 512 int err; 513 514 obj = i915_gem_object_create_shmem(i915, engine->context_size); 515 if (IS_ERR(obj)) 516 return ERR_CAST(obj); 517 518 /* 519 * Try to make the context utilize L3 as well as LLC. 520 * 521 * On VLV we don't have L3 controls in the PTEs so we 522 * shouldn't touch the cache level, especially as that 523 * would make the object snooped which might have a 524 * negative performance impact. 525 * 526 * Snooping is required on non-llc platforms in execlist 527 * mode, but since all GGTT accesses use PAT entry 0 we 528 * get snooping anyway regardless of cache_level. 529 * 530 * This is only applicable for Ivy Bridge devices since 531 * later platforms don't have L3 control bits in the PTE. 532 */ 533 if (IS_IVYBRIDGE(i915)) 534 i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC); 535 536 if (engine->default_state) { 537 void *vaddr; 538 539 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 540 if (IS_ERR(vaddr)) { 541 err = PTR_ERR(vaddr); 542 goto err_obj; 543 } 544 545 shmem_read(engine->default_state, 0, 546 vaddr, engine->context_size); 547 548 i915_gem_object_flush_map(obj); 549 __i915_gem_object_release_map(obj); 550 } 551 552 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 553 if (IS_ERR(vma)) { 554 err = PTR_ERR(vma); 555 goto err_obj; 556 } 557 558 return vma; 559 560 err_obj: 561 i915_gem_object_put(obj); 562 return ERR_PTR(err); 563 } 564 565 static int ring_context_alloc(struct intel_context *ce) 566 { 567 struct intel_engine_cs *engine = ce->engine; 568 569 /* One ringbuffer to rule them all */ 570 GEM_BUG_ON(!engine->legacy.ring); 571 ce->ring = engine->legacy.ring; 572 ce->timeline = intel_timeline_get(engine->legacy.timeline); 573 574 GEM_BUG_ON(ce->state); 575 if (engine->context_size) { 576 struct i915_vma *vma; 577 578 vma = alloc_context_vma(engine); 579 if (IS_ERR(vma)) 580 return PTR_ERR(vma); 581 582 ce->state = vma; 583 if (engine->default_state) 584 __set_bit(CONTEXT_VALID_BIT, &ce->flags); 585 } 586 587 return 0; 588 } 589 590 static int ring_context_pin(struct intel_context *ce) 591 { 592 return __context_pin_ppgtt(ce); 593 } 594 595 static void ring_context_reset(struct intel_context *ce) 596 { 597 intel_ring_reset(ce->ring, ce->ring->emit); 598 } 599 600 static const struct intel_context_ops ring_context_ops = { 601 .alloc = ring_context_alloc, 602 603 .pin = ring_context_pin, 604 .unpin = ring_context_unpin, 605 606 .enter = intel_context_enter_engine, 607 .exit = intel_context_exit_engine, 608 609 .reset = ring_context_reset, 610 .destroy = ring_context_destroy, 611 }; 612 613 static int load_pd_dir(struct i915_request *rq, 614 struct i915_address_space *vm, 615 u32 valid) 616 { 617 const struct intel_engine_cs * const engine = rq->engine; 618 u32 *cs; 619 620 cs = intel_ring_begin(rq, 12); 621 if (IS_ERR(cs)) 622 return PTR_ERR(cs); 623 624 *cs++ = MI_LOAD_REGISTER_IMM(1); 625 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); 626 *cs++ = valid; 627 628 *cs++ = MI_LOAD_REGISTER_IMM(1); 629 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); 630 *cs++ = pp_dir(vm); 631 632 /* Stall until the page table load is complete? */ 633 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 634 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); 635 *cs++ = intel_gt_scratch_offset(engine->gt, 636 INTEL_GT_SCRATCH_FIELD_DEFAULT); 637 638 *cs++ = MI_LOAD_REGISTER_IMM(1); 639 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); 640 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); 641 642 intel_ring_advance(rq, cs); 643 644 return rq->engine->emit_flush(rq, EMIT_FLUSH); 645 } 646 647 static inline int mi_set_context(struct i915_request *rq, 648 struct intel_context *ce, 649 u32 flags) 650 { 651 struct intel_engine_cs *engine = rq->engine; 652 struct drm_i915_private *i915 = engine->i915; 653 enum intel_engine_id id; 654 const int num_engines = 655 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; 656 bool force_restore = false; 657 int len; 658 u32 *cs; 659 660 len = 4; 661 if (IS_GEN(i915, 7)) 662 len += 2 + (num_engines ? 4 * num_engines + 6 : 0); 663 else if (IS_GEN(i915, 5)) 664 len += 2; 665 if (flags & MI_FORCE_RESTORE) { 666 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); 667 flags &= ~MI_FORCE_RESTORE; 668 force_restore = true; 669 len += 2; 670 } 671 672 cs = intel_ring_begin(rq, len); 673 if (IS_ERR(cs)) 674 return PTR_ERR(cs); 675 676 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ 677 if (IS_GEN(i915, 7)) { 678 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 679 if (num_engines) { 680 struct intel_engine_cs *signaller; 681 682 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); 683 for_each_engine(signaller, engine->gt, id) { 684 if (signaller == engine) 685 continue; 686 687 *cs++ = i915_mmio_reg_offset( 688 RING_PSMI_CTL(signaller->mmio_base)); 689 *cs++ = _MASKED_BIT_ENABLE( 690 GEN6_PSMI_SLEEP_MSG_DISABLE); 691 } 692 } 693 } else if (IS_GEN(i915, 5)) { 694 /* 695 * This w/a is only listed for pre-production ilk a/b steppings, 696 * but is also mentioned for programming the powerctx. To be 697 * safe, just apply the workaround; we do not use SyncFlush so 698 * this should never take effect and so be a no-op! 699 */ 700 *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN; 701 } 702 703 if (force_restore) { 704 /* 705 * The HW doesn't handle being told to restore the current 706 * context very well. Quite often it likes goes to go off and 707 * sulk, especially when it is meant to be reloading PP_DIR. 708 * A very simple fix to force the reload is to simply switch 709 * away from the current context and back again. 710 * 711 * Note that the kernel_context will contain random state 712 * following the INHIBIT_RESTORE. We accept this since we 713 * never use the kernel_context state; it is merely a 714 * placeholder we use to flush other contexts. 715 */ 716 *cs++ = MI_SET_CONTEXT; 717 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | 718 MI_MM_SPACE_GTT | 719 MI_RESTORE_INHIBIT; 720 } 721 722 *cs++ = MI_NOOP; 723 *cs++ = MI_SET_CONTEXT; 724 *cs++ = i915_ggtt_offset(ce->state) | flags; 725 /* 726 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP 727 * WaMiSetContext_Hang:snb,ivb,vlv 728 */ 729 *cs++ = MI_NOOP; 730 731 if (IS_GEN(i915, 7)) { 732 if (num_engines) { 733 struct intel_engine_cs *signaller; 734 i915_reg_t last_reg = {}; /* keep gcc quiet */ 735 736 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); 737 for_each_engine(signaller, engine->gt, id) { 738 if (signaller == engine) 739 continue; 740 741 last_reg = RING_PSMI_CTL(signaller->mmio_base); 742 *cs++ = i915_mmio_reg_offset(last_reg); 743 *cs++ = _MASKED_BIT_DISABLE( 744 GEN6_PSMI_SLEEP_MSG_DISABLE); 745 } 746 747 /* Insert a delay before the next switch! */ 748 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 749 *cs++ = i915_mmio_reg_offset(last_reg); 750 *cs++ = intel_gt_scratch_offset(engine->gt, 751 INTEL_GT_SCRATCH_FIELD_DEFAULT); 752 *cs++ = MI_NOOP; 753 } 754 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 755 } else if (IS_GEN(i915, 5)) { 756 *cs++ = MI_SUSPEND_FLUSH; 757 } 758 759 intel_ring_advance(rq, cs); 760 761 return 0; 762 } 763 764 static int remap_l3_slice(struct i915_request *rq, int slice) 765 { 766 u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice]; 767 int i; 768 769 if (!remap_info) 770 return 0; 771 772 cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2); 773 if (IS_ERR(cs)) 774 return PTR_ERR(cs); 775 776 /* 777 * Note: We do not worry about the concurrent register cacheline hang 778 * here because no other code should access these registers other than 779 * at initialization time. 780 */ 781 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); 782 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { 783 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); 784 *cs++ = remap_info[i]; 785 } 786 *cs++ = MI_NOOP; 787 intel_ring_advance(rq, cs); 788 789 return 0; 790 } 791 792 static int remap_l3(struct i915_request *rq) 793 { 794 struct i915_gem_context *ctx = i915_request_gem_context(rq); 795 int i, err; 796 797 if (!ctx || !ctx->remap_slice) 798 return 0; 799 800 for (i = 0; i < MAX_L3_SLICES; i++) { 801 if (!(ctx->remap_slice & BIT(i))) 802 continue; 803 804 err = remap_l3_slice(rq, i); 805 if (err) 806 return err; 807 } 808 809 ctx->remap_slice = 0; 810 return 0; 811 } 812 813 static int switch_mm(struct i915_request *rq, struct i915_address_space *vm) 814 { 815 int ret; 816 817 if (!vm) 818 return 0; 819 820 ret = rq->engine->emit_flush(rq, EMIT_FLUSH); 821 if (ret) 822 return ret; 823 824 /* 825 * Not only do we need a full barrier (post-sync write) after 826 * invalidating the TLBs, but we need to wait a little bit 827 * longer. Whether this is merely delaying us, or the 828 * subsequent flush is a key part of serialising with the 829 * post-sync op, this extra pass appears vital before a 830 * mm switch! 831 */ 832 ret = load_pd_dir(rq, vm, PP_DIR_DCLV_2G); 833 if (ret) 834 return ret; 835 836 return rq->engine->emit_flush(rq, EMIT_INVALIDATE); 837 } 838 839 static int clear_residuals(struct i915_request *rq) 840 { 841 struct intel_engine_cs *engine = rq->engine; 842 int ret; 843 844 ret = switch_mm(rq, vm_alias(engine->kernel_context->vm)); 845 if (ret) 846 return ret; 847 848 if (engine->kernel_context->state) { 849 ret = mi_set_context(rq, 850 engine->kernel_context, 851 MI_MM_SPACE_GTT | MI_RESTORE_INHIBIT); 852 if (ret) 853 return ret; 854 } 855 856 ret = engine->emit_bb_start(rq, 857 engine->wa_ctx.vma->node.start, 0, 858 0); 859 if (ret) 860 return ret; 861 862 ret = engine->emit_flush(rq, EMIT_FLUSH); 863 if (ret) 864 return ret; 865 866 /* Always invalidate before the next switch_mm() */ 867 return engine->emit_flush(rq, EMIT_INVALIDATE); 868 } 869 870 static int switch_context(struct i915_request *rq) 871 { 872 struct intel_engine_cs *engine = rq->engine; 873 struct intel_context *ce = rq->context; 874 void **residuals = NULL; 875 int ret; 876 877 GEM_BUG_ON(HAS_EXECLISTS(engine->i915)); 878 879 if (engine->wa_ctx.vma && ce != engine->kernel_context) { 880 if (engine->wa_ctx.vma->private != ce) { 881 ret = clear_residuals(rq); 882 if (ret) 883 return ret; 884 885 residuals = &engine->wa_ctx.vma->private; 886 } 887 } 888 889 ret = switch_mm(rq, vm_alias(ce->vm)); 890 if (ret) 891 return ret; 892 893 if (ce->state) { 894 u32 flags; 895 896 GEM_BUG_ON(engine->id != RCS0); 897 898 /* For resource streamer on HSW+ and power context elsewhere */ 899 BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN != MI_SAVE_EXT_STATE_EN); 900 BUILD_BUG_ON(HSW_MI_RS_RESTORE_STATE_EN != MI_RESTORE_EXT_STATE_EN); 901 902 flags = MI_SAVE_EXT_STATE_EN | MI_MM_SPACE_GTT; 903 if (test_bit(CONTEXT_VALID_BIT, &ce->flags)) 904 flags |= MI_RESTORE_EXT_STATE_EN; 905 else 906 flags |= MI_RESTORE_INHIBIT; 907 908 ret = mi_set_context(rq, ce, flags); 909 if (ret) 910 return ret; 911 } 912 913 ret = remap_l3(rq); 914 if (ret) 915 return ret; 916 917 /* 918 * Now past the point of no return, this request _will_ be emitted. 919 * 920 * Or at least this preamble will be emitted, the request may be 921 * interrupted prior to submitting the user payload. If so, we 922 * still submit the "empty" request in order to preserve global 923 * state tracking such as this, our tracking of the current 924 * dirty context. 925 */ 926 if (residuals) { 927 intel_context_put(*residuals); 928 *residuals = intel_context_get(ce); 929 } 930 931 return 0; 932 } 933 934 static int ring_request_alloc(struct i915_request *request) 935 { 936 int ret; 937 938 GEM_BUG_ON(!intel_context_is_pinned(request->context)); 939 GEM_BUG_ON(i915_request_timeline(request)->has_initial_breadcrumb); 940 941 /* 942 * Flush enough space to reduce the likelihood of waiting after 943 * we start building the request - in which case we will just 944 * have to repeat work. 945 */ 946 request->reserved_space += LEGACY_REQUEST_SIZE; 947 948 /* Unconditionally invalidate GPU caches and TLBs. */ 949 ret = request->engine->emit_flush(request, EMIT_INVALIDATE); 950 if (ret) 951 return ret; 952 953 ret = switch_context(request); 954 if (ret) 955 return ret; 956 957 request->reserved_space -= LEGACY_REQUEST_SIZE; 958 return 0; 959 } 960 961 static void gen6_bsd_submit_request(struct i915_request *request) 962 { 963 struct intel_uncore *uncore = request->engine->uncore; 964 965 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 966 967 /* Every tail move must follow the sequence below */ 968 969 /* Disable notification that the ring is IDLE. The GT 970 * will then assume that it is busy and bring it out of rc6. 971 */ 972 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL, 973 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); 974 975 /* Clear the context id. Here be magic! */ 976 intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0); 977 978 /* Wait for the ring not to be idle, i.e. for it to wake up. */ 979 if (__intel_wait_for_register_fw(uncore, 980 GEN6_BSD_SLEEP_PSMI_CONTROL, 981 GEN6_BSD_SLEEP_INDICATOR, 982 0, 983 1000, 0, NULL)) 984 drm_err(&uncore->i915->drm, 985 "timed out waiting for the BSD ring to wake up\n"); 986 987 /* Now that the ring is fully powered up, update the tail */ 988 i9xx_submit_request(request); 989 990 /* Let the ring send IDLE messages to the GT again, 991 * and so let it sleep to conserve power when idle. 992 */ 993 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL, 994 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); 995 996 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 997 } 998 999 static void i9xx_set_default_submission(struct intel_engine_cs *engine) 1000 { 1001 engine->submit_request = i9xx_submit_request; 1002 1003 engine->park = NULL; 1004 engine->unpark = NULL; 1005 } 1006 1007 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) 1008 { 1009 i9xx_set_default_submission(engine); 1010 engine->submit_request = gen6_bsd_submit_request; 1011 } 1012 1013 static void ring_release(struct intel_engine_cs *engine) 1014 { 1015 struct drm_i915_private *dev_priv = engine->i915; 1016 1017 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) > 2 && 1018 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); 1019 1020 intel_engine_cleanup_common(engine); 1021 1022 if (engine->wa_ctx.vma) { 1023 intel_context_put(engine->wa_ctx.vma->private); 1024 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); 1025 } 1026 1027 intel_ring_unpin(engine->legacy.ring); 1028 intel_ring_put(engine->legacy.ring); 1029 1030 intel_timeline_unpin(engine->legacy.timeline); 1031 intel_timeline_put(engine->legacy.timeline); 1032 } 1033 1034 static void setup_irq(struct intel_engine_cs *engine) 1035 { 1036 struct drm_i915_private *i915 = engine->i915; 1037 1038 if (INTEL_GEN(i915) >= 6) { 1039 engine->irq_enable = gen6_irq_enable; 1040 engine->irq_disable = gen6_irq_disable; 1041 } else if (INTEL_GEN(i915) >= 5) { 1042 engine->irq_enable = gen5_irq_enable; 1043 engine->irq_disable = gen5_irq_disable; 1044 } else if (INTEL_GEN(i915) >= 3) { 1045 engine->irq_enable = gen3_irq_enable; 1046 engine->irq_disable = gen3_irq_disable; 1047 } else { 1048 engine->irq_enable = gen2_irq_enable; 1049 engine->irq_disable = gen2_irq_disable; 1050 } 1051 } 1052 1053 static void setup_common(struct intel_engine_cs *engine) 1054 { 1055 struct drm_i915_private *i915 = engine->i915; 1056 1057 /* gen8+ are only supported with execlists */ 1058 GEM_BUG_ON(INTEL_GEN(i915) >= 8); 1059 1060 setup_irq(engine); 1061 1062 engine->resume = xcs_resume; 1063 engine->reset.prepare = reset_prepare; 1064 engine->reset.rewind = reset_rewind; 1065 engine->reset.cancel = reset_cancel; 1066 engine->reset.finish = reset_finish; 1067 1068 engine->cops = &ring_context_ops; 1069 engine->request_alloc = ring_request_alloc; 1070 1071 /* 1072 * Using a global execution timeline; the previous final breadcrumb is 1073 * equivalent to our next initial bread so we can elide 1074 * engine->emit_init_breadcrumb(). 1075 */ 1076 engine->emit_fini_breadcrumb = gen3_emit_breadcrumb; 1077 if (IS_GEN(i915, 5)) 1078 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; 1079 1080 engine->set_default_submission = i9xx_set_default_submission; 1081 1082 if (INTEL_GEN(i915) >= 6) 1083 engine->emit_bb_start = gen6_emit_bb_start; 1084 else if (INTEL_GEN(i915) >= 4) 1085 engine->emit_bb_start = gen4_emit_bb_start; 1086 else if (IS_I830(i915) || IS_I845G(i915)) 1087 engine->emit_bb_start = i830_emit_bb_start; 1088 else 1089 engine->emit_bb_start = gen3_emit_bb_start; 1090 } 1091 1092 static void setup_rcs(struct intel_engine_cs *engine) 1093 { 1094 struct drm_i915_private *i915 = engine->i915; 1095 1096 if (HAS_L3_DPF(i915)) 1097 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; 1098 1099 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; 1100 1101 if (INTEL_GEN(i915) >= 7) { 1102 engine->emit_flush = gen7_emit_flush_rcs; 1103 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs; 1104 } else if (IS_GEN(i915, 6)) { 1105 engine->emit_flush = gen6_emit_flush_rcs; 1106 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs; 1107 } else if (IS_GEN(i915, 5)) { 1108 engine->emit_flush = gen4_emit_flush_rcs; 1109 } else { 1110 if (INTEL_GEN(i915) < 4) 1111 engine->emit_flush = gen2_emit_flush; 1112 else 1113 engine->emit_flush = gen4_emit_flush_rcs; 1114 engine->irq_enable_mask = I915_USER_INTERRUPT; 1115 } 1116 1117 if (IS_HASWELL(i915)) 1118 engine->emit_bb_start = hsw_emit_bb_start; 1119 } 1120 1121 static void setup_vcs(struct intel_engine_cs *engine) 1122 { 1123 struct drm_i915_private *i915 = engine->i915; 1124 1125 if (INTEL_GEN(i915) >= 6) { 1126 /* gen6 bsd needs a special wa for tail updates */ 1127 if (IS_GEN(i915, 6)) 1128 engine->set_default_submission = gen6_bsd_set_default_submission; 1129 engine->emit_flush = gen6_emit_flush_vcs; 1130 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; 1131 1132 if (IS_GEN(i915, 6)) 1133 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; 1134 else 1135 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; 1136 } else { 1137 engine->emit_flush = gen4_emit_flush_vcs; 1138 if (IS_GEN(i915, 5)) 1139 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; 1140 else 1141 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; 1142 } 1143 } 1144 1145 static void setup_bcs(struct intel_engine_cs *engine) 1146 { 1147 struct drm_i915_private *i915 = engine->i915; 1148 1149 engine->emit_flush = gen6_emit_flush_xcs; 1150 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; 1151 1152 if (IS_GEN(i915, 6)) 1153 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; 1154 else 1155 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; 1156 } 1157 1158 static void setup_vecs(struct intel_engine_cs *engine) 1159 { 1160 struct drm_i915_private *i915 = engine->i915; 1161 1162 GEM_BUG_ON(INTEL_GEN(i915) < 7); 1163 1164 engine->emit_flush = gen6_emit_flush_xcs; 1165 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; 1166 engine->irq_enable = hsw_irq_enable_vecs; 1167 engine->irq_disable = hsw_irq_disable_vecs; 1168 1169 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; 1170 } 1171 1172 static int gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine, 1173 struct i915_vma * const vma) 1174 { 1175 return gen7_setup_clear_gpr_bb(engine, vma); 1176 } 1177 1178 static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine) 1179 { 1180 struct drm_i915_gem_object *obj; 1181 struct i915_vma *vma; 1182 int size; 1183 int err; 1184 1185 size = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */); 1186 if (size <= 0) 1187 return size; 1188 1189 size = ALIGN(size, PAGE_SIZE); 1190 obj = i915_gem_object_create_internal(engine->i915, size); 1191 if (IS_ERR(obj)) 1192 return PTR_ERR(obj); 1193 1194 vma = i915_vma_instance(obj, engine->gt->vm, NULL); 1195 if (IS_ERR(vma)) { 1196 err = PTR_ERR(vma); 1197 goto err_obj; 1198 } 1199 1200 vma->private = intel_context_create(engine); /* dummy residuals */ 1201 if (IS_ERR(vma->private)) { 1202 err = PTR_ERR(vma->private); 1203 goto err_obj; 1204 } 1205 1206 err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH); 1207 if (err) 1208 goto err_private; 1209 1210 err = i915_vma_sync(vma); 1211 if (err) 1212 goto err_unpin; 1213 1214 err = gen7_ctx_switch_bb_setup(engine, vma); 1215 if (err) 1216 goto err_unpin; 1217 1218 engine->wa_ctx.vma = vma; 1219 return 0; 1220 1221 err_unpin: 1222 i915_vma_unpin(vma); 1223 err_private: 1224 intel_context_put(vma->private); 1225 err_obj: 1226 i915_gem_object_put(obj); 1227 return err; 1228 } 1229 1230 int intel_ring_submission_setup(struct intel_engine_cs *engine) 1231 { 1232 struct intel_timeline *timeline; 1233 struct intel_ring *ring; 1234 int err; 1235 1236 setup_common(engine); 1237 1238 switch (engine->class) { 1239 case RENDER_CLASS: 1240 setup_rcs(engine); 1241 break; 1242 case VIDEO_DECODE_CLASS: 1243 setup_vcs(engine); 1244 break; 1245 case COPY_ENGINE_CLASS: 1246 setup_bcs(engine); 1247 break; 1248 case VIDEO_ENHANCEMENT_CLASS: 1249 setup_vecs(engine); 1250 break; 1251 default: 1252 MISSING_CASE(engine->class); 1253 return -ENODEV; 1254 } 1255 1256 timeline = intel_timeline_create_from_engine(engine, 1257 I915_GEM_HWS_SEQNO_ADDR); 1258 if (IS_ERR(timeline)) { 1259 err = PTR_ERR(timeline); 1260 goto err; 1261 } 1262 GEM_BUG_ON(timeline->has_initial_breadcrumb); 1263 1264 err = intel_timeline_pin(timeline); 1265 if (err) 1266 goto err_timeline; 1267 1268 ring = intel_engine_create_ring(engine, SZ_16K); 1269 if (IS_ERR(ring)) { 1270 err = PTR_ERR(ring); 1271 goto err_timeline_unpin; 1272 } 1273 1274 err = intel_ring_pin(ring); 1275 if (err) 1276 goto err_ring; 1277 1278 GEM_BUG_ON(engine->legacy.ring); 1279 engine->legacy.ring = ring; 1280 engine->legacy.timeline = timeline; 1281 1282 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma); 1283 1284 if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) { 1285 err = gen7_ctx_switch_bb_init(engine); 1286 if (err) 1287 goto err_ring_unpin; 1288 } 1289 1290 /* Finally, take ownership and responsibility for cleanup! */ 1291 engine->release = ring_release; 1292 1293 return 0; 1294 1295 err_ring_unpin: 1296 intel_ring_unpin(ring); 1297 err_ring: 1298 intel_ring_put(ring); 1299 err_timeline_unpin: 1300 intel_timeline_unpin(timeline); 1301 err_timeline: 1302 intel_timeline_put(timeline); 1303 err: 1304 intel_engine_cleanup_common(engine); 1305 return err; 1306 } 1307 1308 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1309 #include "selftest_ring_submission.c" 1310 #endif 1311