1 /* 2 * Copyright © 2008-2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Zou Nan hai <nanhai.zou@intel.com> 26 * Xiang Hai hao<haihao.xiang@intel.com> 27 * 28 */ 29 30 #include "gen2_engine_cs.h" 31 #include "gen6_engine_cs.h" 32 #include "gen6_ppgtt.h" 33 #include "gen7_renderclear.h" 34 #include "i915_drv.h" 35 #include "i915_mitigations.h" 36 #include "intel_breadcrumbs.h" 37 #include "intel_context.h" 38 #include "intel_gt.h" 39 #include "intel_reset.h" 40 #include "intel_ring.h" 41 #include "shmem_utils.h" 42 43 /* Rough estimate of the typical request size, performing a flush, 44 * set-context and then emitting the batch. 45 */ 46 #define LEGACY_REQUEST_SIZE 200 47 48 static void set_hwstam(struct intel_engine_cs *engine, u32 mask) 49 { 50 /* 51 * Keep the render interrupt unmasked as this papers over 52 * lost interrupts following a reset. 53 */ 54 if (engine->class == RENDER_CLASS) { 55 if (INTEL_GEN(engine->i915) >= 6) 56 mask &= ~BIT(0); 57 else 58 mask &= ~I915_USER_INTERRUPT; 59 } 60 61 intel_engine_set_hwsp_writemask(engine, mask); 62 } 63 64 static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys) 65 { 66 u32 addr; 67 68 addr = lower_32_bits(phys); 69 if (INTEL_GEN(engine->i915) >= 4) 70 addr |= (phys >> 28) & 0xf0; 71 72 intel_uncore_write(engine->uncore, HWS_PGA, addr); 73 } 74 75 static struct page *status_page(struct intel_engine_cs *engine) 76 { 77 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; 78 79 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); 80 return sg_page(obj->mm.pages->sgl); 81 } 82 83 static void ring_setup_phys_status_page(struct intel_engine_cs *engine) 84 { 85 set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine)))); 86 set_hwstam(engine, ~0u); 87 } 88 89 static void set_hwsp(struct intel_engine_cs *engine, u32 offset) 90 { 91 i915_reg_t hwsp; 92 93 /* 94 * The ring status page addresses are no longer next to the rest of 95 * the ring registers as of gen7. 96 */ 97 if (IS_GEN(engine->i915, 7)) { 98 switch (engine->id) { 99 /* 100 * No more rings exist on Gen7. Default case is only to shut up 101 * gcc switch check warning. 102 */ 103 default: 104 GEM_BUG_ON(engine->id); 105 fallthrough; 106 case RCS0: 107 hwsp = RENDER_HWS_PGA_GEN7; 108 break; 109 case BCS0: 110 hwsp = BLT_HWS_PGA_GEN7; 111 break; 112 case VCS0: 113 hwsp = BSD_HWS_PGA_GEN7; 114 break; 115 case VECS0: 116 hwsp = VEBOX_HWS_PGA_GEN7; 117 break; 118 } 119 } else if (IS_GEN(engine->i915, 6)) { 120 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); 121 } else { 122 hwsp = RING_HWS_PGA(engine->mmio_base); 123 } 124 125 intel_uncore_write(engine->uncore, hwsp, offset); 126 intel_uncore_posting_read(engine->uncore, hwsp); 127 } 128 129 static void flush_cs_tlb(struct intel_engine_cs *engine) 130 { 131 struct drm_i915_private *dev_priv = engine->i915; 132 133 if (!IS_GEN_RANGE(dev_priv, 6, 7)) 134 return; 135 136 /* ring should be idle before issuing a sync flush*/ 137 drm_WARN_ON(&dev_priv->drm, 138 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); 139 140 ENGINE_WRITE(engine, RING_INSTPM, 141 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | 142 INSTPM_SYNC_FLUSH)); 143 if (intel_wait_for_register(engine->uncore, 144 RING_INSTPM(engine->mmio_base), 145 INSTPM_SYNC_FLUSH, 0, 146 1000)) 147 drm_err(&dev_priv->drm, 148 "%s: wait for SyncFlush to complete for TLB invalidation timed out\n", 149 engine->name); 150 } 151 152 static void ring_setup_status_page(struct intel_engine_cs *engine) 153 { 154 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); 155 set_hwstam(engine, ~0u); 156 157 flush_cs_tlb(engine); 158 } 159 160 static bool stop_ring(struct intel_engine_cs *engine) 161 { 162 struct drm_i915_private *dev_priv = engine->i915; 163 164 if (INTEL_GEN(dev_priv) > 2) { 165 ENGINE_WRITE(engine, 166 RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING)); 167 if (intel_wait_for_register(engine->uncore, 168 RING_MI_MODE(engine->mmio_base), 169 MODE_IDLE, 170 MODE_IDLE, 171 1000)) { 172 drm_err(&dev_priv->drm, 173 "%s : timed out trying to stop ring\n", 174 engine->name); 175 176 /* 177 * Sometimes we observe that the idle flag is not 178 * set even though the ring is empty. So double 179 * check before giving up. 180 */ 181 if (ENGINE_READ(engine, RING_HEAD) != 182 ENGINE_READ(engine, RING_TAIL)) 183 return false; 184 } 185 } 186 187 ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL)); 188 189 ENGINE_WRITE(engine, RING_HEAD, 0); 190 ENGINE_WRITE(engine, RING_TAIL, 0); 191 192 /* The ring must be empty before it is disabled */ 193 ENGINE_WRITE(engine, RING_CTL, 0); 194 195 return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0; 196 } 197 198 static struct i915_address_space *vm_alias(struct i915_address_space *vm) 199 { 200 if (i915_is_ggtt(vm)) 201 vm = &i915_vm_to_ggtt(vm)->alias->vm; 202 203 return vm; 204 } 205 206 static u32 pp_dir(struct i915_address_space *vm) 207 { 208 return to_gen6_ppgtt(i915_vm_to_ppgtt(vm))->pp_dir; 209 } 210 211 static void set_pp_dir(struct intel_engine_cs *engine) 212 { 213 struct i915_address_space *vm = vm_alias(engine->gt->vm); 214 215 if (vm) { 216 ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G); 217 ENGINE_WRITE(engine, RING_PP_DIR_BASE, pp_dir(vm)); 218 } 219 } 220 221 static int xcs_resume(struct intel_engine_cs *engine) 222 { 223 struct drm_i915_private *dev_priv = engine->i915; 224 struct intel_ring *ring = engine->legacy.ring; 225 int ret = 0; 226 227 ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n", 228 ring->head, ring->tail); 229 230 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); 231 232 /* WaClearRingBufHeadRegAtInit:ctg,elk */ 233 if (!stop_ring(engine)) { 234 /* G45 ring initialization often fails to reset head to zero */ 235 drm_dbg(&dev_priv->drm, "%s head not reset to zero " 236 "ctl %08x head %08x tail %08x start %08x\n", 237 engine->name, 238 ENGINE_READ(engine, RING_CTL), 239 ENGINE_READ(engine, RING_HEAD), 240 ENGINE_READ(engine, RING_TAIL), 241 ENGINE_READ(engine, RING_START)); 242 243 if (!stop_ring(engine)) { 244 drm_err(&dev_priv->drm, 245 "failed to set %s head to zero " 246 "ctl %08x head %08x tail %08x start %08x\n", 247 engine->name, 248 ENGINE_READ(engine, RING_CTL), 249 ENGINE_READ(engine, RING_HEAD), 250 ENGINE_READ(engine, RING_TAIL), 251 ENGINE_READ(engine, RING_START)); 252 ret = -EIO; 253 goto out; 254 } 255 } 256 257 if (HWS_NEEDS_PHYSICAL(dev_priv)) 258 ring_setup_phys_status_page(engine); 259 else 260 ring_setup_status_page(engine); 261 262 intel_breadcrumbs_reset(engine->breadcrumbs); 263 264 /* Enforce ordering by reading HEAD register back */ 265 ENGINE_POSTING_READ(engine, RING_HEAD); 266 267 /* 268 * Initialize the ring. This must happen _after_ we've cleared the ring 269 * registers with the above sequence (the readback of the HEAD registers 270 * also enforces ordering), otherwise the hw might lose the new ring 271 * register values. 272 */ 273 ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma)); 274 275 /* Check that the ring offsets point within the ring! */ 276 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); 277 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); 278 intel_ring_update_space(ring); 279 280 set_pp_dir(engine); 281 282 /* First wake the ring up to an empty/idle ring */ 283 ENGINE_WRITE(engine, RING_HEAD, ring->head); 284 ENGINE_WRITE(engine, RING_TAIL, ring->head); 285 ENGINE_POSTING_READ(engine, RING_TAIL); 286 287 ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID); 288 289 /* If the head is still not zero, the ring is dead */ 290 if (intel_wait_for_register(engine->uncore, 291 RING_CTL(engine->mmio_base), 292 RING_VALID, RING_VALID, 293 50)) { 294 drm_err(&dev_priv->drm, "%s initialization failed " 295 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", 296 engine->name, 297 ENGINE_READ(engine, RING_CTL), 298 ENGINE_READ(engine, RING_CTL) & RING_VALID, 299 ENGINE_READ(engine, RING_HEAD), ring->head, 300 ENGINE_READ(engine, RING_TAIL), ring->tail, 301 ENGINE_READ(engine, RING_START), 302 i915_ggtt_offset(ring->vma)); 303 ret = -EIO; 304 goto out; 305 } 306 307 if (INTEL_GEN(dev_priv) > 2) 308 ENGINE_WRITE(engine, 309 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 310 311 /* Now awake, let it get started */ 312 if (ring->tail != ring->head) { 313 ENGINE_WRITE(engine, RING_TAIL, ring->tail); 314 ENGINE_POSTING_READ(engine, RING_TAIL); 315 } 316 317 /* Papering over lost _interrupts_ immediately following the restart */ 318 intel_engine_signal_breadcrumbs(engine); 319 out: 320 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); 321 322 return ret; 323 } 324 325 static void reset_prepare(struct intel_engine_cs *engine) 326 { 327 struct intel_uncore *uncore = engine->uncore; 328 const u32 base = engine->mmio_base; 329 330 /* 331 * We stop engines, otherwise we might get failed reset and a 332 * dead gpu (on elk). Also as modern gpu as kbl can suffer 333 * from system hang if batchbuffer is progressing when 334 * the reset is issued, regardless of READY_TO_RESET ack. 335 * Thus assume it is best to stop engines on all gens 336 * where we have a gpu reset. 337 * 338 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES) 339 * 340 * WaMediaResetMainRingCleanup:ctg,elk (presumably) 341 * 342 * FIXME: Wa for more modern gens needs to be validated 343 */ 344 ENGINE_TRACE(engine, "\n"); 345 346 if (intel_engine_stop_cs(engine)) 347 ENGINE_TRACE(engine, "timed out on STOP_RING\n"); 348 349 intel_uncore_write_fw(uncore, 350 RING_HEAD(base), 351 intel_uncore_read_fw(uncore, RING_TAIL(base))); 352 intel_uncore_posting_read_fw(uncore, RING_HEAD(base)); /* paranoia */ 353 354 intel_uncore_write_fw(uncore, RING_HEAD(base), 0); 355 intel_uncore_write_fw(uncore, RING_TAIL(base), 0); 356 intel_uncore_posting_read_fw(uncore, RING_TAIL(base)); 357 358 /* The ring must be empty before it is disabled */ 359 intel_uncore_write_fw(uncore, RING_CTL(base), 0); 360 361 /* Check acts as a post */ 362 if (intel_uncore_read_fw(uncore, RING_HEAD(base))) 363 ENGINE_TRACE(engine, "ring head [%x] not parked\n", 364 intel_uncore_read_fw(uncore, RING_HEAD(base))); 365 } 366 367 static void reset_rewind(struct intel_engine_cs *engine, bool stalled) 368 { 369 struct i915_request *pos, *rq; 370 unsigned long flags; 371 u32 head; 372 373 rq = NULL; 374 spin_lock_irqsave(&engine->active.lock, flags); 375 list_for_each_entry(pos, &engine->active.requests, sched.link) { 376 if (!i915_request_completed(pos)) { 377 rq = pos; 378 break; 379 } 380 } 381 382 /* 383 * The guilty request will get skipped on a hung engine. 384 * 385 * Users of client default contexts do not rely on logical 386 * state preserved between batches so it is safe to execute 387 * queued requests following the hang. Non default contexts 388 * rely on preserved state, so skipping a batch loses the 389 * evolution of the state and it needs to be considered corrupted. 390 * Executing more queued batches on top of corrupted state is 391 * risky. But we take the risk by trying to advance through 392 * the queued requests in order to make the client behaviour 393 * more predictable around resets, by not throwing away random 394 * amount of batches it has prepared for execution. Sophisticated 395 * clients can use gem_reset_stats_ioctl and dma fence status 396 * (exported via sync_file info ioctl on explicit fences) to observe 397 * when it loses the context state and should rebuild accordingly. 398 * 399 * The context ban, and ultimately the client ban, mechanism are safety 400 * valves if client submission ends up resulting in nothing more than 401 * subsequent hangs. 402 */ 403 404 if (rq) { 405 /* 406 * Try to restore the logical GPU state to match the 407 * continuation of the request queue. If we skip the 408 * context/PD restore, then the next request may try to execute 409 * assuming that its context is valid and loaded on the GPU and 410 * so may try to access invalid memory, prompting repeated GPU 411 * hangs. 412 * 413 * If the request was guilty, we still restore the logical 414 * state in case the next request requires it (e.g. the 415 * aliasing ppgtt), but skip over the hung batch. 416 * 417 * If the request was innocent, we try to replay the request 418 * with the restored context. 419 */ 420 __i915_request_reset(rq, stalled); 421 422 GEM_BUG_ON(rq->ring != engine->legacy.ring); 423 head = rq->head; 424 } else { 425 head = engine->legacy.ring->tail; 426 } 427 engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head); 428 429 spin_unlock_irqrestore(&engine->active.lock, flags); 430 } 431 432 static void reset_finish(struct intel_engine_cs *engine) 433 { 434 } 435 436 static void reset_cancel(struct intel_engine_cs *engine) 437 { 438 struct i915_request *request; 439 unsigned long flags; 440 441 spin_lock_irqsave(&engine->active.lock, flags); 442 443 /* Mark all submitted requests as skipped. */ 444 list_for_each_entry(request, &engine->active.requests, sched.link) { 445 i915_request_set_error_once(request, -EIO); 446 i915_request_mark_complete(request); 447 } 448 intel_engine_signal_breadcrumbs(engine); 449 450 /* Remaining _unready_ requests will be nop'ed when submitted */ 451 452 spin_unlock_irqrestore(&engine->active.lock, flags); 453 } 454 455 static void i9xx_submit_request(struct i915_request *request) 456 { 457 i915_request_submit(request); 458 wmb(); /* paranoid flush writes out of the WCB before mmio */ 459 460 ENGINE_WRITE(request->engine, RING_TAIL, 461 intel_ring_set_tail(request->ring, request->tail)); 462 } 463 464 static void __ring_context_fini(struct intel_context *ce) 465 { 466 i915_vma_put(ce->state); 467 } 468 469 static void ring_context_destroy(struct kref *ref) 470 { 471 struct intel_context *ce = container_of(ref, typeof(*ce), ref); 472 473 GEM_BUG_ON(intel_context_is_pinned(ce)); 474 475 if (ce->state) 476 __ring_context_fini(ce); 477 478 intel_context_fini(ce); 479 intel_context_free(ce); 480 } 481 482 static int ring_context_pre_pin(struct intel_context *ce, 483 struct i915_gem_ww_ctx *ww, 484 void **unused) 485 { 486 struct i915_address_space *vm; 487 int err = 0; 488 489 vm = vm_alias(ce->vm); 490 if (vm) 491 err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)), ww); 492 493 return err; 494 } 495 496 static void __context_unpin_ppgtt(struct intel_context *ce) 497 { 498 struct i915_address_space *vm; 499 500 vm = vm_alias(ce->vm); 501 if (vm) 502 gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm)); 503 } 504 505 static void ring_context_unpin(struct intel_context *ce) 506 { 507 } 508 509 static void ring_context_post_unpin(struct intel_context *ce) 510 { 511 __context_unpin_ppgtt(ce); 512 } 513 514 static struct i915_vma * 515 alloc_context_vma(struct intel_engine_cs *engine) 516 { 517 struct drm_i915_private *i915 = engine->i915; 518 struct drm_i915_gem_object *obj; 519 struct i915_vma *vma; 520 int err; 521 522 obj = i915_gem_object_create_shmem(i915, engine->context_size); 523 if (IS_ERR(obj)) 524 return ERR_CAST(obj); 525 526 /* 527 * Try to make the context utilize L3 as well as LLC. 528 * 529 * On VLV we don't have L3 controls in the PTEs so we 530 * shouldn't touch the cache level, especially as that 531 * would make the object snooped which might have a 532 * negative performance impact. 533 * 534 * Snooping is required on non-llc platforms in execlist 535 * mode, but since all GGTT accesses use PAT entry 0 we 536 * get snooping anyway regardless of cache_level. 537 * 538 * This is only applicable for Ivy Bridge devices since 539 * later platforms don't have L3 control bits in the PTE. 540 */ 541 if (IS_IVYBRIDGE(i915)) 542 i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC); 543 544 if (engine->default_state) { 545 void *vaddr; 546 547 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 548 if (IS_ERR(vaddr)) { 549 err = PTR_ERR(vaddr); 550 goto err_obj; 551 } 552 553 shmem_read(engine->default_state, 0, 554 vaddr, engine->context_size); 555 556 i915_gem_object_flush_map(obj); 557 __i915_gem_object_release_map(obj); 558 } 559 560 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 561 if (IS_ERR(vma)) { 562 err = PTR_ERR(vma); 563 goto err_obj; 564 } 565 566 return vma; 567 568 err_obj: 569 i915_gem_object_put(obj); 570 return ERR_PTR(err); 571 } 572 573 static int ring_context_alloc(struct intel_context *ce) 574 { 575 struct intel_engine_cs *engine = ce->engine; 576 577 /* One ringbuffer to rule them all */ 578 GEM_BUG_ON(!engine->legacy.ring); 579 ce->ring = engine->legacy.ring; 580 ce->timeline = intel_timeline_get(engine->legacy.timeline); 581 582 GEM_BUG_ON(ce->state); 583 if (engine->context_size) { 584 struct i915_vma *vma; 585 586 vma = alloc_context_vma(engine); 587 if (IS_ERR(vma)) 588 return PTR_ERR(vma); 589 590 ce->state = vma; 591 if (engine->default_state) 592 __set_bit(CONTEXT_VALID_BIT, &ce->flags); 593 } 594 595 return 0; 596 } 597 598 static int ring_context_pin(struct intel_context *ce, void *unused) 599 { 600 return 0; 601 } 602 603 static void ring_context_reset(struct intel_context *ce) 604 { 605 intel_ring_reset(ce->ring, ce->ring->emit); 606 } 607 608 static const struct intel_context_ops ring_context_ops = { 609 .alloc = ring_context_alloc, 610 611 .pre_pin = ring_context_pre_pin, 612 .pin = ring_context_pin, 613 .unpin = ring_context_unpin, 614 .post_unpin = ring_context_post_unpin, 615 616 .enter = intel_context_enter_engine, 617 .exit = intel_context_exit_engine, 618 619 .reset = ring_context_reset, 620 .destroy = ring_context_destroy, 621 }; 622 623 static int load_pd_dir(struct i915_request *rq, 624 struct i915_address_space *vm, 625 u32 valid) 626 { 627 const struct intel_engine_cs * const engine = rq->engine; 628 u32 *cs; 629 630 cs = intel_ring_begin(rq, 12); 631 if (IS_ERR(cs)) 632 return PTR_ERR(cs); 633 634 *cs++ = MI_LOAD_REGISTER_IMM(1); 635 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); 636 *cs++ = valid; 637 638 *cs++ = MI_LOAD_REGISTER_IMM(1); 639 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); 640 *cs++ = pp_dir(vm); 641 642 /* Stall until the page table load is complete? */ 643 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 644 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); 645 *cs++ = intel_gt_scratch_offset(engine->gt, 646 INTEL_GT_SCRATCH_FIELD_DEFAULT); 647 648 *cs++ = MI_LOAD_REGISTER_IMM(1); 649 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); 650 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); 651 652 intel_ring_advance(rq, cs); 653 654 return rq->engine->emit_flush(rq, EMIT_FLUSH); 655 } 656 657 static inline int mi_set_context(struct i915_request *rq, 658 struct intel_context *ce, 659 u32 flags) 660 { 661 struct intel_engine_cs *engine = rq->engine; 662 struct drm_i915_private *i915 = engine->i915; 663 enum intel_engine_id id; 664 const int num_engines = 665 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; 666 bool force_restore = false; 667 int len; 668 u32 *cs; 669 670 len = 4; 671 if (IS_GEN(i915, 7)) 672 len += 2 + (num_engines ? 4 * num_engines + 6 : 0); 673 else if (IS_GEN(i915, 5)) 674 len += 2; 675 if (flags & MI_FORCE_RESTORE) { 676 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); 677 flags &= ~MI_FORCE_RESTORE; 678 force_restore = true; 679 len += 2; 680 } 681 682 cs = intel_ring_begin(rq, len); 683 if (IS_ERR(cs)) 684 return PTR_ERR(cs); 685 686 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ 687 if (IS_GEN(i915, 7)) { 688 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 689 if (num_engines) { 690 struct intel_engine_cs *signaller; 691 692 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); 693 for_each_engine(signaller, engine->gt, id) { 694 if (signaller == engine) 695 continue; 696 697 *cs++ = i915_mmio_reg_offset( 698 RING_PSMI_CTL(signaller->mmio_base)); 699 *cs++ = _MASKED_BIT_ENABLE( 700 GEN6_PSMI_SLEEP_MSG_DISABLE); 701 } 702 } 703 } else if (IS_GEN(i915, 5)) { 704 /* 705 * This w/a is only listed for pre-production ilk a/b steppings, 706 * but is also mentioned for programming the powerctx. To be 707 * safe, just apply the workaround; we do not use SyncFlush so 708 * this should never take effect and so be a no-op! 709 */ 710 *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN; 711 } 712 713 if (force_restore) { 714 /* 715 * The HW doesn't handle being told to restore the current 716 * context very well. Quite often it likes goes to go off and 717 * sulk, especially when it is meant to be reloading PP_DIR. 718 * A very simple fix to force the reload is to simply switch 719 * away from the current context and back again. 720 * 721 * Note that the kernel_context will contain random state 722 * following the INHIBIT_RESTORE. We accept this since we 723 * never use the kernel_context state; it is merely a 724 * placeholder we use to flush other contexts. 725 */ 726 *cs++ = MI_SET_CONTEXT; 727 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | 728 MI_MM_SPACE_GTT | 729 MI_RESTORE_INHIBIT; 730 } 731 732 *cs++ = MI_NOOP; 733 *cs++ = MI_SET_CONTEXT; 734 *cs++ = i915_ggtt_offset(ce->state) | flags; 735 /* 736 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP 737 * WaMiSetContext_Hang:snb,ivb,vlv 738 */ 739 *cs++ = MI_NOOP; 740 741 if (IS_GEN(i915, 7)) { 742 if (num_engines) { 743 struct intel_engine_cs *signaller; 744 i915_reg_t last_reg = {}; /* keep gcc quiet */ 745 746 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); 747 for_each_engine(signaller, engine->gt, id) { 748 if (signaller == engine) 749 continue; 750 751 last_reg = RING_PSMI_CTL(signaller->mmio_base); 752 *cs++ = i915_mmio_reg_offset(last_reg); 753 *cs++ = _MASKED_BIT_DISABLE( 754 GEN6_PSMI_SLEEP_MSG_DISABLE); 755 } 756 757 /* Insert a delay before the next switch! */ 758 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 759 *cs++ = i915_mmio_reg_offset(last_reg); 760 *cs++ = intel_gt_scratch_offset(engine->gt, 761 INTEL_GT_SCRATCH_FIELD_DEFAULT); 762 *cs++ = MI_NOOP; 763 } 764 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 765 } else if (IS_GEN(i915, 5)) { 766 *cs++ = MI_SUSPEND_FLUSH; 767 } 768 769 intel_ring_advance(rq, cs); 770 771 return 0; 772 } 773 774 static int remap_l3_slice(struct i915_request *rq, int slice) 775 { 776 u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice]; 777 int i; 778 779 if (!remap_info) 780 return 0; 781 782 cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2); 783 if (IS_ERR(cs)) 784 return PTR_ERR(cs); 785 786 /* 787 * Note: We do not worry about the concurrent register cacheline hang 788 * here because no other code should access these registers other than 789 * at initialization time. 790 */ 791 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); 792 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { 793 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); 794 *cs++ = remap_info[i]; 795 } 796 *cs++ = MI_NOOP; 797 intel_ring_advance(rq, cs); 798 799 return 0; 800 } 801 802 static int remap_l3(struct i915_request *rq) 803 { 804 struct i915_gem_context *ctx = i915_request_gem_context(rq); 805 int i, err; 806 807 if (!ctx || !ctx->remap_slice) 808 return 0; 809 810 for (i = 0; i < MAX_L3_SLICES; i++) { 811 if (!(ctx->remap_slice & BIT(i))) 812 continue; 813 814 err = remap_l3_slice(rq, i); 815 if (err) 816 return err; 817 } 818 819 ctx->remap_slice = 0; 820 return 0; 821 } 822 823 static int switch_mm(struct i915_request *rq, struct i915_address_space *vm) 824 { 825 int ret; 826 827 if (!vm) 828 return 0; 829 830 ret = rq->engine->emit_flush(rq, EMIT_FLUSH); 831 if (ret) 832 return ret; 833 834 /* 835 * Not only do we need a full barrier (post-sync write) after 836 * invalidating the TLBs, but we need to wait a little bit 837 * longer. Whether this is merely delaying us, or the 838 * subsequent flush is a key part of serialising with the 839 * post-sync op, this extra pass appears vital before a 840 * mm switch! 841 */ 842 ret = load_pd_dir(rq, vm, PP_DIR_DCLV_2G); 843 if (ret) 844 return ret; 845 846 return rq->engine->emit_flush(rq, EMIT_INVALIDATE); 847 } 848 849 static int clear_residuals(struct i915_request *rq) 850 { 851 struct intel_engine_cs *engine = rq->engine; 852 int ret; 853 854 ret = switch_mm(rq, vm_alias(engine->kernel_context->vm)); 855 if (ret) 856 return ret; 857 858 if (engine->kernel_context->state) { 859 ret = mi_set_context(rq, 860 engine->kernel_context, 861 MI_MM_SPACE_GTT | MI_RESTORE_INHIBIT); 862 if (ret) 863 return ret; 864 } 865 866 ret = engine->emit_bb_start(rq, 867 engine->wa_ctx.vma->node.start, 0, 868 0); 869 if (ret) 870 return ret; 871 872 ret = engine->emit_flush(rq, EMIT_FLUSH); 873 if (ret) 874 return ret; 875 876 /* Always invalidate before the next switch_mm() */ 877 return engine->emit_flush(rq, EMIT_INVALIDATE); 878 } 879 880 static int switch_context(struct i915_request *rq) 881 { 882 struct intel_engine_cs *engine = rq->engine; 883 struct intel_context *ce = rq->context; 884 void **residuals = NULL; 885 int ret; 886 887 GEM_BUG_ON(HAS_EXECLISTS(engine->i915)); 888 889 if (engine->wa_ctx.vma && ce != engine->kernel_context) { 890 if (engine->wa_ctx.vma->private != ce && 891 i915_mitigate_clear_residuals()) { 892 ret = clear_residuals(rq); 893 if (ret) 894 return ret; 895 896 residuals = &engine->wa_ctx.vma->private; 897 } 898 } 899 900 ret = switch_mm(rq, vm_alias(ce->vm)); 901 if (ret) 902 return ret; 903 904 if (ce->state) { 905 u32 flags; 906 907 GEM_BUG_ON(engine->id != RCS0); 908 909 /* For resource streamer on HSW+ and power context elsewhere */ 910 BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN != MI_SAVE_EXT_STATE_EN); 911 BUILD_BUG_ON(HSW_MI_RS_RESTORE_STATE_EN != MI_RESTORE_EXT_STATE_EN); 912 913 flags = MI_SAVE_EXT_STATE_EN | MI_MM_SPACE_GTT; 914 if (test_bit(CONTEXT_VALID_BIT, &ce->flags)) 915 flags |= MI_RESTORE_EXT_STATE_EN; 916 else 917 flags |= MI_RESTORE_INHIBIT; 918 919 ret = mi_set_context(rq, ce, flags); 920 if (ret) 921 return ret; 922 } 923 924 ret = remap_l3(rq); 925 if (ret) 926 return ret; 927 928 /* 929 * Now past the point of no return, this request _will_ be emitted. 930 * 931 * Or at least this preamble will be emitted, the request may be 932 * interrupted prior to submitting the user payload. If so, we 933 * still submit the "empty" request in order to preserve global 934 * state tracking such as this, our tracking of the current 935 * dirty context. 936 */ 937 if (residuals) { 938 intel_context_put(*residuals); 939 *residuals = intel_context_get(ce); 940 } 941 942 return 0; 943 } 944 945 static int ring_request_alloc(struct i915_request *request) 946 { 947 int ret; 948 949 GEM_BUG_ON(!intel_context_is_pinned(request->context)); 950 GEM_BUG_ON(i915_request_timeline(request)->has_initial_breadcrumb); 951 952 /* 953 * Flush enough space to reduce the likelihood of waiting after 954 * we start building the request - in which case we will just 955 * have to repeat work. 956 */ 957 request->reserved_space += LEGACY_REQUEST_SIZE; 958 959 /* Unconditionally invalidate GPU caches and TLBs. */ 960 ret = request->engine->emit_flush(request, EMIT_INVALIDATE); 961 if (ret) 962 return ret; 963 964 ret = switch_context(request); 965 if (ret) 966 return ret; 967 968 request->reserved_space -= LEGACY_REQUEST_SIZE; 969 return 0; 970 } 971 972 static void gen6_bsd_submit_request(struct i915_request *request) 973 { 974 struct intel_uncore *uncore = request->engine->uncore; 975 976 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 977 978 /* Every tail move must follow the sequence below */ 979 980 /* Disable notification that the ring is IDLE. The GT 981 * will then assume that it is busy and bring it out of rc6. 982 */ 983 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL, 984 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); 985 986 /* Clear the context id. Here be magic! */ 987 intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0); 988 989 /* Wait for the ring not to be idle, i.e. for it to wake up. */ 990 if (__intel_wait_for_register_fw(uncore, 991 GEN6_BSD_SLEEP_PSMI_CONTROL, 992 GEN6_BSD_SLEEP_INDICATOR, 993 0, 994 1000, 0, NULL)) 995 drm_err(&uncore->i915->drm, 996 "timed out waiting for the BSD ring to wake up\n"); 997 998 /* Now that the ring is fully powered up, update the tail */ 999 i9xx_submit_request(request); 1000 1001 /* Let the ring send IDLE messages to the GT again, 1002 * and so let it sleep to conserve power when idle. 1003 */ 1004 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL, 1005 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); 1006 1007 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 1008 } 1009 1010 static void i9xx_set_default_submission(struct intel_engine_cs *engine) 1011 { 1012 engine->submit_request = i9xx_submit_request; 1013 1014 engine->park = NULL; 1015 engine->unpark = NULL; 1016 } 1017 1018 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) 1019 { 1020 i9xx_set_default_submission(engine); 1021 engine->submit_request = gen6_bsd_submit_request; 1022 } 1023 1024 static void ring_release(struct intel_engine_cs *engine) 1025 { 1026 struct drm_i915_private *dev_priv = engine->i915; 1027 1028 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) > 2 && 1029 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); 1030 1031 intel_engine_cleanup_common(engine); 1032 1033 if (engine->wa_ctx.vma) { 1034 intel_context_put(engine->wa_ctx.vma->private); 1035 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); 1036 } 1037 1038 intel_ring_unpin(engine->legacy.ring); 1039 intel_ring_put(engine->legacy.ring); 1040 1041 intel_timeline_unpin(engine->legacy.timeline); 1042 intel_timeline_put(engine->legacy.timeline); 1043 } 1044 1045 static void setup_irq(struct intel_engine_cs *engine) 1046 { 1047 struct drm_i915_private *i915 = engine->i915; 1048 1049 if (INTEL_GEN(i915) >= 6) { 1050 engine->irq_enable = gen6_irq_enable; 1051 engine->irq_disable = gen6_irq_disable; 1052 } else if (INTEL_GEN(i915) >= 5) { 1053 engine->irq_enable = gen5_irq_enable; 1054 engine->irq_disable = gen5_irq_disable; 1055 } else if (INTEL_GEN(i915) >= 3) { 1056 engine->irq_enable = gen3_irq_enable; 1057 engine->irq_disable = gen3_irq_disable; 1058 } else { 1059 engine->irq_enable = gen2_irq_enable; 1060 engine->irq_disable = gen2_irq_disable; 1061 } 1062 } 1063 1064 static void setup_common(struct intel_engine_cs *engine) 1065 { 1066 struct drm_i915_private *i915 = engine->i915; 1067 1068 /* gen8+ are only supported with execlists */ 1069 GEM_BUG_ON(INTEL_GEN(i915) >= 8); 1070 1071 setup_irq(engine); 1072 1073 engine->resume = xcs_resume; 1074 engine->reset.prepare = reset_prepare; 1075 engine->reset.rewind = reset_rewind; 1076 engine->reset.cancel = reset_cancel; 1077 engine->reset.finish = reset_finish; 1078 1079 engine->cops = &ring_context_ops; 1080 engine->request_alloc = ring_request_alloc; 1081 1082 /* 1083 * Using a global execution timeline; the previous final breadcrumb is 1084 * equivalent to our next initial bread so we can elide 1085 * engine->emit_init_breadcrumb(). 1086 */ 1087 engine->emit_fini_breadcrumb = gen3_emit_breadcrumb; 1088 if (IS_GEN(i915, 5)) 1089 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; 1090 1091 engine->set_default_submission = i9xx_set_default_submission; 1092 1093 if (INTEL_GEN(i915) >= 6) 1094 engine->emit_bb_start = gen6_emit_bb_start; 1095 else if (INTEL_GEN(i915) >= 4) 1096 engine->emit_bb_start = gen4_emit_bb_start; 1097 else if (IS_I830(i915) || IS_I845G(i915)) 1098 engine->emit_bb_start = i830_emit_bb_start; 1099 else 1100 engine->emit_bb_start = gen3_emit_bb_start; 1101 } 1102 1103 static void setup_rcs(struct intel_engine_cs *engine) 1104 { 1105 struct drm_i915_private *i915 = engine->i915; 1106 1107 if (HAS_L3_DPF(i915)) 1108 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; 1109 1110 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; 1111 1112 if (INTEL_GEN(i915) >= 7) { 1113 engine->emit_flush = gen7_emit_flush_rcs; 1114 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs; 1115 } else if (IS_GEN(i915, 6)) { 1116 engine->emit_flush = gen6_emit_flush_rcs; 1117 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs; 1118 } else if (IS_GEN(i915, 5)) { 1119 engine->emit_flush = gen4_emit_flush_rcs; 1120 } else { 1121 if (INTEL_GEN(i915) < 4) 1122 engine->emit_flush = gen2_emit_flush; 1123 else 1124 engine->emit_flush = gen4_emit_flush_rcs; 1125 engine->irq_enable_mask = I915_USER_INTERRUPT; 1126 } 1127 1128 if (IS_HASWELL(i915)) 1129 engine->emit_bb_start = hsw_emit_bb_start; 1130 } 1131 1132 static void setup_vcs(struct intel_engine_cs *engine) 1133 { 1134 struct drm_i915_private *i915 = engine->i915; 1135 1136 if (INTEL_GEN(i915) >= 6) { 1137 /* gen6 bsd needs a special wa for tail updates */ 1138 if (IS_GEN(i915, 6)) 1139 engine->set_default_submission = gen6_bsd_set_default_submission; 1140 engine->emit_flush = gen6_emit_flush_vcs; 1141 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; 1142 1143 if (IS_GEN(i915, 6)) 1144 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; 1145 else 1146 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; 1147 } else { 1148 engine->emit_flush = gen4_emit_flush_vcs; 1149 if (IS_GEN(i915, 5)) 1150 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; 1151 else 1152 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; 1153 } 1154 } 1155 1156 static void setup_bcs(struct intel_engine_cs *engine) 1157 { 1158 struct drm_i915_private *i915 = engine->i915; 1159 1160 engine->emit_flush = gen6_emit_flush_xcs; 1161 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; 1162 1163 if (IS_GEN(i915, 6)) 1164 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; 1165 else 1166 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; 1167 } 1168 1169 static void setup_vecs(struct intel_engine_cs *engine) 1170 { 1171 struct drm_i915_private *i915 = engine->i915; 1172 1173 GEM_BUG_ON(INTEL_GEN(i915) < 7); 1174 1175 engine->emit_flush = gen6_emit_flush_xcs; 1176 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; 1177 engine->irq_enable = hsw_irq_enable_vecs; 1178 engine->irq_disable = hsw_irq_disable_vecs; 1179 1180 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; 1181 } 1182 1183 static int gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine, 1184 struct i915_vma * const vma) 1185 { 1186 return gen7_setup_clear_gpr_bb(engine, vma); 1187 } 1188 1189 static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine) 1190 { 1191 struct drm_i915_gem_object *obj; 1192 struct i915_vma *vma; 1193 int size; 1194 int err; 1195 1196 size = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */); 1197 if (size <= 0) 1198 return size; 1199 1200 size = ALIGN(size, PAGE_SIZE); 1201 obj = i915_gem_object_create_internal(engine->i915, size); 1202 if (IS_ERR(obj)) 1203 return PTR_ERR(obj); 1204 1205 vma = i915_vma_instance(obj, engine->gt->vm, NULL); 1206 if (IS_ERR(vma)) { 1207 err = PTR_ERR(vma); 1208 goto err_obj; 1209 } 1210 1211 vma->private = intel_context_create(engine); /* dummy residuals */ 1212 if (IS_ERR(vma->private)) { 1213 err = PTR_ERR(vma->private); 1214 goto err_obj; 1215 } 1216 1217 err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH); 1218 if (err) 1219 goto err_private; 1220 1221 err = i915_vma_sync(vma); 1222 if (err) 1223 goto err_unpin; 1224 1225 err = gen7_ctx_switch_bb_setup(engine, vma); 1226 if (err) 1227 goto err_unpin; 1228 1229 engine->wa_ctx.vma = vma; 1230 return 0; 1231 1232 err_unpin: 1233 i915_vma_unpin(vma); 1234 err_private: 1235 intel_context_put(vma->private); 1236 err_obj: 1237 i915_gem_object_put(obj); 1238 return err; 1239 } 1240 1241 int intel_ring_submission_setup(struct intel_engine_cs *engine) 1242 { 1243 struct intel_timeline *timeline; 1244 struct intel_ring *ring; 1245 int err; 1246 1247 setup_common(engine); 1248 1249 switch (engine->class) { 1250 case RENDER_CLASS: 1251 setup_rcs(engine); 1252 break; 1253 case VIDEO_DECODE_CLASS: 1254 setup_vcs(engine); 1255 break; 1256 case COPY_ENGINE_CLASS: 1257 setup_bcs(engine); 1258 break; 1259 case VIDEO_ENHANCEMENT_CLASS: 1260 setup_vecs(engine); 1261 break; 1262 default: 1263 MISSING_CASE(engine->class); 1264 return -ENODEV; 1265 } 1266 1267 timeline = intel_timeline_create_from_engine(engine, 1268 I915_GEM_HWS_SEQNO_ADDR); 1269 if (IS_ERR(timeline)) { 1270 err = PTR_ERR(timeline); 1271 goto err; 1272 } 1273 GEM_BUG_ON(timeline->has_initial_breadcrumb); 1274 1275 err = intel_timeline_pin(timeline, NULL); 1276 if (err) 1277 goto err_timeline; 1278 1279 ring = intel_engine_create_ring(engine, SZ_16K); 1280 if (IS_ERR(ring)) { 1281 err = PTR_ERR(ring); 1282 goto err_timeline_unpin; 1283 } 1284 1285 err = intel_ring_pin(ring, NULL); 1286 if (err) 1287 goto err_ring; 1288 1289 GEM_BUG_ON(engine->legacy.ring); 1290 engine->legacy.ring = ring; 1291 engine->legacy.timeline = timeline; 1292 1293 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma); 1294 1295 if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) { 1296 err = gen7_ctx_switch_bb_init(engine); 1297 if (err) 1298 goto err_ring_unpin; 1299 } 1300 1301 /* Finally, take ownership and responsibility for cleanup! */ 1302 engine->release = ring_release; 1303 1304 return 0; 1305 1306 err_ring_unpin: 1307 intel_ring_unpin(ring); 1308 err_ring: 1309 intel_ring_put(ring); 1310 err_timeline_unpin: 1311 intel_timeline_unpin(timeline); 1312 err_timeline: 1313 intel_timeline_put(timeline); 1314 err: 1315 intel_engine_cleanup_common(engine); 1316 return err; 1317 } 1318 1319 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1320 #include "selftest_ring_submission.c" 1321 #endif 1322