1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include "gem/i915_gem_lmem.h" 7 #include "gem/i915_gem_object.h" 8 9 #include "i915_drv.h" 10 #include "i915_vma.h" 11 #include "intel_engine.h" 12 #include "intel_gpu_commands.h" 13 #include "intel_ring.h" 14 #include "intel_timeline.h" 15 16 unsigned int intel_ring_update_space(struct intel_ring *ring) 17 { 18 unsigned int space; 19 20 space = __intel_ring_space(ring->head, ring->emit, ring->size); 21 22 ring->space = space; 23 return space; 24 } 25 26 void __intel_ring_pin(struct intel_ring *ring) 27 { 28 GEM_BUG_ON(!atomic_read(&ring->pin_count)); 29 atomic_inc(&ring->pin_count); 30 } 31 32 int intel_ring_pin(struct intel_ring *ring, struct i915_gem_ww_ctx *ww) 33 { 34 struct i915_vma *vma = ring->vma; 35 unsigned int flags; 36 void *addr; 37 int ret; 38 39 if (atomic_fetch_inc(&ring->pin_count)) 40 return 0; 41 42 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ 43 flags = PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); 44 45 if (i915_gem_object_is_stolen(vma->obj)) 46 flags |= PIN_MAPPABLE; 47 else 48 flags |= PIN_HIGH; 49 50 ret = i915_ggtt_pin(vma, ww, 0, flags); 51 if (unlikely(ret)) 52 goto err_unpin; 53 54 if (i915_vma_is_map_and_fenceable(vma)) 55 addr = (void __force *)i915_vma_pin_iomap(vma); 56 else 57 addr = i915_gem_object_pin_map(vma->obj, 58 i915_coherent_map_type(vma->vm->i915)); 59 if (IS_ERR(addr)) { 60 ret = PTR_ERR(addr); 61 goto err_ring; 62 } 63 64 i915_vma_make_unshrinkable(vma); 65 66 /* Discard any unused bytes beyond that submitted to hw. */ 67 intel_ring_reset(ring, ring->emit); 68 69 ring->vaddr = addr; 70 return 0; 71 72 err_ring: 73 i915_vma_unpin(vma); 74 err_unpin: 75 atomic_dec(&ring->pin_count); 76 return ret; 77 } 78 79 void intel_ring_reset(struct intel_ring *ring, u32 tail) 80 { 81 tail = intel_ring_wrap(ring, tail); 82 ring->tail = tail; 83 ring->head = tail; 84 ring->emit = tail; 85 intel_ring_update_space(ring); 86 } 87 88 void intel_ring_unpin(struct intel_ring *ring) 89 { 90 struct i915_vma *vma = ring->vma; 91 92 if (!atomic_dec_and_test(&ring->pin_count)) 93 return; 94 95 i915_vma_unset_ggtt_write(vma); 96 if (i915_vma_is_map_and_fenceable(vma)) 97 i915_vma_unpin_iomap(vma); 98 else 99 i915_gem_object_unpin_map(vma->obj); 100 101 i915_vma_make_purgeable(vma); 102 i915_vma_unpin(vma); 103 } 104 105 static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) 106 { 107 struct i915_address_space *vm = &ggtt->vm; 108 struct drm_i915_private *i915 = vm->i915; 109 struct drm_i915_gem_object *obj; 110 struct i915_vma *vma; 111 112 obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE); 113 if (IS_ERR(obj) && i915_ggtt_has_aperture(ggtt)) 114 obj = i915_gem_object_create_stolen(i915, size); 115 if (IS_ERR(obj)) 116 obj = i915_gem_object_create_internal(i915, size); 117 if (IS_ERR(obj)) 118 return ERR_CAST(obj); 119 120 /* 121 * Mark ring buffers as read-only from GPU side (so no stray overwrites) 122 * if supported by the platform's GGTT. 123 */ 124 if (vm->has_read_only) 125 i915_gem_object_set_readonly(obj); 126 127 vma = i915_vma_instance(obj, vm, NULL); 128 if (IS_ERR(vma)) 129 goto err; 130 131 return vma; 132 133 err: 134 i915_gem_object_put(obj); 135 return vma; 136 } 137 138 struct intel_ring * 139 intel_engine_create_ring(struct intel_engine_cs *engine, int size) 140 { 141 struct drm_i915_private *i915 = engine->i915; 142 struct intel_ring *ring; 143 struct i915_vma *vma; 144 145 GEM_BUG_ON(!is_power_of_2(size)); 146 GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); 147 148 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 149 if (!ring) 150 return ERR_PTR(-ENOMEM); 151 152 kref_init(&ring->ref); 153 ring->size = size; 154 ring->wrap = BITS_PER_TYPE(ring->size) - ilog2(size); 155 156 /* 157 * Workaround an erratum on the i830 which causes a hang if 158 * the TAIL pointer points to within the last 2 cachelines 159 * of the buffer. 160 */ 161 ring->effective_size = size; 162 if (IS_I830(i915) || IS_I845G(i915)) 163 ring->effective_size -= 2 * CACHELINE_BYTES; 164 165 intel_ring_update_space(ring); 166 167 vma = create_ring_vma(engine->gt->ggtt, size); 168 if (IS_ERR(vma)) { 169 kfree(ring); 170 return ERR_CAST(vma); 171 } 172 ring->vma = vma; 173 174 return ring; 175 } 176 177 void intel_ring_free(struct kref *ref) 178 { 179 struct intel_ring *ring = container_of(ref, typeof(*ring), ref); 180 181 i915_vma_put(ring->vma); 182 kfree(ring); 183 } 184 185 static noinline int 186 wait_for_space(struct intel_ring *ring, 187 struct intel_timeline *tl, 188 unsigned int bytes) 189 { 190 struct i915_request *target; 191 long timeout; 192 193 if (intel_ring_update_space(ring) >= bytes) 194 return 0; 195 196 GEM_BUG_ON(list_empty(&tl->requests)); 197 list_for_each_entry(target, &tl->requests, link) { 198 if (target->ring != ring) 199 continue; 200 201 /* Would completion of this request free enough space? */ 202 if (bytes <= __intel_ring_space(target->postfix, 203 ring->emit, ring->size)) 204 break; 205 } 206 207 if (GEM_WARN_ON(&target->link == &tl->requests)) 208 return -ENOSPC; 209 210 timeout = i915_request_wait(target, 211 I915_WAIT_INTERRUPTIBLE, 212 MAX_SCHEDULE_TIMEOUT); 213 if (timeout < 0) 214 return timeout; 215 216 i915_request_retire_upto(target); 217 218 intel_ring_update_space(ring); 219 GEM_BUG_ON(ring->space < bytes); 220 return 0; 221 } 222 223 u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords) 224 { 225 struct intel_ring *ring = rq->ring; 226 const unsigned int remain_usable = ring->effective_size - ring->emit; 227 const unsigned int bytes = num_dwords * sizeof(u32); 228 unsigned int need_wrap = 0; 229 unsigned int total_bytes; 230 u32 *cs; 231 232 /* Packets must be qword aligned. */ 233 GEM_BUG_ON(num_dwords & 1); 234 235 total_bytes = bytes + rq->reserved_space; 236 GEM_BUG_ON(total_bytes > ring->effective_size); 237 238 if (unlikely(total_bytes > remain_usable)) { 239 const int remain_actual = ring->size - ring->emit; 240 241 if (bytes > remain_usable) { 242 /* 243 * Not enough space for the basic request. So need to 244 * flush out the remainder and then wait for 245 * base + reserved. 246 */ 247 total_bytes += remain_actual; 248 need_wrap = remain_actual | 1; 249 } else { 250 /* 251 * The base request will fit but the reserved space 252 * falls off the end. So we don't need an immediate 253 * wrap and only need to effectively wait for the 254 * reserved size from the start of ringbuffer. 255 */ 256 total_bytes = rq->reserved_space + remain_actual; 257 } 258 } 259 260 if (unlikely(total_bytes > ring->space)) { 261 int ret; 262 263 /* 264 * Space is reserved in the ringbuffer for finalising the 265 * request, as that cannot be allowed to fail. During request 266 * finalisation, reserved_space is set to 0 to stop the 267 * overallocation and the assumption is that then we never need 268 * to wait (which has the risk of failing with EINTR). 269 * 270 * See also i915_request_alloc() and i915_request_add(). 271 */ 272 GEM_BUG_ON(!rq->reserved_space); 273 274 ret = wait_for_space(ring, 275 i915_request_timeline(rq), 276 total_bytes); 277 if (unlikely(ret)) 278 return ERR_PTR(ret); 279 } 280 281 if (unlikely(need_wrap)) { 282 need_wrap &= ~1; 283 GEM_BUG_ON(need_wrap > ring->space); 284 GEM_BUG_ON(ring->emit + need_wrap > ring->size); 285 GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64))); 286 287 /* Fill the tail with MI_NOOP */ 288 memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64)); 289 ring->space -= need_wrap; 290 ring->emit = 0; 291 } 292 293 GEM_BUG_ON(ring->emit > ring->size - bytes); 294 GEM_BUG_ON(ring->space < bytes); 295 cs = ring->vaddr + ring->emit; 296 GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs))); 297 ring->emit += bytes; 298 ring->space -= bytes; 299 300 return cs; 301 } 302 303 /* Align the ring tail to a cacheline boundary */ 304 int intel_ring_cacheline_align(struct i915_request *rq) 305 { 306 int num_dwords; 307 void *cs; 308 309 num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32); 310 if (num_dwords == 0) 311 return 0; 312 313 num_dwords = CACHELINE_DWORDS - num_dwords; 314 GEM_BUG_ON(num_dwords & 1); 315 316 cs = intel_ring_begin(rq, num_dwords); 317 if (IS_ERR(cs)) 318 return PTR_ERR(cs); 319 320 memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2); 321 intel_ring_advance(rq, cs + num_dwords); 322 323 GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); 324 return 0; 325 } 326 327 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 328 #include "selftest_ring.c" 329 #endif 330