1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Mika Kuoppala <mika.kuoppala@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_renderstate.h" 30 #include "intel_context.h" 31 #include "intel_gpu_commands.h" 32 #include "intel_ring.h" 33 34 static const struct intel_renderstate_rodata * 35 render_state_get_rodata(const struct intel_engine_cs *engine) 36 { 37 if (engine->class != RENDER_CLASS) 38 return NULL; 39 40 switch (INTEL_GEN(engine->i915)) { 41 case 6: 42 return &gen6_null_state; 43 case 7: 44 return &gen7_null_state; 45 case 8: 46 return &gen8_null_state; 47 case 9: 48 return &gen9_null_state; 49 } 50 51 return NULL; 52 } 53 54 /* 55 * Macro to add commands to auxiliary batch. 56 * This macro only checks for page overflow before inserting the commands, 57 * this is sufficient as the null state generator makes the final batch 58 * with two passes to build command and state separately. At this point 59 * the size of both are known and it compacts them by relocating the state 60 * right after the commands taking care of alignment so we should sufficient 61 * space below them for adding new commands. 62 */ 63 #define OUT_BATCH(batch, i, val) \ 64 do { \ 65 if ((i) >= PAGE_SIZE / sizeof(u32)) \ 66 goto out; \ 67 (batch)[(i)++] = (val); \ 68 } while(0) 69 70 static int render_state_setup(struct intel_renderstate *so, 71 struct drm_i915_private *i915) 72 { 73 const struct intel_renderstate_rodata *rodata = so->rodata; 74 unsigned int i = 0, reloc_index = 0; 75 int ret = -EINVAL; 76 u32 *d; 77 78 d = i915_gem_object_pin_map(so->vma->obj, I915_MAP_WB); 79 if (IS_ERR(d)) 80 return PTR_ERR(d); 81 82 while (i < rodata->batch_items) { 83 u32 s = rodata->batch[i]; 84 85 if (i * 4 == rodata->reloc[reloc_index]) { 86 u64 r = s + so->vma->node.start; 87 s = lower_32_bits(r); 88 if (HAS_64BIT_RELOC(i915)) { 89 if (i + 1 >= rodata->batch_items || 90 rodata->batch[i + 1] != 0) 91 goto out; 92 93 d[i++] = s; 94 s = upper_32_bits(r); 95 } 96 97 reloc_index++; 98 } 99 100 d[i++] = s; 101 } 102 103 if (rodata->reloc[reloc_index] != -1) { 104 drm_err(&i915->drm, "only %d relocs resolved\n", reloc_index); 105 goto out; 106 } 107 108 so->batch_offset = i915_ggtt_offset(so->vma); 109 so->batch_size = rodata->batch_items * sizeof(u32); 110 111 while (i % CACHELINE_DWORDS) 112 OUT_BATCH(d, i, MI_NOOP); 113 114 so->aux_offset = i * sizeof(u32); 115 116 if (HAS_POOLED_EU(i915)) { 117 /* 118 * We always program 3x6 pool config but depending upon which 119 * subslice is disabled HW drops down to appropriate config 120 * shown below. 121 * 122 * In the below table 2x6 config always refers to 123 * fused-down version, native 2x6 is not available and can 124 * be ignored 125 * 126 * SNo subslices config eu pool configuration 127 * ----------------------------------------------------------- 128 * 1 3 subslices enabled (3x6) - 0x00777000 (9+9) 129 * 2 ss0 disabled (2x6) - 0x00777000 (3+9) 130 * 3 ss1 disabled (2x6) - 0x00770000 (6+6) 131 * 4 ss2 disabled (2x6) - 0x00007000 (9+3) 132 */ 133 u32 eu_pool_config = 0x00777000; 134 135 OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE); 136 OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE); 137 OUT_BATCH(d, i, eu_pool_config); 138 OUT_BATCH(d, i, 0); 139 OUT_BATCH(d, i, 0); 140 OUT_BATCH(d, i, 0); 141 } 142 143 OUT_BATCH(d, i, MI_BATCH_BUFFER_END); 144 so->aux_size = i * sizeof(u32) - so->aux_offset; 145 so->aux_offset += so->batch_offset; 146 /* 147 * Since we are sending length, we need to strictly conform to 148 * all requirements. For Gen2 this must be a multiple of 8. 149 */ 150 so->aux_size = ALIGN(so->aux_size, 8); 151 152 ret = 0; 153 out: 154 __i915_gem_object_flush_map(so->vma->obj, 0, i * sizeof(u32)); 155 __i915_gem_object_release_map(so->vma->obj); 156 return ret; 157 } 158 159 #undef OUT_BATCH 160 161 int intel_renderstate_init(struct intel_renderstate *so, 162 struct intel_context *ce) 163 { 164 struct intel_engine_cs *engine = ce->engine; 165 struct drm_i915_gem_object *obj = NULL; 166 int err; 167 168 memset(so, 0, sizeof(*so)); 169 170 so->rodata = render_state_get_rodata(engine); 171 if (so->rodata) { 172 if (so->rodata->batch_items * 4 > PAGE_SIZE) 173 return -EINVAL; 174 175 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); 176 if (IS_ERR(obj)) 177 return PTR_ERR(obj); 178 179 so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 180 if (IS_ERR(so->vma)) { 181 err = PTR_ERR(so->vma); 182 goto err_obj; 183 } 184 } 185 186 i915_gem_ww_ctx_init(&so->ww, true); 187 retry: 188 err = intel_context_pin_ww(ce, &so->ww); 189 if (err) 190 goto err_fini; 191 192 /* return early if there's nothing to setup */ 193 if (!err && !so->rodata) 194 return 0; 195 196 err = i915_gem_object_lock(so->vma->obj, &so->ww); 197 if (err) 198 goto err_context; 199 200 err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH); 201 if (err) 202 goto err_context; 203 204 err = render_state_setup(so, engine->i915); 205 if (err) 206 goto err_unpin; 207 208 return 0; 209 210 err_unpin: 211 i915_vma_unpin(so->vma); 212 err_context: 213 intel_context_unpin(ce); 214 err_fini: 215 if (err == -EDEADLK) { 216 err = i915_gem_ww_ctx_backoff(&so->ww); 217 if (!err) 218 goto retry; 219 } 220 i915_gem_ww_ctx_fini(&so->ww); 221 err_obj: 222 if (obj) 223 i915_gem_object_put(obj); 224 so->vma = NULL; 225 return err; 226 } 227 228 int intel_renderstate_emit(struct intel_renderstate *so, 229 struct i915_request *rq) 230 { 231 struct intel_engine_cs *engine = rq->engine; 232 int err; 233 234 if (!so->vma) 235 return 0; 236 237 err = i915_request_await_object(rq, so->vma->obj, false); 238 if (err == 0) 239 err = i915_vma_move_to_active(so->vma, rq, 0); 240 if (err) 241 return err; 242 243 err = engine->emit_bb_start(rq, 244 so->batch_offset, so->batch_size, 245 I915_DISPATCH_SECURE); 246 if (err) 247 return err; 248 249 if (so->aux_size > 8) { 250 err = engine->emit_bb_start(rq, 251 so->aux_offset, so->aux_size, 252 I915_DISPATCH_SECURE); 253 if (err) 254 return err; 255 } 256 257 return 0; 258 } 259 260 void intel_renderstate_fini(struct intel_renderstate *so, 261 struct intel_context *ce) 262 { 263 if (so->vma) { 264 i915_vma_unpin(so->vma); 265 i915_vma_close(so->vma); 266 } 267 268 intel_context_unpin(ce); 269 i915_gem_ww_ctx_fini(&so->ww); 270 271 if (so->vma) 272 i915_gem_object_put(so->vma->obj); 273 } 274