1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Mika Kuoppala <mika.kuoppala@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_renderstate.h" 30 #include "intel_ring.h" 31 32 static const struct intel_renderstate_rodata * 33 render_state_get_rodata(const struct intel_engine_cs *engine) 34 { 35 if (engine->class != RENDER_CLASS) 36 return NULL; 37 38 switch (INTEL_GEN(engine->i915)) { 39 case 6: 40 return &gen6_null_state; 41 case 7: 42 return &gen7_null_state; 43 case 8: 44 return &gen8_null_state; 45 case 9: 46 return &gen9_null_state; 47 } 48 49 return NULL; 50 } 51 52 /* 53 * Macro to add commands to auxiliary batch. 54 * This macro only checks for page overflow before inserting the commands, 55 * this is sufficient as the null state generator makes the final batch 56 * with two passes to build command and state separately. At this point 57 * the size of both are known and it compacts them by relocating the state 58 * right after the commands taking care of alignment so we should sufficient 59 * space below them for adding new commands. 60 */ 61 #define OUT_BATCH(batch, i, val) \ 62 do { \ 63 if ((i) >= PAGE_SIZE / sizeof(u32)) \ 64 goto err; \ 65 (batch)[(i)++] = (val); \ 66 } while(0) 67 68 static int render_state_setup(struct intel_renderstate *so, 69 struct drm_i915_private *i915) 70 { 71 const struct intel_renderstate_rodata *rodata = so->rodata; 72 unsigned int i = 0, reloc_index = 0; 73 unsigned int needs_clflush; 74 u32 *d; 75 int ret; 76 77 ret = i915_gem_object_prepare_write(so->vma->obj, &needs_clflush); 78 if (ret) 79 return ret; 80 81 d = kmap_atomic(i915_gem_object_get_dirty_page(so->vma->obj, 0)); 82 83 while (i < rodata->batch_items) { 84 u32 s = rodata->batch[i]; 85 86 if (i * 4 == rodata->reloc[reloc_index]) { 87 u64 r = s + so->vma->node.start; 88 s = lower_32_bits(r); 89 if (HAS_64BIT_RELOC(i915)) { 90 if (i + 1 >= rodata->batch_items || 91 rodata->batch[i + 1] != 0) 92 goto err; 93 94 d[i++] = s; 95 s = upper_32_bits(r); 96 } 97 98 reloc_index++; 99 } 100 101 d[i++] = s; 102 } 103 104 if (rodata->reloc[reloc_index] != -1) { 105 DRM_ERROR("only %d relocs resolved\n", reloc_index); 106 goto err; 107 } 108 109 so->batch_offset = i915_ggtt_offset(so->vma); 110 so->batch_size = rodata->batch_items * sizeof(u32); 111 112 while (i % CACHELINE_DWORDS) 113 OUT_BATCH(d, i, MI_NOOP); 114 115 so->aux_offset = i * sizeof(u32); 116 117 if (HAS_POOLED_EU(i915)) { 118 /* 119 * We always program 3x6 pool config but depending upon which 120 * subslice is disabled HW drops down to appropriate config 121 * shown below. 122 * 123 * In the below table 2x6 config always refers to 124 * fused-down version, native 2x6 is not available and can 125 * be ignored 126 * 127 * SNo subslices config eu pool configuration 128 * ----------------------------------------------------------- 129 * 1 3 subslices enabled (3x6) - 0x00777000 (9+9) 130 * 2 ss0 disabled (2x6) - 0x00777000 (3+9) 131 * 3 ss1 disabled (2x6) - 0x00770000 (6+6) 132 * 4 ss2 disabled (2x6) - 0x00007000 (9+3) 133 */ 134 u32 eu_pool_config = 0x00777000; 135 136 OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE); 137 OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE); 138 OUT_BATCH(d, i, eu_pool_config); 139 OUT_BATCH(d, i, 0); 140 OUT_BATCH(d, i, 0); 141 OUT_BATCH(d, i, 0); 142 } 143 144 OUT_BATCH(d, i, MI_BATCH_BUFFER_END); 145 so->aux_size = i * sizeof(u32) - so->aux_offset; 146 so->aux_offset += so->batch_offset; 147 /* 148 * Since we are sending length, we need to strictly conform to 149 * all requirements. For Gen2 this must be a multiple of 8. 150 */ 151 so->aux_size = ALIGN(so->aux_size, 8); 152 153 if (needs_clflush) 154 drm_clflush_virt_range(d, i * sizeof(u32)); 155 kunmap_atomic(d); 156 157 ret = 0; 158 out: 159 i915_gem_object_finish_access(so->vma->obj); 160 return ret; 161 162 err: 163 kunmap_atomic(d); 164 ret = -EINVAL; 165 goto out; 166 } 167 168 #undef OUT_BATCH 169 170 int intel_renderstate_init(struct intel_renderstate *so, 171 struct intel_engine_cs *engine) 172 { 173 struct drm_i915_gem_object *obj; 174 int err; 175 176 memset(so, 0, sizeof(*so)); 177 178 so->rodata = render_state_get_rodata(engine); 179 if (!so->rodata) 180 return 0; 181 182 if (so->rodata->batch_items * 4 > PAGE_SIZE) 183 return -EINVAL; 184 185 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); 186 if (IS_ERR(obj)) 187 return PTR_ERR(obj); 188 189 so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 190 if (IS_ERR(so->vma)) { 191 err = PTR_ERR(so->vma); 192 goto err_obj; 193 } 194 195 err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH); 196 if (err) 197 goto err_vma; 198 199 err = render_state_setup(so, engine->i915); 200 if (err) 201 goto err_unpin; 202 203 return 0; 204 205 err_unpin: 206 i915_vma_unpin(so->vma); 207 err_vma: 208 i915_vma_close(so->vma); 209 err_obj: 210 i915_gem_object_put(obj); 211 so->vma = NULL; 212 return err; 213 } 214 215 int intel_renderstate_emit(struct intel_renderstate *so, 216 struct i915_request *rq) 217 { 218 struct intel_engine_cs *engine = rq->engine; 219 int err; 220 221 if (!so->vma) 222 return 0; 223 224 err = engine->emit_bb_start(rq, 225 so->batch_offset, so->batch_size, 226 I915_DISPATCH_SECURE); 227 if (err) 228 return err; 229 230 if (so->aux_size > 8) { 231 err = engine->emit_bb_start(rq, 232 so->aux_offset, so->aux_size, 233 I915_DISPATCH_SECURE); 234 if (err) 235 return err; 236 } 237 238 i915_vma_lock(so->vma); 239 err = i915_request_await_object(rq, so->vma->obj, false); 240 if (err == 0) 241 err = i915_vma_move_to_active(so->vma, rq, 0); 242 i915_vma_unlock(so->vma); 243 244 return err; 245 } 246 247 void intel_renderstate_fini(struct intel_renderstate *so) 248 { 249 i915_vma_unpin_and_release(&so->vma, 0); 250 } 251