1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/pm_runtime.h> 7 8 #include "i915_drv.h" 9 #include "i915_vgpu.h" 10 #include "intel_gt.h" 11 #include "intel_gt_pm.h" 12 #include "intel_pcode.h" 13 #include "intel_rc6.h" 14 15 /** 16 * DOC: RC6 17 * 18 * RC6 is a special power stage which allows the GPU to enter an very 19 * low-voltage mode when idle, using down to 0V while at this stage. This 20 * stage is entered automatically when the GPU is idle when RC6 support is 21 * enabled, and as soon as new workload arises GPU wakes up automatically as 22 * well. 23 * 24 * There are different RC6 modes available in Intel GPU, which differentiate 25 * among each other with the latency required to enter and leave RC6 and 26 * voltage consumed by the GPU in different states. 27 * 28 * The combination of the following flags define which states GPU is allowed 29 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 30 * RC6pp is deepest RC6. Their support by hardware varies according to the 31 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 32 * which brings the most power savings; deeper states save more power, but 33 * require higher latency to switch to and wake up. 34 */ 35 36 static struct intel_gt *rc6_to_gt(struct intel_rc6 *rc6) 37 { 38 return container_of(rc6, struct intel_gt, rc6); 39 } 40 41 static struct intel_uncore *rc6_to_uncore(struct intel_rc6 *rc) 42 { 43 return rc6_to_gt(rc)->uncore; 44 } 45 46 static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc) 47 { 48 return rc6_to_gt(rc)->i915; 49 } 50 51 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) 52 { 53 intel_uncore_write_fw(uncore, reg, val); 54 } 55 56 static void gen11_rc6_enable(struct intel_rc6 *rc6) 57 { 58 struct intel_gt *gt = rc6_to_gt(rc6); 59 struct intel_uncore *uncore = gt->uncore; 60 struct intel_engine_cs *engine; 61 enum intel_engine_id id; 62 u32 pg_enable; 63 int i; 64 65 /* 66 * With GuCRC, these parameters are set by GuC 67 */ 68 if (!intel_uc_uses_guc_rc(>->uc)) { 69 /* 2b: Program RC6 thresholds.*/ 70 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); 71 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); 72 73 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 74 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 75 for_each_engine(engine, rc6_to_gt(rc6), id) 76 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 77 78 set(uncore, GUC_MAX_IDLE_COUNT, 0xA); 79 80 set(uncore, GEN6_RC_SLEEP, 0); 81 82 set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 83 } 84 85 /* 86 * 2c: Program Coarse Power Gating Policies. 87 * 88 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we 89 * use instead is a more conservative estimate for the maximum time 90 * it takes us to service a CS interrupt and submit a new ELSP - that 91 * is the time which the GPU is idle waiting for the CPU to select the 92 * next request to execute. If the idle hysteresis is less than that 93 * interrupt service latency, the hardware will automatically gate 94 * the power well and we will then incur the wake up cost on top of 95 * the service latency. A similar guide from plane_state is that we 96 * do not want the enable hysteresis to less than the wakeup latency. 97 * 98 * igt/gem_exec_nop/sequential provides a rough estimate for the 99 * service latency, and puts it under 10us for Icelake, similar to 100 * Broadwell+, To be conservative, we want to factor in a context 101 * switch on top (due to ksoftirqd). 102 */ 103 set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60); 104 set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60); 105 106 /* 3a: Enable RC6 107 * 108 * With GuCRC, we do not enable bit 31 of RC_CTL, 109 * thus allowing GuC to control RC6 entry/exit fully instead. 110 * We will not set the HW ENABLE and EI bits 111 */ 112 if (!intel_guc_rc_enable(>->uc.guc)) 113 rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE; 114 else 115 rc6->ctl_enable = 116 GEN6_RC_CTL_HW_ENABLE | 117 GEN6_RC_CTL_RC6_ENABLE | 118 GEN6_RC_CTL_EI_MODE(1); 119 120 pg_enable = 121 GEN9_RENDER_PG_ENABLE | 122 GEN9_MEDIA_PG_ENABLE | 123 GEN11_MEDIA_SAMPLER_PG_ENABLE; 124 125 if (GRAPHICS_VER(gt->i915) >= 12) { 126 for (i = 0; i < I915_MAX_VCS; i++) 127 if (HAS_ENGINE(gt, _VCS(i))) 128 pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) | 129 VDN_MFX_POWERGATE_ENABLE(i)); 130 } 131 132 set(uncore, GEN9_PG_ENABLE, pg_enable); 133 } 134 135 static void gen9_rc6_enable(struct intel_rc6 *rc6) 136 { 137 struct intel_uncore *uncore = rc6_to_uncore(rc6); 138 struct intel_engine_cs *engine; 139 enum intel_engine_id id; 140 141 /* 2b: Program RC6 thresholds.*/ 142 if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) { 143 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); 144 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); 145 } else if (IS_SKYLAKE(rc6_to_i915(rc6))) { 146 /* 147 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only 148 * when CPG is enabled 149 */ 150 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); 151 } else { 152 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); 153 } 154 155 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 156 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 157 for_each_engine(engine, rc6_to_gt(rc6), id) 158 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 159 160 set(uncore, GUC_MAX_IDLE_COUNT, 0xA); 161 162 set(uncore, GEN6_RC_SLEEP, 0); 163 164 /* 165 * 2c: Program Coarse Power Gating Policies. 166 * 167 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we 168 * use instead is a more conservative estimate for the maximum time 169 * it takes us to service a CS interrupt and submit a new ELSP - that 170 * is the time which the GPU is idle waiting for the CPU to select the 171 * next request to execute. If the idle hysteresis is less than that 172 * interrupt service latency, the hardware will automatically gate 173 * the power well and we will then incur the wake up cost on top of 174 * the service latency. A similar guide from plane_state is that we 175 * do not want the enable hysteresis to less than the wakeup latency. 176 * 177 * igt/gem_exec_nop/sequential provides a rough estimate for the 178 * service latency, and puts it around 10us for Broadwell (and other 179 * big core) and around 40us for Broxton (and other low power cores). 180 * [Note that for legacy ringbuffer submission, this is less than 1us!] 181 * However, the wakeup latency on Broxton is closer to 100us. To be 182 * conservative, we have to factor in a context switch on top (due 183 * to ksoftirqd). 184 */ 185 set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250); 186 set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250); 187 188 /* 3a: Enable RC6 */ 189 set(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ 190 191 rc6->ctl_enable = 192 GEN6_RC_CTL_HW_ENABLE | 193 GEN6_RC_CTL_RC6_ENABLE | 194 GEN6_RC_CTL_EI_MODE(1); 195 196 /* 197 * WaRsDisableCoarsePowerGating:skl,cnl 198 * - Render/Media PG need to be disabled with RC6. 199 */ 200 if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6))) 201 set(uncore, GEN9_PG_ENABLE, 202 GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE); 203 } 204 205 static void gen8_rc6_enable(struct intel_rc6 *rc6) 206 { 207 struct intel_uncore *uncore = rc6_to_uncore(rc6); 208 struct intel_engine_cs *engine; 209 enum intel_engine_id id; 210 211 /* 2b: Program RC6 thresholds.*/ 212 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 213 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 214 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 215 for_each_engine(engine, rc6_to_gt(rc6), id) 216 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 217 set(uncore, GEN6_RC_SLEEP, 0); 218 set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ 219 220 /* 3: Enable RC6 */ 221 rc6->ctl_enable = 222 GEN6_RC_CTL_HW_ENABLE | 223 GEN7_RC_CTL_TO_MODE | 224 GEN6_RC_CTL_RC6_ENABLE; 225 } 226 227 static void gen6_rc6_enable(struct intel_rc6 *rc6) 228 { 229 struct intel_uncore *uncore = rc6_to_uncore(rc6); 230 struct drm_i915_private *i915 = rc6_to_i915(rc6); 231 struct intel_engine_cs *engine; 232 enum intel_engine_id id; 233 u32 rc6vids, rc6_mask; 234 int ret; 235 236 set(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 237 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 238 set(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 239 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); 240 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); 241 242 for_each_engine(engine, rc6_to_gt(rc6), id) 243 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 244 245 set(uncore, GEN6_RC_SLEEP, 0); 246 set(uncore, GEN6_RC1e_THRESHOLD, 1000); 247 set(uncore, GEN6_RC6_THRESHOLD, 50000); 248 set(uncore, GEN6_RC6p_THRESHOLD, 150000); 249 set(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 250 251 /* We don't use those on Haswell */ 252 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 253 if (HAS_RC6p(i915)) 254 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 255 if (HAS_RC6pp(i915)) 256 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 257 rc6->ctl_enable = 258 rc6_mask | 259 GEN6_RC_CTL_EI_MODE(1) | 260 GEN6_RC_CTL_HW_ENABLE; 261 262 rc6vids = 0; 263 ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, 264 &rc6vids, NULL); 265 if (GRAPHICS_VER(i915) == 6 && ret) { 266 drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n"); 267 } else if (GRAPHICS_VER(i915) == 6 && 268 (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 269 drm_dbg(&i915->drm, 270 "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 271 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 272 rc6vids &= 0xffff00; 273 rc6vids |= GEN6_ENCODE_RC6_VID(450); 274 ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 275 if (ret) 276 drm_err(&i915->drm, 277 "Couldn't fix incorrect rc6 voltage\n"); 278 } 279 } 280 281 /* Check that the pcbr address is not empty. */ 282 static int chv_rc6_init(struct intel_rc6 *rc6) 283 { 284 struct intel_uncore *uncore = rc6_to_uncore(rc6); 285 struct drm_i915_private *i915 = rc6_to_i915(rc6); 286 resource_size_t pctx_paddr, paddr; 287 resource_size_t pctx_size = 32 * SZ_1K; 288 u32 pcbr; 289 290 pcbr = intel_uncore_read(uncore, VLV_PCBR); 291 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { 292 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); 293 paddr = i915->dsm.end + 1 - pctx_size; 294 GEM_BUG_ON(paddr > U32_MAX); 295 296 pctx_paddr = (paddr & ~4095); 297 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr); 298 } 299 300 return 0; 301 } 302 303 static int vlv_rc6_init(struct intel_rc6 *rc6) 304 { 305 struct drm_i915_private *i915 = rc6_to_i915(rc6); 306 struct intel_uncore *uncore = rc6_to_uncore(rc6); 307 struct drm_i915_gem_object *pctx; 308 resource_size_t pctx_paddr; 309 resource_size_t pctx_size = 24 * SZ_1K; 310 u32 pcbr; 311 312 pcbr = intel_uncore_read(uncore, VLV_PCBR); 313 if (pcbr) { 314 /* BIOS set it up already, grab the pre-alloc'd space */ 315 resource_size_t pcbr_offset; 316 317 pcbr_offset = (pcbr & ~4095) - i915->dsm.start; 318 pctx = i915_gem_object_create_stolen_for_preallocated(i915, 319 pcbr_offset, 320 pctx_size); 321 if (IS_ERR(pctx)) 322 return PTR_ERR(pctx); 323 324 goto out; 325 } 326 327 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); 328 329 /* 330 * From the Gunit register HAS: 331 * The Gfx driver is expected to program this register and ensure 332 * proper allocation within Gfx stolen memory. For example, this 333 * register should be programmed such than the PCBR range does not 334 * overlap with other ranges, such as the frame buffer, protected 335 * memory, or any other relevant ranges. 336 */ 337 pctx = i915_gem_object_create_stolen(i915, pctx_size); 338 if (IS_ERR(pctx)) { 339 drm_dbg(&i915->drm, 340 "not enough stolen space for PCTX, disabling\n"); 341 return PTR_ERR(pctx); 342 } 343 344 GEM_BUG_ON(range_overflows_end_t(u64, 345 i915->dsm.start, 346 pctx->stolen->start, 347 U32_MAX)); 348 pctx_paddr = i915->dsm.start + pctx->stolen->start; 349 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr); 350 351 out: 352 rc6->pctx = pctx; 353 return 0; 354 } 355 356 static void chv_rc6_enable(struct intel_rc6 *rc6) 357 { 358 struct intel_uncore *uncore = rc6_to_uncore(rc6); 359 struct intel_engine_cs *engine; 360 enum intel_engine_id id; 361 362 /* 2a: Program RC6 thresholds.*/ 363 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 364 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 365 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 366 367 for_each_engine(engine, rc6_to_gt(rc6), id) 368 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 369 set(uncore, GEN6_RC_SLEEP, 0); 370 371 /* TO threshold set to 500 us (0x186 * 1.28 us) */ 372 set(uncore, GEN6_RC6_THRESHOLD, 0x186); 373 374 /* Allows RC6 residency counter to work */ 375 set(uncore, VLV_COUNTER_CONTROL, 376 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 377 VLV_MEDIA_RC6_COUNT_EN | 378 VLV_RENDER_RC6_COUNT_EN)); 379 380 /* 3: Enable RC6 */ 381 rc6->ctl_enable = GEN7_RC_CTL_TO_MODE; 382 } 383 384 static void vlv_rc6_enable(struct intel_rc6 *rc6) 385 { 386 struct intel_uncore *uncore = rc6_to_uncore(rc6); 387 struct intel_engine_cs *engine; 388 enum intel_engine_id id; 389 390 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); 391 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); 392 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); 393 394 for_each_engine(engine, rc6_to_gt(rc6), id) 395 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 396 397 set(uncore, GEN6_RC6_THRESHOLD, 0x557); 398 399 /* Allows RC6 residency counter to work */ 400 set(uncore, VLV_COUNTER_CONTROL, 401 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 402 VLV_MEDIA_RC0_COUNT_EN | 403 VLV_RENDER_RC0_COUNT_EN | 404 VLV_MEDIA_RC6_COUNT_EN | 405 VLV_RENDER_RC6_COUNT_EN)); 406 407 rc6->ctl_enable = 408 GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; 409 } 410 411 static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6) 412 { 413 struct intel_uncore *uncore = rc6_to_uncore(rc6); 414 struct drm_i915_private *i915 = rc6_to_i915(rc6); 415 u32 rc6_ctx_base, rc_ctl, rc_sw_target; 416 bool enable_rc6 = true; 417 418 rc_ctl = intel_uncore_read(uncore, GEN6_RC_CONTROL); 419 rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE); 420 rc_sw_target &= RC_SW_TARGET_STATE_MASK; 421 rc_sw_target >>= RC_SW_TARGET_STATE_SHIFT; 422 drm_dbg(&i915->drm, "BIOS enabled RC states: " 423 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n", 424 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE), 425 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE), 426 rc_sw_target); 427 428 if (!(intel_uncore_read(uncore, RC6_LOCATION) & RC6_CTX_IN_DRAM)) { 429 drm_dbg(&i915->drm, "RC6 Base location not set properly.\n"); 430 enable_rc6 = false; 431 } 432 433 /* 434 * The exact context size is not known for BXT, so assume a page size 435 * for this check. 436 */ 437 rc6_ctx_base = 438 intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK; 439 if (!(rc6_ctx_base >= i915->dsm_reserved.start && 440 rc6_ctx_base + PAGE_SIZE < i915->dsm_reserved.end)) { 441 drm_dbg(&i915->drm, "RC6 Base address not as expected.\n"); 442 enable_rc6 = false; 443 } 444 445 if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 && 446 (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 && 447 (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 && 448 (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) { 449 drm_dbg(&i915->drm, 450 "Engine Idle wait time not set properly.\n"); 451 enable_rc6 = false; 452 } 453 454 if (!intel_uncore_read(uncore, GEN8_PUSHBUS_CONTROL) || 455 !intel_uncore_read(uncore, GEN8_PUSHBUS_ENABLE) || 456 !intel_uncore_read(uncore, GEN8_PUSHBUS_SHIFT)) { 457 drm_dbg(&i915->drm, "Pushbus not setup properly.\n"); 458 enable_rc6 = false; 459 } 460 461 if (!intel_uncore_read(uncore, GEN6_GFXPAUSE)) { 462 drm_dbg(&i915->drm, "GFX pause not setup properly.\n"); 463 enable_rc6 = false; 464 } 465 466 if (!intel_uncore_read(uncore, GEN8_MISC_CTRL0)) { 467 drm_dbg(&i915->drm, "GPM control not setup properly.\n"); 468 enable_rc6 = false; 469 } 470 471 return enable_rc6; 472 } 473 474 static bool rc6_supported(struct intel_rc6 *rc6) 475 { 476 struct drm_i915_private *i915 = rc6_to_i915(rc6); 477 478 if (!HAS_RC6(i915)) 479 return false; 480 481 if (intel_vgpu_active(i915)) 482 return false; 483 484 if (is_mock_gt(rc6_to_gt(rc6))) 485 return false; 486 487 if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) { 488 drm_notice(&i915->drm, 489 "RC6 and powersaving disabled by BIOS\n"); 490 return false; 491 } 492 493 return true; 494 } 495 496 static void rpm_get(struct intel_rc6 *rc6) 497 { 498 GEM_BUG_ON(rc6->wakeref); 499 pm_runtime_get_sync(rc6_to_i915(rc6)->drm.dev); 500 rc6->wakeref = true; 501 } 502 503 static void rpm_put(struct intel_rc6 *rc6) 504 { 505 GEM_BUG_ON(!rc6->wakeref); 506 pm_runtime_put(rc6_to_i915(rc6)->drm.dev); 507 rc6->wakeref = false; 508 } 509 510 static bool pctx_corrupted(struct intel_rc6 *rc6) 511 { 512 struct drm_i915_private *i915 = rc6_to_i915(rc6); 513 514 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 515 return false; 516 517 if (intel_uncore_read(rc6_to_uncore(rc6), GEN8_RC6_CTX_INFO)) 518 return false; 519 520 drm_notice(&i915->drm, 521 "RC6 context corruption, disabling runtime power management\n"); 522 return true; 523 } 524 525 static void __intel_rc6_disable(struct intel_rc6 *rc6) 526 { 527 struct drm_i915_private *i915 = rc6_to_i915(rc6); 528 struct intel_uncore *uncore = rc6_to_uncore(rc6); 529 struct intel_gt *gt = rc6_to_gt(rc6); 530 531 /* Take control of RC6 back from GuC */ 532 intel_guc_rc_disable(>->uc.guc); 533 534 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 535 if (GRAPHICS_VER(i915) >= 9) 536 set(uncore, GEN9_PG_ENABLE, 0); 537 set(uncore, GEN6_RC_CONTROL, 0); 538 set(uncore, GEN6_RC_STATE, 0); 539 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 540 } 541 542 void intel_rc6_init(struct intel_rc6 *rc6) 543 { 544 struct drm_i915_private *i915 = rc6_to_i915(rc6); 545 int err; 546 547 /* Disable runtime-pm until we can save the GPU state with rc6 pctx */ 548 rpm_get(rc6); 549 550 if (!rc6_supported(rc6)) 551 return; 552 553 if (IS_CHERRYVIEW(i915)) 554 err = chv_rc6_init(rc6); 555 else if (IS_VALLEYVIEW(i915)) 556 err = vlv_rc6_init(rc6); 557 else 558 err = 0; 559 560 /* Sanitize rc6, ensure it is disabled before we are ready. */ 561 __intel_rc6_disable(rc6); 562 563 rc6->supported = err == 0; 564 } 565 566 void intel_rc6_sanitize(struct intel_rc6 *rc6) 567 { 568 memset(rc6->prev_hw_residency, 0, sizeof(rc6->prev_hw_residency)); 569 570 if (rc6->enabled) { /* unbalanced suspend/resume */ 571 rpm_get(rc6); 572 rc6->enabled = false; 573 } 574 575 if (rc6->supported) 576 __intel_rc6_disable(rc6); 577 } 578 579 void intel_rc6_enable(struct intel_rc6 *rc6) 580 { 581 struct drm_i915_private *i915 = rc6_to_i915(rc6); 582 struct intel_uncore *uncore = rc6_to_uncore(rc6); 583 584 if (!rc6->supported) 585 return; 586 587 GEM_BUG_ON(rc6->enabled); 588 589 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 590 591 if (IS_CHERRYVIEW(i915)) 592 chv_rc6_enable(rc6); 593 else if (IS_VALLEYVIEW(i915)) 594 vlv_rc6_enable(rc6); 595 else if (GRAPHICS_VER(i915) >= 11) 596 gen11_rc6_enable(rc6); 597 else if (GRAPHICS_VER(i915) >= 9) 598 gen9_rc6_enable(rc6); 599 else if (IS_BROADWELL(i915)) 600 gen8_rc6_enable(rc6); 601 else if (GRAPHICS_VER(i915) >= 6) 602 gen6_rc6_enable(rc6); 603 604 rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE; 605 if (NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 606 rc6->ctl_enable = 0; 607 608 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 609 610 if (unlikely(pctx_corrupted(rc6))) 611 return; 612 613 /* rc6 is ready, runtime-pm is go! */ 614 rpm_put(rc6); 615 rc6->enabled = true; 616 } 617 618 void intel_rc6_unpark(struct intel_rc6 *rc6) 619 { 620 struct intel_uncore *uncore = rc6_to_uncore(rc6); 621 622 if (!rc6->enabled) 623 return; 624 625 /* Restore HW timers for automatic RC6 entry while busy */ 626 set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable); 627 } 628 629 void intel_rc6_park(struct intel_rc6 *rc6) 630 { 631 struct intel_uncore *uncore = rc6_to_uncore(rc6); 632 unsigned int target; 633 634 if (!rc6->enabled) 635 return; 636 637 if (unlikely(pctx_corrupted(rc6))) { 638 intel_rc6_disable(rc6); 639 return; 640 } 641 642 if (!rc6->manual) 643 return; 644 645 /* Turn off the HW timers and go directly to rc6 */ 646 set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE); 647 648 if (HAS_RC6pp(rc6_to_i915(rc6))) 649 target = 0x6; /* deepest rc6 */ 650 else if (HAS_RC6p(rc6_to_i915(rc6))) 651 target = 0x5; /* deep rc6 */ 652 else 653 target = 0x4; /* normal rc6 */ 654 set(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT); 655 } 656 657 void intel_rc6_disable(struct intel_rc6 *rc6) 658 { 659 if (!rc6->enabled) 660 return; 661 662 rpm_get(rc6); 663 rc6->enabled = false; 664 665 __intel_rc6_disable(rc6); 666 } 667 668 void intel_rc6_fini(struct intel_rc6 *rc6) 669 { 670 struct drm_i915_gem_object *pctx; 671 672 intel_rc6_disable(rc6); 673 674 pctx = fetch_and_zero(&rc6->pctx); 675 if (pctx) 676 i915_gem_object_put(pctx); 677 678 if (rc6->wakeref) 679 rpm_put(rc6); 680 } 681 682 static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg) 683 { 684 u32 lower, upper, tmp; 685 int loop = 2; 686 687 /* 688 * The register accessed do not need forcewake. We borrow 689 * uncore lock to prevent concurrent access to range reg. 690 */ 691 lockdep_assert_held(&uncore->lock); 692 693 /* 694 * vlv and chv residency counters are 40 bits in width. 695 * With a control bit, we can choose between upper or lower 696 * 32bit window into this counter. 697 * 698 * Although we always use the counter in high-range mode elsewhere, 699 * userspace may attempt to read the value before rc6 is initialised, 700 * before we have set the default VLV_COUNTER_CONTROL value. So always 701 * set the high bit to be safe. 702 */ 703 set(uncore, VLV_COUNTER_CONTROL, 704 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); 705 upper = intel_uncore_read_fw(uncore, reg); 706 do { 707 tmp = upper; 708 709 set(uncore, VLV_COUNTER_CONTROL, 710 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); 711 lower = intel_uncore_read_fw(uncore, reg); 712 713 set(uncore, VLV_COUNTER_CONTROL, 714 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); 715 upper = intel_uncore_read_fw(uncore, reg); 716 } while (upper != tmp && --loop); 717 718 /* 719 * Everywhere else we always use VLV_COUNTER_CONTROL with the 720 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set 721 * now. 722 */ 723 724 return lower | (u64)upper << 8; 725 } 726 727 u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) 728 { 729 struct drm_i915_private *i915 = rc6_to_i915(rc6); 730 struct intel_uncore *uncore = rc6_to_uncore(rc6); 731 u64 time_hw, prev_hw, overflow_hw; 732 unsigned int fw_domains; 733 unsigned long flags; 734 unsigned int i; 735 u32 mul, div; 736 737 if (!rc6->supported) 738 return 0; 739 740 /* 741 * Store previous hw counter values for counter wrap-around handling. 742 * 743 * There are only four interesting registers and they live next to each 744 * other so we can use the relative address, compared to the smallest 745 * one as the index into driver storage. 746 */ 747 i = (i915_mmio_reg_offset(reg) - 748 i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32); 749 if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency))) 750 return 0; 751 752 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); 753 754 spin_lock_irqsave(&uncore->lock, flags); 755 intel_uncore_forcewake_get__locked(uncore, fw_domains); 756 757 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ 758 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 759 mul = 1000000; 760 div = i915->czclk_freq; 761 overflow_hw = BIT_ULL(40); 762 time_hw = vlv_residency_raw(uncore, reg); 763 } else { 764 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */ 765 if (IS_GEN9_LP(i915)) { 766 mul = 10000; 767 div = 12; 768 } else { 769 mul = 1280; 770 div = 1; 771 } 772 773 overflow_hw = BIT_ULL(32); 774 time_hw = intel_uncore_read_fw(uncore, reg); 775 } 776 777 /* 778 * Counter wrap handling. 779 * 780 * But relying on a sufficient frequency of queries otherwise counters 781 * can still wrap. 782 */ 783 prev_hw = rc6->prev_hw_residency[i]; 784 rc6->prev_hw_residency[i] = time_hw; 785 786 /* RC6 delta from last sample. */ 787 if (time_hw >= prev_hw) 788 time_hw -= prev_hw; 789 else 790 time_hw += overflow_hw - prev_hw; 791 792 /* Add delta to RC6 extended raw driver copy. */ 793 time_hw += rc6->cur_residency[i]; 794 rc6->cur_residency[i] = time_hw; 795 796 intel_uncore_forcewake_put__locked(uncore, fw_domains); 797 spin_unlock_irqrestore(&uncore->lock, flags); 798 799 return mul_u64_u32_div(time_hw, mul, div); 800 } 801 802 u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg) 803 { 804 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000); 805 } 806 807 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 808 #include "selftest_rc6.c" 809 #endif 810