1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/pm_runtime.h> 7 8 #include "i915_drv.h" 9 #include "i915_vgpu.h" 10 #include "intel_gt.h" 11 #include "intel_gt_pm.h" 12 #include "intel_pcode.h" 13 #include "intel_rc6.h" 14 15 /** 16 * DOC: RC6 17 * 18 * RC6 is a special power stage which allows the GPU to enter an very 19 * low-voltage mode when idle, using down to 0V while at this stage. This 20 * stage is entered automatically when the GPU is idle when RC6 support is 21 * enabled, and as soon as new workload arises GPU wakes up automatically as 22 * well. 23 * 24 * There are different RC6 modes available in Intel GPU, which differentiate 25 * among each other with the latency required to enter and leave RC6 and 26 * voltage consumed by the GPU in different states. 27 * 28 * The combination of the following flags define which states GPU is allowed 29 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 30 * RC6pp is deepest RC6. Their support by hardware varies according to the 31 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 32 * which brings the most power savings; deeper states save more power, but 33 * require higher latency to switch to and wake up. 34 */ 35 36 static struct intel_gt *rc6_to_gt(struct intel_rc6 *rc6) 37 { 38 return container_of(rc6, struct intel_gt, rc6); 39 } 40 41 static struct intel_uncore *rc6_to_uncore(struct intel_rc6 *rc) 42 { 43 return rc6_to_gt(rc)->uncore; 44 } 45 46 static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc) 47 { 48 return rc6_to_gt(rc)->i915; 49 } 50 51 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) 52 { 53 intel_uncore_write_fw(uncore, reg, val); 54 } 55 56 static void gen11_rc6_enable(struct intel_rc6 *rc6) 57 { 58 struct intel_gt *gt = rc6_to_gt(rc6); 59 struct intel_uncore *uncore = gt->uncore; 60 struct intel_engine_cs *engine; 61 enum intel_engine_id id; 62 u32 pg_enable; 63 int i; 64 65 /* 66 * With GuCRC, these parameters are set by GuC 67 */ 68 if (!intel_uc_uses_guc_rc(>->uc)) { 69 /* 2b: Program RC6 thresholds.*/ 70 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); 71 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); 72 73 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 74 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 75 for_each_engine(engine, rc6_to_gt(rc6), id) 76 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 77 78 set(uncore, GUC_MAX_IDLE_COUNT, 0xA); 79 80 set(uncore, GEN6_RC_SLEEP, 0); 81 82 set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 83 } 84 85 /* 86 * 2c: Program Coarse Power Gating Policies. 87 * 88 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we 89 * use instead is a more conservative estimate for the maximum time 90 * it takes us to service a CS interrupt and submit a new ELSP - that 91 * is the time which the GPU is idle waiting for the CPU to select the 92 * next request to execute. If the idle hysteresis is less than that 93 * interrupt service latency, the hardware will automatically gate 94 * the power well and we will then incur the wake up cost on top of 95 * the service latency. A similar guide from plane_state is that we 96 * do not want the enable hysteresis to less than the wakeup latency. 97 * 98 * igt/gem_exec_nop/sequential provides a rough estimate for the 99 * service latency, and puts it under 10us for Icelake, similar to 100 * Broadwell+, To be conservative, we want to factor in a context 101 * switch on top (due to ksoftirqd). 102 */ 103 set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60); 104 set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60); 105 106 /* 3a: Enable RC6 107 * 108 * With GuCRC, we do not enable bit 31 of RC_CTL, 109 * thus allowing GuC to control RC6 entry/exit fully instead. 110 * We will not set the HW ENABLE and EI bits 111 */ 112 if (!intel_guc_rc_enable(>->uc.guc)) 113 rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE; 114 else 115 rc6->ctl_enable = 116 GEN6_RC_CTL_HW_ENABLE | 117 GEN6_RC_CTL_RC6_ENABLE | 118 GEN6_RC_CTL_EI_MODE(1); 119 120 /* Wa_16011777198 - Render powergating must remain disabled */ 121 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || 122 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) 123 pg_enable = 124 GEN9_MEDIA_PG_ENABLE | 125 GEN11_MEDIA_SAMPLER_PG_ENABLE; 126 else 127 pg_enable = 128 GEN9_RENDER_PG_ENABLE | 129 GEN9_MEDIA_PG_ENABLE | 130 GEN11_MEDIA_SAMPLER_PG_ENABLE; 131 132 if (GRAPHICS_VER(gt->i915) >= 12) { 133 for (i = 0; i < I915_MAX_VCS; i++) 134 if (HAS_ENGINE(gt, _VCS(i))) 135 pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) | 136 VDN_MFX_POWERGATE_ENABLE(i)); 137 } 138 139 set(uncore, GEN9_PG_ENABLE, pg_enable); 140 } 141 142 static void gen9_rc6_enable(struct intel_rc6 *rc6) 143 { 144 struct intel_uncore *uncore = rc6_to_uncore(rc6); 145 struct intel_engine_cs *engine; 146 enum intel_engine_id id; 147 148 /* 2b: Program RC6 thresholds.*/ 149 if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) { 150 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); 151 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); 152 } else if (IS_SKYLAKE(rc6_to_i915(rc6))) { 153 /* 154 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only 155 * when CPG is enabled 156 */ 157 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); 158 } else { 159 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); 160 } 161 162 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 163 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 164 for_each_engine(engine, rc6_to_gt(rc6), id) 165 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 166 167 set(uncore, GUC_MAX_IDLE_COUNT, 0xA); 168 169 set(uncore, GEN6_RC_SLEEP, 0); 170 171 /* 172 * 2c: Program Coarse Power Gating Policies. 173 * 174 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we 175 * use instead is a more conservative estimate for the maximum time 176 * it takes us to service a CS interrupt and submit a new ELSP - that 177 * is the time which the GPU is idle waiting for the CPU to select the 178 * next request to execute. If the idle hysteresis is less than that 179 * interrupt service latency, the hardware will automatically gate 180 * the power well and we will then incur the wake up cost on top of 181 * the service latency. A similar guide from plane_state is that we 182 * do not want the enable hysteresis to less than the wakeup latency. 183 * 184 * igt/gem_exec_nop/sequential provides a rough estimate for the 185 * service latency, and puts it around 10us for Broadwell (and other 186 * big core) and around 40us for Broxton (and other low power cores). 187 * [Note that for legacy ringbuffer submission, this is less than 1us!] 188 * However, the wakeup latency on Broxton is closer to 100us. To be 189 * conservative, we have to factor in a context switch on top (due 190 * to ksoftirqd). 191 */ 192 set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250); 193 set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250); 194 195 /* 3a: Enable RC6 */ 196 set(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ 197 198 rc6->ctl_enable = 199 GEN6_RC_CTL_HW_ENABLE | 200 GEN6_RC_CTL_RC6_ENABLE | 201 GEN6_RC_CTL_EI_MODE(1); 202 203 /* 204 * WaRsDisableCoarsePowerGating:skl,cnl 205 * - Render/Media PG need to be disabled with RC6. 206 */ 207 if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6))) 208 set(uncore, GEN9_PG_ENABLE, 209 GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE); 210 } 211 212 static void gen8_rc6_enable(struct intel_rc6 *rc6) 213 { 214 struct intel_uncore *uncore = rc6_to_uncore(rc6); 215 struct intel_engine_cs *engine; 216 enum intel_engine_id id; 217 218 /* 2b: Program RC6 thresholds.*/ 219 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 220 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 221 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 222 for_each_engine(engine, rc6_to_gt(rc6), id) 223 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 224 set(uncore, GEN6_RC_SLEEP, 0); 225 set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ 226 227 /* 3: Enable RC6 */ 228 rc6->ctl_enable = 229 GEN6_RC_CTL_HW_ENABLE | 230 GEN7_RC_CTL_TO_MODE | 231 GEN6_RC_CTL_RC6_ENABLE; 232 } 233 234 static void gen6_rc6_enable(struct intel_rc6 *rc6) 235 { 236 struct intel_uncore *uncore = rc6_to_uncore(rc6); 237 struct drm_i915_private *i915 = rc6_to_i915(rc6); 238 struct intel_engine_cs *engine; 239 enum intel_engine_id id; 240 u32 rc6vids, rc6_mask; 241 int ret; 242 243 set(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 244 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 245 set(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 246 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); 247 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); 248 249 for_each_engine(engine, rc6_to_gt(rc6), id) 250 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 251 252 set(uncore, GEN6_RC_SLEEP, 0); 253 set(uncore, GEN6_RC1e_THRESHOLD, 1000); 254 set(uncore, GEN6_RC6_THRESHOLD, 50000); 255 set(uncore, GEN6_RC6p_THRESHOLD, 150000); 256 set(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 257 258 /* We don't use those on Haswell */ 259 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 260 if (HAS_RC6p(i915)) 261 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 262 if (HAS_RC6pp(i915)) 263 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 264 rc6->ctl_enable = 265 rc6_mask | 266 GEN6_RC_CTL_EI_MODE(1) | 267 GEN6_RC_CTL_HW_ENABLE; 268 269 rc6vids = 0; 270 ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, 271 &rc6vids, NULL); 272 if (GRAPHICS_VER(i915) == 6 && ret) { 273 drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n"); 274 } else if (GRAPHICS_VER(i915) == 6 && 275 (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 276 drm_dbg(&i915->drm, 277 "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 278 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 279 rc6vids &= 0xffff00; 280 rc6vids |= GEN6_ENCODE_RC6_VID(450); 281 ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 282 if (ret) 283 drm_err(&i915->drm, 284 "Couldn't fix incorrect rc6 voltage\n"); 285 } 286 } 287 288 /* Check that the pcbr address is not empty. */ 289 static int chv_rc6_init(struct intel_rc6 *rc6) 290 { 291 struct intel_uncore *uncore = rc6_to_uncore(rc6); 292 struct drm_i915_private *i915 = rc6_to_i915(rc6); 293 resource_size_t pctx_paddr, paddr; 294 resource_size_t pctx_size = 32 * SZ_1K; 295 u32 pcbr; 296 297 pcbr = intel_uncore_read(uncore, VLV_PCBR); 298 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { 299 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); 300 paddr = i915->dsm.end + 1 - pctx_size; 301 GEM_BUG_ON(paddr > U32_MAX); 302 303 pctx_paddr = (paddr & ~4095); 304 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr); 305 } 306 307 return 0; 308 } 309 310 static int vlv_rc6_init(struct intel_rc6 *rc6) 311 { 312 struct drm_i915_private *i915 = rc6_to_i915(rc6); 313 struct intel_uncore *uncore = rc6_to_uncore(rc6); 314 struct drm_i915_gem_object *pctx; 315 resource_size_t pctx_paddr; 316 resource_size_t pctx_size = 24 * SZ_1K; 317 u32 pcbr; 318 319 pcbr = intel_uncore_read(uncore, VLV_PCBR); 320 if (pcbr) { 321 /* BIOS set it up already, grab the pre-alloc'd space */ 322 resource_size_t pcbr_offset; 323 324 pcbr_offset = (pcbr & ~4095) - i915->dsm.start; 325 pctx = i915_gem_object_create_stolen_for_preallocated(i915, 326 pcbr_offset, 327 pctx_size); 328 if (IS_ERR(pctx)) 329 return PTR_ERR(pctx); 330 331 goto out; 332 } 333 334 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); 335 336 /* 337 * From the Gunit register HAS: 338 * The Gfx driver is expected to program this register and ensure 339 * proper allocation within Gfx stolen memory. For example, this 340 * register should be programmed such than the PCBR range does not 341 * overlap with other ranges, such as the frame buffer, protected 342 * memory, or any other relevant ranges. 343 */ 344 pctx = i915_gem_object_create_stolen(i915, pctx_size); 345 if (IS_ERR(pctx)) { 346 drm_dbg(&i915->drm, 347 "not enough stolen space for PCTX, disabling\n"); 348 return PTR_ERR(pctx); 349 } 350 351 GEM_BUG_ON(range_overflows_end_t(u64, 352 i915->dsm.start, 353 pctx->stolen->start, 354 U32_MAX)); 355 pctx_paddr = i915->dsm.start + pctx->stolen->start; 356 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr); 357 358 out: 359 rc6->pctx = pctx; 360 return 0; 361 } 362 363 static void chv_rc6_enable(struct intel_rc6 *rc6) 364 { 365 struct intel_uncore *uncore = rc6_to_uncore(rc6); 366 struct intel_engine_cs *engine; 367 enum intel_engine_id id; 368 369 /* 2a: Program RC6 thresholds.*/ 370 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 371 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 372 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 373 374 for_each_engine(engine, rc6_to_gt(rc6), id) 375 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 376 set(uncore, GEN6_RC_SLEEP, 0); 377 378 /* TO threshold set to 500 us (0x186 * 1.28 us) */ 379 set(uncore, GEN6_RC6_THRESHOLD, 0x186); 380 381 /* Allows RC6 residency counter to work */ 382 set(uncore, VLV_COUNTER_CONTROL, 383 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 384 VLV_MEDIA_RC6_COUNT_EN | 385 VLV_RENDER_RC6_COUNT_EN)); 386 387 /* 3: Enable RC6 */ 388 rc6->ctl_enable = GEN7_RC_CTL_TO_MODE; 389 } 390 391 static void vlv_rc6_enable(struct intel_rc6 *rc6) 392 { 393 struct intel_uncore *uncore = rc6_to_uncore(rc6); 394 struct intel_engine_cs *engine; 395 enum intel_engine_id id; 396 397 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); 398 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); 399 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); 400 401 for_each_engine(engine, rc6_to_gt(rc6), id) 402 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 403 404 set(uncore, GEN6_RC6_THRESHOLD, 0x557); 405 406 /* Allows RC6 residency counter to work */ 407 set(uncore, VLV_COUNTER_CONTROL, 408 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 409 VLV_MEDIA_RC0_COUNT_EN | 410 VLV_RENDER_RC0_COUNT_EN | 411 VLV_MEDIA_RC6_COUNT_EN | 412 VLV_RENDER_RC6_COUNT_EN)); 413 414 rc6->ctl_enable = 415 GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; 416 } 417 418 static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6) 419 { 420 struct intel_uncore *uncore = rc6_to_uncore(rc6); 421 struct drm_i915_private *i915 = rc6_to_i915(rc6); 422 u32 rc6_ctx_base, rc_ctl, rc_sw_target; 423 bool enable_rc6 = true; 424 425 rc_ctl = intel_uncore_read(uncore, GEN6_RC_CONTROL); 426 rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE); 427 rc_sw_target &= RC_SW_TARGET_STATE_MASK; 428 rc_sw_target >>= RC_SW_TARGET_STATE_SHIFT; 429 drm_dbg(&i915->drm, "BIOS enabled RC states: " 430 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n", 431 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE), 432 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE), 433 rc_sw_target); 434 435 if (!(intel_uncore_read(uncore, RC6_LOCATION) & RC6_CTX_IN_DRAM)) { 436 drm_dbg(&i915->drm, "RC6 Base location not set properly.\n"); 437 enable_rc6 = false; 438 } 439 440 /* 441 * The exact context size is not known for BXT, so assume a page size 442 * for this check. 443 */ 444 rc6_ctx_base = 445 intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK; 446 if (!(rc6_ctx_base >= i915->dsm_reserved.start && 447 rc6_ctx_base + PAGE_SIZE < i915->dsm_reserved.end)) { 448 drm_dbg(&i915->drm, "RC6 Base address not as expected.\n"); 449 enable_rc6 = false; 450 } 451 452 if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 && 453 (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 && 454 (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 && 455 (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) { 456 drm_dbg(&i915->drm, 457 "Engine Idle wait time not set properly.\n"); 458 enable_rc6 = false; 459 } 460 461 if (!intel_uncore_read(uncore, GEN8_PUSHBUS_CONTROL) || 462 !intel_uncore_read(uncore, GEN8_PUSHBUS_ENABLE) || 463 !intel_uncore_read(uncore, GEN8_PUSHBUS_SHIFT)) { 464 drm_dbg(&i915->drm, "Pushbus not setup properly.\n"); 465 enable_rc6 = false; 466 } 467 468 if (!intel_uncore_read(uncore, GEN6_GFXPAUSE)) { 469 drm_dbg(&i915->drm, "GFX pause not setup properly.\n"); 470 enable_rc6 = false; 471 } 472 473 if (!intel_uncore_read(uncore, GEN8_MISC_CTRL0)) { 474 drm_dbg(&i915->drm, "GPM control not setup properly.\n"); 475 enable_rc6 = false; 476 } 477 478 return enable_rc6; 479 } 480 481 static bool rc6_supported(struct intel_rc6 *rc6) 482 { 483 struct drm_i915_private *i915 = rc6_to_i915(rc6); 484 485 if (!HAS_RC6(i915)) 486 return false; 487 488 if (intel_vgpu_active(i915)) 489 return false; 490 491 if (is_mock_gt(rc6_to_gt(rc6))) 492 return false; 493 494 if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) { 495 drm_notice(&i915->drm, 496 "RC6 and powersaving disabled by BIOS\n"); 497 return false; 498 } 499 500 return true; 501 } 502 503 static void rpm_get(struct intel_rc6 *rc6) 504 { 505 GEM_BUG_ON(rc6->wakeref); 506 pm_runtime_get_sync(rc6_to_i915(rc6)->drm.dev); 507 rc6->wakeref = true; 508 } 509 510 static void rpm_put(struct intel_rc6 *rc6) 511 { 512 GEM_BUG_ON(!rc6->wakeref); 513 pm_runtime_put(rc6_to_i915(rc6)->drm.dev); 514 rc6->wakeref = false; 515 } 516 517 static bool pctx_corrupted(struct intel_rc6 *rc6) 518 { 519 struct drm_i915_private *i915 = rc6_to_i915(rc6); 520 521 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 522 return false; 523 524 if (intel_uncore_read(rc6_to_uncore(rc6), GEN8_RC6_CTX_INFO)) 525 return false; 526 527 drm_notice(&i915->drm, 528 "RC6 context corruption, disabling runtime power management\n"); 529 return true; 530 } 531 532 static void __intel_rc6_disable(struct intel_rc6 *rc6) 533 { 534 struct drm_i915_private *i915 = rc6_to_i915(rc6); 535 struct intel_uncore *uncore = rc6_to_uncore(rc6); 536 struct intel_gt *gt = rc6_to_gt(rc6); 537 538 /* Take control of RC6 back from GuC */ 539 intel_guc_rc_disable(>->uc.guc); 540 541 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 542 if (GRAPHICS_VER(i915) >= 9) 543 set(uncore, GEN9_PG_ENABLE, 0); 544 set(uncore, GEN6_RC_CONTROL, 0); 545 set(uncore, GEN6_RC_STATE, 0); 546 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 547 } 548 549 void intel_rc6_init(struct intel_rc6 *rc6) 550 { 551 struct drm_i915_private *i915 = rc6_to_i915(rc6); 552 int err; 553 554 /* Disable runtime-pm until we can save the GPU state with rc6 pctx */ 555 rpm_get(rc6); 556 557 if (!rc6_supported(rc6)) 558 return; 559 560 if (IS_CHERRYVIEW(i915)) 561 err = chv_rc6_init(rc6); 562 else if (IS_VALLEYVIEW(i915)) 563 err = vlv_rc6_init(rc6); 564 else 565 err = 0; 566 567 /* Sanitize rc6, ensure it is disabled before we are ready. */ 568 __intel_rc6_disable(rc6); 569 570 rc6->supported = err == 0; 571 } 572 573 void intel_rc6_sanitize(struct intel_rc6 *rc6) 574 { 575 memset(rc6->prev_hw_residency, 0, sizeof(rc6->prev_hw_residency)); 576 577 if (rc6->enabled) { /* unbalanced suspend/resume */ 578 rpm_get(rc6); 579 rc6->enabled = false; 580 } 581 582 if (rc6->supported) 583 __intel_rc6_disable(rc6); 584 } 585 586 void intel_rc6_enable(struct intel_rc6 *rc6) 587 { 588 struct drm_i915_private *i915 = rc6_to_i915(rc6); 589 struct intel_uncore *uncore = rc6_to_uncore(rc6); 590 591 if (!rc6->supported) 592 return; 593 594 GEM_BUG_ON(rc6->enabled); 595 596 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 597 598 if (IS_CHERRYVIEW(i915)) 599 chv_rc6_enable(rc6); 600 else if (IS_VALLEYVIEW(i915)) 601 vlv_rc6_enable(rc6); 602 else if (GRAPHICS_VER(i915) >= 11) 603 gen11_rc6_enable(rc6); 604 else if (GRAPHICS_VER(i915) >= 9) 605 gen9_rc6_enable(rc6); 606 else if (IS_BROADWELL(i915)) 607 gen8_rc6_enable(rc6); 608 else if (GRAPHICS_VER(i915) >= 6) 609 gen6_rc6_enable(rc6); 610 611 rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE; 612 if (NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 613 rc6->ctl_enable = 0; 614 615 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 616 617 if (unlikely(pctx_corrupted(rc6))) 618 return; 619 620 /* rc6 is ready, runtime-pm is go! */ 621 rpm_put(rc6); 622 rc6->enabled = true; 623 } 624 625 void intel_rc6_unpark(struct intel_rc6 *rc6) 626 { 627 struct intel_uncore *uncore = rc6_to_uncore(rc6); 628 629 if (!rc6->enabled) 630 return; 631 632 /* Restore HW timers for automatic RC6 entry while busy */ 633 set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable); 634 } 635 636 void intel_rc6_park(struct intel_rc6 *rc6) 637 { 638 struct intel_uncore *uncore = rc6_to_uncore(rc6); 639 unsigned int target; 640 641 if (!rc6->enabled) 642 return; 643 644 if (unlikely(pctx_corrupted(rc6))) { 645 intel_rc6_disable(rc6); 646 return; 647 } 648 649 if (!rc6->manual) 650 return; 651 652 /* Turn off the HW timers and go directly to rc6 */ 653 set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE); 654 655 if (HAS_RC6pp(rc6_to_i915(rc6))) 656 target = 0x6; /* deepest rc6 */ 657 else if (HAS_RC6p(rc6_to_i915(rc6))) 658 target = 0x5; /* deep rc6 */ 659 else 660 target = 0x4; /* normal rc6 */ 661 set(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT); 662 } 663 664 void intel_rc6_disable(struct intel_rc6 *rc6) 665 { 666 if (!rc6->enabled) 667 return; 668 669 rpm_get(rc6); 670 rc6->enabled = false; 671 672 __intel_rc6_disable(rc6); 673 } 674 675 void intel_rc6_fini(struct intel_rc6 *rc6) 676 { 677 struct drm_i915_gem_object *pctx; 678 679 intel_rc6_disable(rc6); 680 681 pctx = fetch_and_zero(&rc6->pctx); 682 if (pctx) 683 i915_gem_object_put(pctx); 684 685 if (rc6->wakeref) 686 rpm_put(rc6); 687 } 688 689 static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg) 690 { 691 u32 lower, upper, tmp; 692 int loop = 2; 693 694 /* 695 * The register accessed do not need forcewake. We borrow 696 * uncore lock to prevent concurrent access to range reg. 697 */ 698 lockdep_assert_held(&uncore->lock); 699 700 /* 701 * vlv and chv residency counters are 40 bits in width. 702 * With a control bit, we can choose between upper or lower 703 * 32bit window into this counter. 704 * 705 * Although we always use the counter in high-range mode elsewhere, 706 * userspace may attempt to read the value before rc6 is initialised, 707 * before we have set the default VLV_COUNTER_CONTROL value. So always 708 * set the high bit to be safe. 709 */ 710 set(uncore, VLV_COUNTER_CONTROL, 711 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); 712 upper = intel_uncore_read_fw(uncore, reg); 713 do { 714 tmp = upper; 715 716 set(uncore, VLV_COUNTER_CONTROL, 717 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); 718 lower = intel_uncore_read_fw(uncore, reg); 719 720 set(uncore, VLV_COUNTER_CONTROL, 721 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); 722 upper = intel_uncore_read_fw(uncore, reg); 723 } while (upper != tmp && --loop); 724 725 /* 726 * Everywhere else we always use VLV_COUNTER_CONTROL with the 727 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set 728 * now. 729 */ 730 731 return lower | (u64)upper << 8; 732 } 733 734 u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) 735 { 736 struct drm_i915_private *i915 = rc6_to_i915(rc6); 737 struct intel_uncore *uncore = rc6_to_uncore(rc6); 738 u64 time_hw, prev_hw, overflow_hw; 739 unsigned int fw_domains; 740 unsigned long flags; 741 unsigned int i; 742 u32 mul, div; 743 744 if (!rc6->supported) 745 return 0; 746 747 /* 748 * Store previous hw counter values for counter wrap-around handling. 749 * 750 * There are only four interesting registers and they live next to each 751 * other so we can use the relative address, compared to the smallest 752 * one as the index into driver storage. 753 */ 754 i = (i915_mmio_reg_offset(reg) - 755 i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32); 756 if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency))) 757 return 0; 758 759 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); 760 761 spin_lock_irqsave(&uncore->lock, flags); 762 intel_uncore_forcewake_get__locked(uncore, fw_domains); 763 764 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ 765 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 766 mul = 1000000; 767 div = i915->czclk_freq; 768 overflow_hw = BIT_ULL(40); 769 time_hw = vlv_residency_raw(uncore, reg); 770 } else { 771 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */ 772 if (IS_GEN9_LP(i915)) { 773 mul = 10000; 774 div = 12; 775 } else { 776 mul = 1280; 777 div = 1; 778 } 779 780 overflow_hw = BIT_ULL(32); 781 time_hw = intel_uncore_read_fw(uncore, reg); 782 } 783 784 /* 785 * Counter wrap handling. 786 * 787 * But relying on a sufficient frequency of queries otherwise counters 788 * can still wrap. 789 */ 790 prev_hw = rc6->prev_hw_residency[i]; 791 rc6->prev_hw_residency[i] = time_hw; 792 793 /* RC6 delta from last sample. */ 794 if (time_hw >= prev_hw) 795 time_hw -= prev_hw; 796 else 797 time_hw += overflow_hw - prev_hw; 798 799 /* Add delta to RC6 extended raw driver copy. */ 800 time_hw += rc6->cur_residency[i]; 801 rc6->cur_residency[i] = time_hw; 802 803 intel_uncore_forcewake_put__locked(uncore, fw_domains); 804 spin_unlock_irqrestore(&uncore->lock, flags); 805 806 return mul_u64_u32_div(time_hw, mul, div); 807 } 808 809 u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg) 810 { 811 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000); 812 } 813 814 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 815 #include "selftest_rc6.c" 816 #endif 817