1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/pm_runtime.h> 7 #include <linux/string_helpers.h> 8 9 #include "gem/i915_gem_region.h" 10 #include "i915_drv.h" 11 #include "i915_reg.h" 12 #include "i915_vgpu.h" 13 #include "intel_engine_regs.h" 14 #include "intel_gt.h" 15 #include "intel_gt_pm.h" 16 #include "intel_gt_regs.h" 17 #include "intel_pcode.h" 18 #include "intel_rc6.h" 19 20 /** 21 * DOC: RC6 22 * 23 * RC6 is a special power stage which allows the GPU to enter an very 24 * low-voltage mode when idle, using down to 0V while at this stage. This 25 * stage is entered automatically when the GPU is idle when RC6 support is 26 * enabled, and as soon as new workload arises GPU wakes up automatically as 27 * well. 28 * 29 * There are different RC6 modes available in Intel GPU, which differentiate 30 * among each other with the latency required to enter and leave RC6 and 31 * voltage consumed by the GPU in different states. 32 * 33 * The combination of the following flags define which states GPU is allowed 34 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 35 * RC6pp is deepest RC6. Their support by hardware varies according to the 36 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 37 * which brings the most power savings; deeper states save more power, but 38 * require higher latency to switch to and wake up. 39 */ 40 41 static struct intel_gt *rc6_to_gt(struct intel_rc6 *rc6) 42 { 43 return container_of(rc6, struct intel_gt, rc6); 44 } 45 46 static struct intel_uncore *rc6_to_uncore(struct intel_rc6 *rc) 47 { 48 return rc6_to_gt(rc)->uncore; 49 } 50 51 static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc) 52 { 53 return rc6_to_gt(rc)->i915; 54 } 55 56 static void gen11_rc6_enable(struct intel_rc6 *rc6) 57 { 58 struct intel_gt *gt = rc6_to_gt(rc6); 59 struct intel_uncore *uncore = gt->uncore; 60 struct intel_engine_cs *engine; 61 enum intel_engine_id id; 62 u32 pg_enable; 63 int i; 64 65 /* 66 * With GuCRC, these parameters are set by GuC 67 */ 68 if (!intel_uc_uses_guc_rc(>->uc)) { 69 /* 2b: Program RC6 thresholds.*/ 70 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); 71 intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); 72 73 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 74 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 75 for_each_engine(engine, rc6_to_gt(rc6), id) 76 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 77 78 intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA); 79 80 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); 81 82 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 83 } 84 85 /* 86 * 2c: Program Coarse Power Gating Policies. 87 * 88 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we 89 * use instead is a more conservative estimate for the maximum time 90 * it takes us to service a CS interrupt and submit a new ELSP - that 91 * is the time which the GPU is idle waiting for the CPU to select the 92 * next request to execute. If the idle hysteresis is less than that 93 * interrupt service latency, the hardware will automatically gate 94 * the power well and we will then incur the wake up cost on top of 95 * the service latency. A similar guide from plane_state is that we 96 * do not want the enable hysteresis to less than the wakeup latency. 97 * 98 * igt/gem_exec_nop/sequential provides a rough estimate for the 99 * service latency, and puts it under 10us for Icelake, similar to 100 * Broadwell+, To be conservative, we want to factor in a context 101 * switch on top (due to ksoftirqd). 102 */ 103 intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60); 104 intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60); 105 106 /* 3a: Enable RC6 107 * 108 * With GuCRC, we do not enable bit 31 of RC_CTL, 109 * thus allowing GuC to control RC6 entry/exit fully instead. 110 * We will not set the HW ENABLE and EI bits 111 */ 112 if (!intel_guc_rc_enable(>->uc.guc)) 113 rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE; 114 else 115 rc6->ctl_enable = 116 GEN6_RC_CTL_HW_ENABLE | 117 GEN6_RC_CTL_RC6_ENABLE | 118 GEN6_RC_CTL_EI_MODE(1); 119 120 /* Wa_16011777198 - Render powergating must remain disabled */ 121 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || 122 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) 123 pg_enable = 124 GEN9_MEDIA_PG_ENABLE | 125 GEN11_MEDIA_SAMPLER_PG_ENABLE; 126 else 127 pg_enable = 128 GEN9_RENDER_PG_ENABLE | 129 GEN9_MEDIA_PG_ENABLE | 130 GEN11_MEDIA_SAMPLER_PG_ENABLE; 131 132 if (GRAPHICS_VER(gt->i915) >= 12) { 133 for (i = 0; i < I915_MAX_VCS; i++) 134 if (HAS_ENGINE(gt, _VCS(i))) 135 pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) | 136 VDN_MFX_POWERGATE_ENABLE(i)); 137 } 138 139 intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable); 140 } 141 142 static void gen9_rc6_enable(struct intel_rc6 *rc6) 143 { 144 struct intel_uncore *uncore = rc6_to_uncore(rc6); 145 struct intel_engine_cs *engine; 146 enum intel_engine_id id; 147 148 /* 2b: Program RC6 thresholds.*/ 149 if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) { 150 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); 151 intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); 152 } else if (IS_SKYLAKE(rc6_to_i915(rc6))) { 153 /* 154 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only 155 * when CPG is enabled 156 */ 157 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); 158 } else { 159 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); 160 } 161 162 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 163 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 164 for_each_engine(engine, rc6_to_gt(rc6), id) 165 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 166 167 intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA); 168 169 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); 170 171 /* 172 * 2c: Program Coarse Power Gating Policies. 173 * 174 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we 175 * use instead is a more conservative estimate for the maximum time 176 * it takes us to service a CS interrupt and submit a new ELSP - that 177 * is the time which the GPU is idle waiting for the CPU to select the 178 * next request to execute. If the idle hysteresis is less than that 179 * interrupt service latency, the hardware will automatically gate 180 * the power well and we will then incur the wake up cost on top of 181 * the service latency. A similar guide from plane_state is that we 182 * do not want the enable hysteresis to less than the wakeup latency. 183 * 184 * igt/gem_exec_nop/sequential provides a rough estimate for the 185 * service latency, and puts it around 10us for Broadwell (and other 186 * big core) and around 40us for Broxton (and other low power cores). 187 * [Note that for legacy ringbuffer submission, this is less than 1us!] 188 * However, the wakeup latency on Broxton is closer to 100us. To be 189 * conservative, we have to factor in a context switch on top (due 190 * to ksoftirqd). 191 */ 192 intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250); 193 intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250); 194 195 /* 3a: Enable RC6 */ 196 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ 197 198 rc6->ctl_enable = 199 GEN6_RC_CTL_HW_ENABLE | 200 GEN6_RC_CTL_RC6_ENABLE | 201 GEN6_RC_CTL_EI_MODE(1); 202 203 /* 204 * WaRsDisableCoarsePowerGating:skl,cnl 205 * - Render/Media PG need to be disabled with RC6. 206 */ 207 if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6))) 208 intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 209 GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE); 210 } 211 212 static void gen8_rc6_enable(struct intel_rc6 *rc6) 213 { 214 struct intel_uncore *uncore = rc6_to_uncore(rc6); 215 struct intel_engine_cs *engine; 216 enum intel_engine_id id; 217 218 /* 2b: Program RC6 thresholds.*/ 219 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 220 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 221 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 222 for_each_engine(engine, rc6_to_gt(rc6), id) 223 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 224 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); 225 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ 226 227 /* 3: Enable RC6 */ 228 rc6->ctl_enable = 229 GEN6_RC_CTL_HW_ENABLE | 230 GEN7_RC_CTL_TO_MODE | 231 GEN6_RC_CTL_RC6_ENABLE; 232 } 233 234 static void gen6_rc6_enable(struct intel_rc6 *rc6) 235 { 236 struct intel_uncore *uncore = rc6_to_uncore(rc6); 237 struct drm_i915_private *i915 = rc6_to_i915(rc6); 238 struct intel_engine_cs *engine; 239 enum intel_engine_id id; 240 u32 rc6vids, rc6_mask; 241 int ret; 242 243 intel_uncore_write_fw(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 244 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 245 intel_uncore_write_fw(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 246 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); 247 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); 248 249 for_each_engine(engine, rc6_to_gt(rc6), id) 250 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 251 252 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); 253 intel_uncore_write_fw(uncore, GEN6_RC1e_THRESHOLD, 1000); 254 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); 255 intel_uncore_write_fw(uncore, GEN6_RC6p_THRESHOLD, 150000); 256 intel_uncore_write_fw(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 257 258 /* We don't use those on Haswell */ 259 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 260 if (HAS_RC6p(i915)) 261 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 262 if (HAS_RC6pp(i915)) 263 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 264 rc6->ctl_enable = 265 rc6_mask | 266 GEN6_RC_CTL_EI_MODE(1) | 267 GEN6_RC_CTL_HW_ENABLE; 268 269 rc6vids = 0; 270 ret = snb_pcode_read(rc6_to_gt(rc6)->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL); 271 if (GRAPHICS_VER(i915) == 6 && ret) { 272 drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n"); 273 } else if (GRAPHICS_VER(i915) == 6 && 274 (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 275 drm_dbg(&i915->drm, 276 "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 277 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 278 rc6vids &= 0xffff00; 279 rc6vids |= GEN6_ENCODE_RC6_VID(450); 280 ret = snb_pcode_write(rc6_to_gt(rc6)->uncore, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 281 if (ret) 282 drm_err(&i915->drm, 283 "Couldn't fix incorrect rc6 voltage\n"); 284 } 285 } 286 287 /* Check that the pcbr address is not empty. */ 288 static int chv_rc6_init(struct intel_rc6 *rc6) 289 { 290 struct intel_uncore *uncore = rc6_to_uncore(rc6); 291 struct drm_i915_private *i915 = rc6_to_i915(rc6); 292 resource_size_t pctx_paddr, paddr; 293 resource_size_t pctx_size = 32 * SZ_1K; 294 u32 pcbr; 295 296 pcbr = intel_uncore_read(uncore, VLV_PCBR); 297 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { 298 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); 299 paddr = i915->dsm.stolen.end + 1 - pctx_size; 300 GEM_BUG_ON(paddr > U32_MAX); 301 302 pctx_paddr = (paddr & ~4095); 303 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr); 304 } 305 306 return 0; 307 } 308 309 static int vlv_rc6_init(struct intel_rc6 *rc6) 310 { 311 struct drm_i915_private *i915 = rc6_to_i915(rc6); 312 struct intel_uncore *uncore = rc6_to_uncore(rc6); 313 struct drm_i915_gem_object *pctx; 314 resource_size_t pctx_paddr; 315 resource_size_t pctx_size = 24 * SZ_1K; 316 u32 pcbr; 317 318 pcbr = intel_uncore_read(uncore, VLV_PCBR); 319 if (pcbr) { 320 /* BIOS set it up already, grab the pre-alloc'd space */ 321 resource_size_t pcbr_offset; 322 323 pcbr_offset = (pcbr & ~4095) - i915->dsm.stolen.start; 324 pctx = i915_gem_object_create_region_at(i915->mm.stolen_region, 325 pcbr_offset, 326 pctx_size, 327 0); 328 if (IS_ERR(pctx)) 329 return PTR_ERR(pctx); 330 331 goto out; 332 } 333 334 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); 335 336 /* 337 * From the Gunit register HAS: 338 * The Gfx driver is expected to program this register and ensure 339 * proper allocation within Gfx stolen memory. For example, this 340 * register should be programmed such than the PCBR range does not 341 * overlap with other ranges, such as the frame buffer, protected 342 * memory, or any other relevant ranges. 343 */ 344 pctx = i915_gem_object_create_stolen(i915, pctx_size); 345 if (IS_ERR(pctx)) { 346 drm_dbg(&i915->drm, 347 "not enough stolen space for PCTX, disabling\n"); 348 return PTR_ERR(pctx); 349 } 350 351 GEM_BUG_ON(range_overflows_end_t(u64, 352 i915->dsm.stolen.start, 353 pctx->stolen->start, 354 U32_MAX)); 355 pctx_paddr = i915->dsm.stolen.start + pctx->stolen->start; 356 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr); 357 358 out: 359 rc6->pctx = pctx; 360 return 0; 361 } 362 363 static void chv_rc6_enable(struct intel_rc6 *rc6) 364 { 365 struct intel_uncore *uncore = rc6_to_uncore(rc6); 366 struct intel_engine_cs *engine; 367 enum intel_engine_id id; 368 369 /* 2a: Program RC6 thresholds.*/ 370 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 371 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 372 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 373 374 for_each_engine(engine, rc6_to_gt(rc6), id) 375 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 376 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); 377 378 /* TO threshold set to 500 us (0x186 * 1.28 us) */ 379 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x186); 380 381 /* Allows RC6 residency counter to work */ 382 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, 383 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 384 VLV_MEDIA_RC6_COUNT_EN | 385 VLV_RENDER_RC6_COUNT_EN)); 386 387 /* 3: Enable RC6 */ 388 rc6->ctl_enable = GEN7_RC_CTL_TO_MODE; 389 } 390 391 static void vlv_rc6_enable(struct intel_rc6 *rc6) 392 { 393 struct intel_uncore *uncore = rc6_to_uncore(rc6); 394 struct intel_engine_cs *engine; 395 enum intel_engine_id id; 396 397 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); 398 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); 399 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); 400 401 for_each_engine(engine, rc6_to_gt(rc6), id) 402 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 403 404 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x557); 405 406 /* Allows RC6 residency counter to work */ 407 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, 408 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 409 VLV_MEDIA_RC0_COUNT_EN | 410 VLV_RENDER_RC0_COUNT_EN | 411 VLV_MEDIA_RC6_COUNT_EN | 412 VLV_RENDER_RC6_COUNT_EN)); 413 414 rc6->ctl_enable = 415 GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; 416 } 417 418 bool intel_check_bios_c6_setup(struct intel_rc6 *rc6) 419 { 420 if (!rc6->bios_state_captured) { 421 struct intel_uncore *uncore = rc6_to_uncore(rc6); 422 intel_wakeref_t wakeref; 423 424 with_intel_runtime_pm(uncore->rpm, wakeref) 425 rc6->bios_rc_state = intel_uncore_read(uncore, GEN6_RC_STATE); 426 427 rc6->bios_state_captured = true; 428 } 429 430 return rc6->bios_rc_state & RC_SW_TARGET_STATE_MASK; 431 } 432 433 static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6) 434 { 435 struct intel_uncore *uncore = rc6_to_uncore(rc6); 436 struct drm_i915_private *i915 = rc6_to_i915(rc6); 437 u32 rc6_ctx_base, rc_ctl, rc_sw_target; 438 bool enable_rc6 = true; 439 440 rc_ctl = intel_uncore_read(uncore, GEN6_RC_CONTROL); 441 rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE); 442 rc_sw_target &= RC_SW_TARGET_STATE_MASK; 443 rc_sw_target >>= RC_SW_TARGET_STATE_SHIFT; 444 drm_dbg(&i915->drm, "BIOS enabled RC states: " 445 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n", 446 str_on_off(rc_ctl & GEN6_RC_CTL_HW_ENABLE), 447 str_on_off(rc_ctl & GEN6_RC_CTL_RC6_ENABLE), 448 rc_sw_target); 449 450 if (!(intel_uncore_read(uncore, RC6_LOCATION) & RC6_CTX_IN_DRAM)) { 451 drm_dbg(&i915->drm, "RC6 Base location not set properly.\n"); 452 enable_rc6 = false; 453 } 454 455 /* 456 * The exact context size is not known for BXT, so assume a page size 457 * for this check. 458 */ 459 rc6_ctx_base = 460 intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK; 461 if (!(rc6_ctx_base >= i915->dsm.reserved.start && 462 rc6_ctx_base + PAGE_SIZE < i915->dsm.reserved.end)) { 463 drm_dbg(&i915->drm, "RC6 Base address not as expected.\n"); 464 enable_rc6 = false; 465 } 466 467 if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 && 468 (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 && 469 (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 && 470 (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) { 471 drm_dbg(&i915->drm, 472 "Engine Idle wait time not set properly.\n"); 473 enable_rc6 = false; 474 } 475 476 if (!intel_uncore_read(uncore, GEN8_PUSHBUS_CONTROL) || 477 !intel_uncore_read(uncore, GEN8_PUSHBUS_ENABLE) || 478 !intel_uncore_read(uncore, GEN8_PUSHBUS_SHIFT)) { 479 drm_dbg(&i915->drm, "Pushbus not setup properly.\n"); 480 enable_rc6 = false; 481 } 482 483 if (!intel_uncore_read(uncore, GEN6_GFXPAUSE)) { 484 drm_dbg(&i915->drm, "GFX pause not setup properly.\n"); 485 enable_rc6 = false; 486 } 487 488 if (!intel_uncore_read(uncore, GEN8_MISC_CTRL0)) { 489 drm_dbg(&i915->drm, "GPM control not setup properly.\n"); 490 enable_rc6 = false; 491 } 492 493 return enable_rc6; 494 } 495 496 static bool rc6_supported(struct intel_rc6 *rc6) 497 { 498 struct drm_i915_private *i915 = rc6_to_i915(rc6); 499 struct intel_gt *gt = rc6_to_gt(rc6); 500 501 if (!HAS_RC6(i915)) 502 return false; 503 504 if (intel_vgpu_active(i915)) 505 return false; 506 507 if (is_mock_gt(rc6_to_gt(rc6))) 508 return false; 509 510 if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) { 511 drm_notice(&i915->drm, 512 "RC6 and powersaving disabled by BIOS\n"); 513 return false; 514 } 515 516 if (IS_METEORLAKE(gt->i915) && 517 !intel_check_bios_c6_setup(rc6)) { 518 drm_notice(&i915->drm, 519 "C6 disabled by BIOS\n"); 520 return false; 521 } 522 523 if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) && 524 gt->type == GT_MEDIA) { 525 drm_notice(&i915->drm, 526 "Media RC6 disabled on A step\n"); 527 return false; 528 } 529 530 return true; 531 } 532 533 static void rpm_get(struct intel_rc6 *rc6) 534 { 535 GEM_BUG_ON(rc6->wakeref); 536 pm_runtime_get_sync(rc6_to_i915(rc6)->drm.dev); 537 rc6->wakeref = true; 538 } 539 540 static void rpm_put(struct intel_rc6 *rc6) 541 { 542 GEM_BUG_ON(!rc6->wakeref); 543 pm_runtime_put(rc6_to_i915(rc6)->drm.dev); 544 rc6->wakeref = false; 545 } 546 547 static bool pctx_corrupted(struct intel_rc6 *rc6) 548 { 549 struct drm_i915_private *i915 = rc6_to_i915(rc6); 550 551 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 552 return false; 553 554 if (intel_uncore_read(rc6_to_uncore(rc6), GEN8_RC6_CTX_INFO)) 555 return false; 556 557 drm_notice(&i915->drm, 558 "RC6 context corruption, disabling runtime power management\n"); 559 return true; 560 } 561 562 static void __intel_rc6_disable(struct intel_rc6 *rc6) 563 { 564 struct drm_i915_private *i915 = rc6_to_i915(rc6); 565 struct intel_uncore *uncore = rc6_to_uncore(rc6); 566 struct intel_gt *gt = rc6_to_gt(rc6); 567 568 /* Take control of RC6 back from GuC */ 569 intel_guc_rc_disable(>->uc.guc); 570 571 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 572 if (GRAPHICS_VER(i915) >= 9) 573 intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 0); 574 intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, 0); 575 intel_uncore_write_fw(uncore, GEN6_RC_STATE, 0); 576 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 577 } 578 579 static void rc6_res_reg_init(struct intel_rc6 *rc6) 580 { 581 memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg)); 582 583 switch (rc6_to_gt(rc6)->type) { 584 case GT_MEDIA: 585 rc6->res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6; 586 break; 587 default: 588 rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED; 589 rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6; 590 rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p; 591 rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp; 592 break; 593 } 594 } 595 596 void intel_rc6_init(struct intel_rc6 *rc6) 597 { 598 struct drm_i915_private *i915 = rc6_to_i915(rc6); 599 int err; 600 601 /* Disable runtime-pm until we can save the GPU state with rc6 pctx */ 602 rpm_get(rc6); 603 604 if (!rc6_supported(rc6)) 605 return; 606 607 rc6_res_reg_init(rc6); 608 609 if (IS_CHERRYVIEW(i915)) 610 err = chv_rc6_init(rc6); 611 else if (IS_VALLEYVIEW(i915)) 612 err = vlv_rc6_init(rc6); 613 else 614 err = 0; 615 616 /* Sanitize rc6, ensure it is disabled before we are ready. */ 617 __intel_rc6_disable(rc6); 618 619 rc6->supported = err == 0; 620 } 621 622 void intel_rc6_sanitize(struct intel_rc6 *rc6) 623 { 624 memset(rc6->prev_hw_residency, 0, sizeof(rc6->prev_hw_residency)); 625 626 if (rc6->enabled) { /* unbalanced suspend/resume */ 627 rpm_get(rc6); 628 rc6->enabled = false; 629 } 630 631 if (rc6->supported) 632 __intel_rc6_disable(rc6); 633 } 634 635 void intel_rc6_enable(struct intel_rc6 *rc6) 636 { 637 struct drm_i915_private *i915 = rc6_to_i915(rc6); 638 struct intel_uncore *uncore = rc6_to_uncore(rc6); 639 640 if (!rc6->supported) 641 return; 642 643 GEM_BUG_ON(rc6->enabled); 644 645 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 646 647 if (IS_CHERRYVIEW(i915)) 648 chv_rc6_enable(rc6); 649 else if (IS_VALLEYVIEW(i915)) 650 vlv_rc6_enable(rc6); 651 else if (GRAPHICS_VER(i915) >= 11) 652 gen11_rc6_enable(rc6); 653 else if (GRAPHICS_VER(i915) >= 9) 654 gen9_rc6_enable(rc6); 655 else if (IS_BROADWELL(i915)) 656 gen8_rc6_enable(rc6); 657 else if (GRAPHICS_VER(i915) >= 6) 658 gen6_rc6_enable(rc6); 659 660 rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE; 661 if (NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 662 rc6->ctl_enable = 0; 663 664 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 665 666 if (unlikely(pctx_corrupted(rc6))) 667 return; 668 669 /* rc6 is ready, runtime-pm is go! */ 670 rpm_put(rc6); 671 rc6->enabled = true; 672 } 673 674 void intel_rc6_unpark(struct intel_rc6 *rc6) 675 { 676 struct intel_uncore *uncore = rc6_to_uncore(rc6); 677 678 if (!rc6->enabled) 679 return; 680 681 /* Restore HW timers for automatic RC6 entry while busy */ 682 intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable); 683 } 684 685 void intel_rc6_park(struct intel_rc6 *rc6) 686 { 687 struct intel_uncore *uncore = rc6_to_uncore(rc6); 688 unsigned int target; 689 690 if (!rc6->enabled) 691 return; 692 693 if (unlikely(pctx_corrupted(rc6))) { 694 intel_rc6_disable(rc6); 695 return; 696 } 697 698 if (!rc6->manual) 699 return; 700 701 /* Turn off the HW timers and go directly to rc6 */ 702 intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE); 703 704 if (HAS_RC6pp(rc6_to_i915(rc6))) 705 target = 0x6; /* deepest rc6 */ 706 else if (HAS_RC6p(rc6_to_i915(rc6))) 707 target = 0x5; /* deep rc6 */ 708 else 709 target = 0x4; /* normal rc6 */ 710 intel_uncore_write_fw(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT); 711 } 712 713 void intel_rc6_disable(struct intel_rc6 *rc6) 714 { 715 if (!rc6->enabled) 716 return; 717 718 rpm_get(rc6); 719 rc6->enabled = false; 720 721 __intel_rc6_disable(rc6); 722 } 723 724 void intel_rc6_fini(struct intel_rc6 *rc6) 725 { 726 struct drm_i915_gem_object *pctx; 727 struct intel_uncore *uncore = rc6_to_uncore(rc6); 728 729 intel_rc6_disable(rc6); 730 731 /* We want the BIOS C6 state preserved across loads for MTL */ 732 if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured) 733 intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state); 734 735 pctx = fetch_and_zero(&rc6->pctx); 736 if (pctx) 737 i915_gem_object_put(pctx); 738 739 if (rc6->wakeref) 740 rpm_put(rc6); 741 } 742 743 static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg) 744 { 745 u32 lower, upper, tmp; 746 int loop = 2; 747 748 /* 749 * The register accessed do not need forcewake. We borrow 750 * uncore lock to prevent concurrent access to range reg. 751 */ 752 lockdep_assert_held(&uncore->lock); 753 754 /* 755 * vlv and chv residency counters are 40 bits in width. 756 * With a control bit, we can choose between upper or lower 757 * 32bit window into this counter. 758 * 759 * Although we always use the counter in high-range mode elsewhere, 760 * userspace may attempt to read the value before rc6 is initialised, 761 * before we have set the default VLV_COUNTER_CONTROL value. So always 762 * set the high bit to be safe. 763 */ 764 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, 765 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); 766 upper = intel_uncore_read_fw(uncore, reg); 767 do { 768 tmp = upper; 769 770 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, 771 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); 772 lower = intel_uncore_read_fw(uncore, reg); 773 774 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, 775 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); 776 upper = intel_uncore_read_fw(uncore, reg); 777 } while (upper != tmp && --loop); 778 779 /* 780 * Everywhere else we always use VLV_COUNTER_CONTROL with the 781 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set 782 * now. 783 */ 784 785 return lower | (u64)upper << 8; 786 } 787 788 u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id) 789 { 790 struct drm_i915_private *i915 = rc6_to_i915(rc6); 791 struct intel_uncore *uncore = rc6_to_uncore(rc6); 792 u64 time_hw, prev_hw, overflow_hw; 793 i915_reg_t reg = rc6->res_reg[id]; 794 unsigned int fw_domains; 795 unsigned long flags; 796 u32 mul, div; 797 798 if (!rc6->supported) 799 return 0; 800 801 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); 802 803 spin_lock_irqsave(&uncore->lock, flags); 804 intel_uncore_forcewake_get__locked(uncore, fw_domains); 805 806 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ 807 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 808 mul = 1000000; 809 div = i915->czclk_freq; 810 overflow_hw = BIT_ULL(40); 811 time_hw = vlv_residency_raw(uncore, reg); 812 } else { 813 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */ 814 if (IS_GEN9_LP(i915)) { 815 mul = 10000; 816 div = 12; 817 } else { 818 mul = 1280; 819 div = 1; 820 } 821 822 overflow_hw = BIT_ULL(32); 823 time_hw = intel_uncore_read_fw(uncore, reg); 824 } 825 826 /* 827 * Counter wrap handling. 828 * 829 * Store previous hw counter values for counter wrap-around handling. But 830 * relying on a sufficient frequency of queries otherwise counters can still wrap. 831 */ 832 prev_hw = rc6->prev_hw_residency[id]; 833 rc6->prev_hw_residency[id] = time_hw; 834 835 /* RC6 delta from last sample. */ 836 if (time_hw >= prev_hw) 837 time_hw -= prev_hw; 838 else 839 time_hw += overflow_hw - prev_hw; 840 841 /* Add delta to RC6 extended raw driver copy. */ 842 time_hw += rc6->cur_residency[id]; 843 rc6->cur_residency[id] = time_hw; 844 845 intel_uncore_forcewake_put__locked(uncore, fw_domains); 846 spin_unlock_irqrestore(&uncore->lock, flags); 847 848 return mul_u64_u32_div(time_hw, mul, div); 849 } 850 851 u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id) 852 { 853 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, id), 1000); 854 } 855 856 void intel_rc6_print_residency(struct seq_file *m, const char *title, 857 enum intel_rc6_res_type id) 858 { 859 struct intel_gt *gt = m->private; 860 i915_reg_t reg = gt->rc6.res_reg[id]; 861 intel_wakeref_t wakeref; 862 863 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 864 seq_printf(m, "%s %u (%llu us)\n", title, 865 intel_uncore_read(gt->uncore, reg), 866 intel_rc6_residency_us(>->rc6, id)); 867 } 868 869 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 870 #include "selftest_rc6.c" 871 #endif 872