1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2019 Intel Corporation 5 */ 6 7 #include <linux/pm_runtime.h> 8 9 #include "i915_drv.h" 10 #include "intel_gt.h" 11 #include "intel_gt_pm.h" 12 #include "intel_rc6.h" 13 #include "intel_sideband.h" 14 15 /** 16 * DOC: RC6 17 * 18 * RC6 is a special power stage which allows the GPU to enter an very 19 * low-voltage mode when idle, using down to 0V while at this stage. This 20 * stage is entered automatically when the GPU is idle when RC6 support is 21 * enabled, and as soon as new workload arises GPU wakes up automatically as 22 * well. 23 * 24 * There are different RC6 modes available in Intel GPU, which differentiate 25 * among each other with the latency required to enter and leave RC6 and 26 * voltage consumed by the GPU in different states. 27 * 28 * The combination of the following flags define which states GPU is allowed 29 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 30 * RC6pp is deepest RC6. Their support by hardware varies according to the 31 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 32 * which brings the most power savings; deeper states save more power, but 33 * require higher latency to switch to and wake up. 34 */ 35 36 static struct intel_gt *rc6_to_gt(struct intel_rc6 *rc6) 37 { 38 return container_of(rc6, struct intel_gt, rc6); 39 } 40 41 static struct intel_uncore *rc6_to_uncore(struct intel_rc6 *rc) 42 { 43 return rc6_to_gt(rc)->uncore; 44 } 45 46 static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc) 47 { 48 return rc6_to_gt(rc)->i915; 49 } 50 51 static inline void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) 52 { 53 intel_uncore_write_fw(uncore, reg, val); 54 } 55 56 static void gen11_rc6_enable(struct intel_rc6 *rc6) 57 { 58 struct intel_uncore *uncore = rc6_to_uncore(rc6); 59 struct intel_engine_cs *engine; 60 enum intel_engine_id id; 61 62 /* 2b: Program RC6 thresholds.*/ 63 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); 64 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); 65 66 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 67 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 68 for_each_engine(engine, rc6_to_gt(rc6), id) 69 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 70 71 set(uncore, GUC_MAX_IDLE_COUNT, 0xA); 72 73 set(uncore, GEN6_RC_SLEEP, 0); 74 75 set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 76 77 /* 78 * 2c: Program Coarse Power Gating Policies. 79 * 80 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we 81 * use instead is a more conservative estimate for the maximum time 82 * it takes us to service a CS interrupt and submit a new ELSP - that 83 * is the time which the GPU is idle waiting for the CPU to select the 84 * next request to execute. If the idle hysteresis is less than that 85 * interrupt service latency, the hardware will automatically gate 86 * the power well and we will then incur the wake up cost on top of 87 * the service latency. A similar guide from plane_state is that we 88 * do not want the enable hysteresis to less than the wakeup latency. 89 * 90 * igt/gem_exec_nop/sequential provides a rough estimate for the 91 * service latency, and puts it under 10us for Icelake, similar to 92 * Broadwell+, To be conservative, we want to factor in a context 93 * switch on top (due to ksoftirqd). 94 */ 95 set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60); 96 set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60); 97 98 /* 3a: Enable RC6 */ 99 rc6->ctl_enable = 100 GEN6_RC_CTL_HW_ENABLE | 101 GEN6_RC_CTL_RC6_ENABLE | 102 GEN6_RC_CTL_EI_MODE(1); 103 104 set(uncore, GEN9_PG_ENABLE, 105 GEN9_RENDER_PG_ENABLE | 106 GEN9_MEDIA_PG_ENABLE | 107 GEN11_MEDIA_SAMPLER_PG_ENABLE); 108 } 109 110 static void gen9_rc6_enable(struct intel_rc6 *rc6) 111 { 112 struct intel_uncore *uncore = rc6_to_uncore(rc6); 113 struct intel_engine_cs *engine; 114 enum intel_engine_id id; 115 u32 rc6_mode; 116 117 /* 2b: Program RC6 thresholds.*/ 118 if (INTEL_GEN(rc6_to_i915(rc6)) >= 10) { 119 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); 120 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); 121 } else if (IS_SKYLAKE(rc6_to_i915(rc6))) { 122 /* 123 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only 124 * when CPG is enabled 125 */ 126 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); 127 } else { 128 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); 129 } 130 131 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 132 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 133 for_each_engine(engine, rc6_to_gt(rc6), id) 134 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 135 136 set(uncore, GUC_MAX_IDLE_COUNT, 0xA); 137 138 set(uncore, GEN6_RC_SLEEP, 0); 139 140 /* 141 * 2c: Program Coarse Power Gating Policies. 142 * 143 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we 144 * use instead is a more conservative estimate for the maximum time 145 * it takes us to service a CS interrupt and submit a new ELSP - that 146 * is the time which the GPU is idle waiting for the CPU to select the 147 * next request to execute. If the idle hysteresis is less than that 148 * interrupt service latency, the hardware will automatically gate 149 * the power well and we will then incur the wake up cost on top of 150 * the service latency. A similar guide from plane_state is that we 151 * do not want the enable hysteresis to less than the wakeup latency. 152 * 153 * igt/gem_exec_nop/sequential provides a rough estimate for the 154 * service latency, and puts it around 10us for Broadwell (and other 155 * big core) and around 40us for Broxton (and other low power cores). 156 * [Note that for legacy ringbuffer submission, this is less than 1us!] 157 * However, the wakeup latency on Broxton is closer to 100us. To be 158 * conservative, we have to factor in a context switch on top (due 159 * to ksoftirqd). 160 */ 161 set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250); 162 set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250); 163 164 /* 3a: Enable RC6 */ 165 set(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ 166 167 /* WaRsUseTimeoutMode:cnl (pre-prod) */ 168 if (IS_CNL_REVID(rc6_to_i915(rc6), CNL_REVID_A0, CNL_REVID_C0)) 169 rc6_mode = GEN7_RC_CTL_TO_MODE; 170 else 171 rc6_mode = GEN6_RC_CTL_EI_MODE(1); 172 173 rc6->ctl_enable = 174 GEN6_RC_CTL_HW_ENABLE | 175 GEN6_RC_CTL_RC6_ENABLE | 176 rc6_mode; 177 178 /* 179 * WaRsDisableCoarsePowerGating:skl,cnl 180 * - Render/Media PG need to be disabled with RC6. 181 */ 182 if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6))) 183 set(uncore, GEN9_PG_ENABLE, 184 GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE); 185 } 186 187 static void gen8_rc6_enable(struct intel_rc6 *rc6) 188 { 189 struct intel_uncore *uncore = rc6_to_uncore(rc6); 190 struct intel_engine_cs *engine; 191 enum intel_engine_id id; 192 193 /* 2b: Program RC6 thresholds.*/ 194 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 195 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 196 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 197 for_each_engine(engine, rc6_to_gt(rc6), id) 198 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 199 set(uncore, GEN6_RC_SLEEP, 0); 200 set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ 201 202 /* 3: Enable RC6 */ 203 rc6->ctl_enable = 204 GEN6_RC_CTL_HW_ENABLE | 205 GEN7_RC_CTL_TO_MODE | 206 GEN6_RC_CTL_RC6_ENABLE; 207 } 208 209 static void gen6_rc6_enable(struct intel_rc6 *rc6) 210 { 211 struct intel_uncore *uncore = rc6_to_uncore(rc6); 212 struct drm_i915_private *i915 = rc6_to_i915(rc6); 213 struct intel_engine_cs *engine; 214 enum intel_engine_id id; 215 u32 rc6vids, rc6_mask; 216 int ret; 217 218 set(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 219 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 220 set(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 221 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); 222 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); 223 224 for_each_engine(engine, rc6_to_gt(rc6), id) 225 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 226 227 set(uncore, GEN6_RC_SLEEP, 0); 228 set(uncore, GEN6_RC1e_THRESHOLD, 1000); 229 set(uncore, GEN6_RC6_THRESHOLD, 50000); 230 set(uncore, GEN6_RC6p_THRESHOLD, 150000); 231 set(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 232 233 /* We don't use those on Haswell */ 234 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 235 if (HAS_RC6p(i915)) 236 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 237 if (HAS_RC6pp(i915)) 238 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 239 rc6->ctl_enable = 240 rc6_mask | 241 GEN6_RC_CTL_EI_MODE(1) | 242 GEN6_RC_CTL_HW_ENABLE; 243 244 rc6vids = 0; 245 ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, 246 &rc6vids, NULL); 247 if (IS_GEN(i915, 6) && ret) { 248 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); 249 } else if (IS_GEN(i915, 6) && 250 (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 251 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 252 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 253 rc6vids &= 0xffff00; 254 rc6vids |= GEN6_ENCODE_RC6_VID(450); 255 ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 256 if (ret) 257 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 258 } 259 } 260 261 /* Check that the pcbr address is not empty. */ 262 static int chv_rc6_init(struct intel_rc6 *rc6) 263 { 264 struct intel_uncore *uncore = rc6_to_uncore(rc6); 265 resource_size_t pctx_paddr, paddr; 266 resource_size_t pctx_size = 32 * SZ_1K; 267 u32 pcbr; 268 269 pcbr = intel_uncore_read(uncore, VLV_PCBR); 270 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { 271 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 272 paddr = rc6_to_i915(rc6)->dsm.end + 1 - pctx_size; 273 GEM_BUG_ON(paddr > U32_MAX); 274 275 pctx_paddr = (paddr & ~4095); 276 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr); 277 } 278 279 return 0; 280 } 281 282 static int vlv_rc6_init(struct intel_rc6 *rc6) 283 { 284 struct drm_i915_private *i915 = rc6_to_i915(rc6); 285 struct intel_uncore *uncore = rc6_to_uncore(rc6); 286 struct drm_i915_gem_object *pctx; 287 resource_size_t pctx_paddr; 288 resource_size_t pctx_size = 24 * SZ_1K; 289 u32 pcbr; 290 291 pcbr = intel_uncore_read(uncore, VLV_PCBR); 292 if (pcbr) { 293 /* BIOS set it up already, grab the pre-alloc'd space */ 294 resource_size_t pcbr_offset; 295 296 pcbr_offset = (pcbr & ~4095) - i915->dsm.start; 297 pctx = i915_gem_object_create_stolen_for_preallocated(i915, 298 pcbr_offset, 299 pctx_size); 300 if (IS_ERR(pctx)) 301 return PTR_ERR(pctx); 302 303 goto out; 304 } 305 306 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 307 308 /* 309 * From the Gunit register HAS: 310 * The Gfx driver is expected to program this register and ensure 311 * proper allocation within Gfx stolen memory. For example, this 312 * register should be programmed such than the PCBR range does not 313 * overlap with other ranges, such as the frame buffer, protected 314 * memory, or any other relevant ranges. 315 */ 316 pctx = i915_gem_object_create_stolen(i915, pctx_size); 317 if (IS_ERR(pctx)) { 318 DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); 319 return PTR_ERR(pctx); 320 } 321 322 GEM_BUG_ON(range_overflows_t(u64, 323 i915->dsm.start, 324 pctx->stolen->start, 325 U32_MAX)); 326 pctx_paddr = i915->dsm.start + pctx->stolen->start; 327 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr); 328 329 out: 330 rc6->pctx = pctx; 331 return 0; 332 } 333 334 static void chv_rc6_enable(struct intel_rc6 *rc6) 335 { 336 struct intel_uncore *uncore = rc6_to_uncore(rc6); 337 struct intel_engine_cs *engine; 338 enum intel_engine_id id; 339 340 /* 2a: Program RC6 thresholds.*/ 341 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 342 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 343 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 344 345 for_each_engine(engine, rc6_to_gt(rc6), id) 346 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 347 set(uncore, GEN6_RC_SLEEP, 0); 348 349 /* TO threshold set to 500 us (0x186 * 1.28 us) */ 350 set(uncore, GEN6_RC6_THRESHOLD, 0x186); 351 352 /* Allows RC6 residency counter to work */ 353 set(uncore, VLV_COUNTER_CONTROL, 354 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 355 VLV_MEDIA_RC6_COUNT_EN | 356 VLV_RENDER_RC6_COUNT_EN)); 357 358 /* 3: Enable RC6 */ 359 rc6->ctl_enable = GEN7_RC_CTL_TO_MODE; 360 } 361 362 static void vlv_rc6_enable(struct intel_rc6 *rc6) 363 { 364 struct intel_uncore *uncore = rc6_to_uncore(rc6); 365 struct intel_engine_cs *engine; 366 enum intel_engine_id id; 367 368 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); 369 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); 370 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); 371 372 for_each_engine(engine, rc6_to_gt(rc6), id) 373 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 374 375 set(uncore, GEN6_RC6_THRESHOLD, 0x557); 376 377 /* Allows RC6 residency counter to work */ 378 set(uncore, VLV_COUNTER_CONTROL, 379 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 380 VLV_MEDIA_RC0_COUNT_EN | 381 VLV_RENDER_RC0_COUNT_EN | 382 VLV_MEDIA_RC6_COUNT_EN | 383 VLV_RENDER_RC6_COUNT_EN)); 384 385 rc6->ctl_enable = 386 GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; 387 } 388 389 static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6) 390 { 391 struct intel_uncore *uncore = rc6_to_uncore(rc6); 392 struct drm_i915_private *i915 = rc6_to_i915(rc6); 393 u32 rc6_ctx_base, rc_ctl, rc_sw_target; 394 bool enable_rc6 = true; 395 396 rc_ctl = intel_uncore_read(uncore, GEN6_RC_CONTROL); 397 rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE); 398 rc_sw_target &= RC_SW_TARGET_STATE_MASK; 399 rc_sw_target >>= RC_SW_TARGET_STATE_SHIFT; 400 DRM_DEBUG_DRIVER("BIOS enabled RC states: " 401 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n", 402 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE), 403 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE), 404 rc_sw_target); 405 406 if (!(intel_uncore_read(uncore, RC6_LOCATION) & RC6_CTX_IN_DRAM)) { 407 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n"); 408 enable_rc6 = false; 409 } 410 411 /* 412 * The exact context size is not known for BXT, so assume a page size 413 * for this check. 414 */ 415 rc6_ctx_base = 416 intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK; 417 if (!(rc6_ctx_base >= i915->dsm_reserved.start && 418 rc6_ctx_base + PAGE_SIZE < i915->dsm_reserved.end)) { 419 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n"); 420 enable_rc6 = false; 421 } 422 423 if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 && 424 (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 && 425 (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 && 426 (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) { 427 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n"); 428 enable_rc6 = false; 429 } 430 431 if (!intel_uncore_read(uncore, GEN8_PUSHBUS_CONTROL) || 432 !intel_uncore_read(uncore, GEN8_PUSHBUS_ENABLE) || 433 !intel_uncore_read(uncore, GEN8_PUSHBUS_SHIFT)) { 434 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n"); 435 enable_rc6 = false; 436 } 437 438 if (!intel_uncore_read(uncore, GEN6_GFXPAUSE)) { 439 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n"); 440 enable_rc6 = false; 441 } 442 443 if (!intel_uncore_read(uncore, GEN8_MISC_CTRL0)) { 444 DRM_DEBUG_DRIVER("GPM control not setup properly.\n"); 445 enable_rc6 = false; 446 } 447 448 return enable_rc6; 449 } 450 451 static bool rc6_supported(struct intel_rc6 *rc6) 452 { 453 struct drm_i915_private *i915 = rc6_to_i915(rc6); 454 455 if (!HAS_RC6(i915)) 456 return false; 457 458 if (intel_vgpu_active(i915)) 459 return false; 460 461 if (is_mock_gt(rc6_to_gt(rc6))) 462 return false; 463 464 if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) { 465 dev_notice(i915->drm.dev, 466 "RC6 and powersaving disabled by BIOS\n"); 467 return false; 468 } 469 470 return true; 471 } 472 473 static void rpm_get(struct intel_rc6 *rc6) 474 { 475 GEM_BUG_ON(rc6->wakeref); 476 pm_runtime_get_sync(&rc6_to_i915(rc6)->drm.pdev->dev); 477 rc6->wakeref = true; 478 } 479 480 static void rpm_put(struct intel_rc6 *rc6) 481 { 482 GEM_BUG_ON(!rc6->wakeref); 483 pm_runtime_put(&rc6_to_i915(rc6)->drm.pdev->dev); 484 rc6->wakeref = false; 485 } 486 487 static bool pctx_corrupted(struct intel_rc6 *rc6) 488 { 489 struct drm_i915_private *i915 = rc6_to_i915(rc6); 490 491 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 492 return false; 493 494 if (intel_uncore_read(rc6_to_uncore(rc6), GEN8_RC6_CTX_INFO)) 495 return false; 496 497 dev_notice(i915->drm.dev, 498 "RC6 context corruption, disabling runtime power management\n"); 499 return true; 500 } 501 502 static void __intel_rc6_disable(struct intel_rc6 *rc6) 503 { 504 struct drm_i915_private *i915 = rc6_to_i915(rc6); 505 struct intel_uncore *uncore = rc6_to_uncore(rc6); 506 507 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 508 if (INTEL_GEN(i915) >= 9) 509 set(uncore, GEN9_PG_ENABLE, 0); 510 set(uncore, GEN6_RC_CONTROL, 0); 511 set(uncore, GEN6_RC_STATE, 0); 512 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 513 } 514 515 void intel_rc6_init(struct intel_rc6 *rc6) 516 { 517 struct drm_i915_private *i915 = rc6_to_i915(rc6); 518 int err; 519 520 /* Disable runtime-pm until we can save the GPU state with rc6 pctx */ 521 rpm_get(rc6); 522 523 if (!rc6_supported(rc6)) 524 return; 525 526 if (IS_CHERRYVIEW(i915)) 527 err = chv_rc6_init(rc6); 528 else if (IS_VALLEYVIEW(i915)) 529 err = vlv_rc6_init(rc6); 530 else 531 err = 0; 532 533 /* Sanitize rc6, ensure it is disabled before we are ready. */ 534 __intel_rc6_disable(rc6); 535 536 rc6->supported = err == 0; 537 } 538 539 void intel_rc6_sanitize(struct intel_rc6 *rc6) 540 { 541 memset(rc6->prev_hw_residency, 0, sizeof(rc6->prev_hw_residency)); 542 543 if (rc6->enabled) { /* unbalanced suspend/resume */ 544 rpm_get(rc6); 545 rc6->enabled = false; 546 } 547 548 if (rc6->supported) 549 __intel_rc6_disable(rc6); 550 } 551 552 void intel_rc6_enable(struct intel_rc6 *rc6) 553 { 554 struct drm_i915_private *i915 = rc6_to_i915(rc6); 555 struct intel_uncore *uncore = rc6_to_uncore(rc6); 556 557 if (!rc6->supported) 558 return; 559 560 GEM_BUG_ON(rc6->enabled); 561 562 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 563 564 if (IS_CHERRYVIEW(i915)) 565 chv_rc6_enable(rc6); 566 else if (IS_VALLEYVIEW(i915)) 567 vlv_rc6_enable(rc6); 568 else if (INTEL_GEN(i915) >= 11) 569 gen11_rc6_enable(rc6); 570 else if (INTEL_GEN(i915) >= 9) 571 gen9_rc6_enable(rc6); 572 else if (IS_BROADWELL(i915)) 573 gen8_rc6_enable(rc6); 574 else if (INTEL_GEN(i915) >= 6) 575 gen6_rc6_enable(rc6); 576 577 rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE; 578 if (NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 579 rc6->ctl_enable = 0; 580 581 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 582 583 if (unlikely(pctx_corrupted(rc6))) 584 return; 585 586 /* rc6 is ready, runtime-pm is go! */ 587 rpm_put(rc6); 588 rc6->enabled = true; 589 } 590 591 void intel_rc6_unpark(struct intel_rc6 *rc6) 592 { 593 struct intel_uncore *uncore = rc6_to_uncore(rc6); 594 595 if (!rc6->enabled) 596 return; 597 598 /* Restore HW timers for automatic RC6 entry while busy */ 599 set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable); 600 } 601 602 void intel_rc6_park(struct intel_rc6 *rc6) 603 { 604 struct intel_uncore *uncore = rc6_to_uncore(rc6); 605 606 if (!rc6->enabled) 607 return; 608 609 if (unlikely(pctx_corrupted(rc6))) { 610 intel_rc6_disable(rc6); 611 return; 612 } 613 614 if (!rc6->manual) 615 return; 616 617 /* Turn off the HW timers and go directly to rc6 */ 618 set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE); 619 set(uncore, GEN6_RC_STATE, 0x4 << RC_SW_TARGET_STATE_SHIFT); 620 } 621 622 void intel_rc6_disable(struct intel_rc6 *rc6) 623 { 624 if (!rc6->enabled) 625 return; 626 627 rpm_get(rc6); 628 rc6->enabled = false; 629 630 __intel_rc6_disable(rc6); 631 } 632 633 void intel_rc6_fini(struct intel_rc6 *rc6) 634 { 635 struct drm_i915_gem_object *pctx; 636 637 intel_rc6_disable(rc6); 638 639 pctx = fetch_and_zero(&rc6->pctx); 640 if (pctx) 641 i915_gem_object_put(pctx); 642 643 if (rc6->wakeref) 644 rpm_put(rc6); 645 } 646 647 static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg) 648 { 649 u32 lower, upper, tmp; 650 int loop = 2; 651 652 /* 653 * The register accessed do not need forcewake. We borrow 654 * uncore lock to prevent concurrent access to range reg. 655 */ 656 lockdep_assert_held(&uncore->lock); 657 658 /* 659 * vlv and chv residency counters are 40 bits in width. 660 * With a control bit, we can choose between upper or lower 661 * 32bit window into this counter. 662 * 663 * Although we always use the counter in high-range mode elsewhere, 664 * userspace may attempt to read the value before rc6 is initialised, 665 * before we have set the default VLV_COUNTER_CONTROL value. So always 666 * set the high bit to be safe. 667 */ 668 set(uncore, VLV_COUNTER_CONTROL, 669 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); 670 upper = intel_uncore_read_fw(uncore, reg); 671 do { 672 tmp = upper; 673 674 set(uncore, VLV_COUNTER_CONTROL, 675 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); 676 lower = intel_uncore_read_fw(uncore, reg); 677 678 set(uncore, VLV_COUNTER_CONTROL, 679 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); 680 upper = intel_uncore_read_fw(uncore, reg); 681 } while (upper != tmp && --loop); 682 683 /* 684 * Everywhere else we always use VLV_COUNTER_CONTROL with the 685 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set 686 * now. 687 */ 688 689 return lower | (u64)upper << 8; 690 } 691 692 u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) 693 { 694 struct drm_i915_private *i915 = rc6_to_i915(rc6); 695 struct intel_uncore *uncore = rc6_to_uncore(rc6); 696 u64 time_hw, prev_hw, overflow_hw; 697 unsigned int fw_domains; 698 unsigned long flags; 699 unsigned int i; 700 u32 mul, div; 701 702 if (!rc6->supported) 703 return 0; 704 705 /* 706 * Store previous hw counter values for counter wrap-around handling. 707 * 708 * There are only four interesting registers and they live next to each 709 * other so we can use the relative address, compared to the smallest 710 * one as the index into driver storage. 711 */ 712 i = (i915_mmio_reg_offset(reg) - 713 i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32); 714 if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency))) 715 return 0; 716 717 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); 718 719 spin_lock_irqsave(&uncore->lock, flags); 720 intel_uncore_forcewake_get__locked(uncore, fw_domains); 721 722 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ 723 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 724 mul = 1000000; 725 div = i915->czclk_freq; 726 overflow_hw = BIT_ULL(40); 727 time_hw = vlv_residency_raw(uncore, reg); 728 } else { 729 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */ 730 if (IS_GEN9_LP(i915)) { 731 mul = 10000; 732 div = 12; 733 } else { 734 mul = 1280; 735 div = 1; 736 } 737 738 overflow_hw = BIT_ULL(32); 739 time_hw = intel_uncore_read_fw(uncore, reg); 740 } 741 742 /* 743 * Counter wrap handling. 744 * 745 * But relying on a sufficient frequency of queries otherwise counters 746 * can still wrap. 747 */ 748 prev_hw = rc6->prev_hw_residency[i]; 749 rc6->prev_hw_residency[i] = time_hw; 750 751 /* RC6 delta from last sample. */ 752 if (time_hw >= prev_hw) 753 time_hw -= prev_hw; 754 else 755 time_hw += overflow_hw - prev_hw; 756 757 /* Add delta to RC6 extended raw driver copy. */ 758 time_hw += rc6->cur_residency[i]; 759 rc6->cur_residency[i] = time_hw; 760 761 intel_uncore_forcewake_put__locked(uncore, fw_domains); 762 spin_unlock_irqrestore(&uncore->lock, flags); 763 764 return mul_u64_u32_div(time_hw, mul, div); 765 } 766 767 u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg) 768 { 769 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000); 770 } 771 772 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 773 #include "selftest_rc6.c" 774 #endif 775