1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/pm_runtime.h> 7 #include <linux/string_helpers.h> 8 9 #include "i915_drv.h" 10 #include "i915_reg.h" 11 #include "i915_vgpu.h" 12 #include "intel_engine_regs.h" 13 #include "intel_gt.h" 14 #include "intel_gt_pm.h" 15 #include "intel_gt_regs.h" 16 #include "intel_pcode.h" 17 #include "intel_rc6.h" 18 19 /** 20 * DOC: RC6 21 * 22 * RC6 is a special power stage which allows the GPU to enter an very 23 * low-voltage mode when idle, using down to 0V while at this stage. This 24 * stage is entered automatically when the GPU is idle when RC6 support is 25 * enabled, and as soon as new workload arises GPU wakes up automatically as 26 * well. 27 * 28 * There are different RC6 modes available in Intel GPU, which differentiate 29 * among each other with the latency required to enter and leave RC6 and 30 * voltage consumed by the GPU in different states. 31 * 32 * The combination of the following flags define which states GPU is allowed 33 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 34 * RC6pp is deepest RC6. Their support by hardware varies according to the 35 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 36 * which brings the most power savings; deeper states save more power, but 37 * require higher latency to switch to and wake up. 38 */ 39 40 static struct intel_gt *rc6_to_gt(struct intel_rc6 *rc6) 41 { 42 return container_of(rc6, struct intel_gt, rc6); 43 } 44 45 static struct intel_uncore *rc6_to_uncore(struct intel_rc6 *rc) 46 { 47 return rc6_to_gt(rc)->uncore; 48 } 49 50 static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc) 51 { 52 return rc6_to_gt(rc)->i915; 53 } 54 55 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) 56 { 57 intel_uncore_write_fw(uncore, reg, val); 58 } 59 60 static void gen11_rc6_enable(struct intel_rc6 *rc6) 61 { 62 struct intel_gt *gt = rc6_to_gt(rc6); 63 struct intel_uncore *uncore = gt->uncore; 64 struct intel_engine_cs *engine; 65 enum intel_engine_id id; 66 u32 pg_enable; 67 int i; 68 69 /* 70 * With GuCRC, these parameters are set by GuC 71 */ 72 if (!intel_uc_uses_guc_rc(>->uc)) { 73 /* 2b: Program RC6 thresholds.*/ 74 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); 75 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); 76 77 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 78 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 79 for_each_engine(engine, rc6_to_gt(rc6), id) 80 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 81 82 set(uncore, GUC_MAX_IDLE_COUNT, 0xA); 83 84 set(uncore, GEN6_RC_SLEEP, 0); 85 86 set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 87 } 88 89 /* 90 * 2c: Program Coarse Power Gating Policies. 91 * 92 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we 93 * use instead is a more conservative estimate for the maximum time 94 * it takes us to service a CS interrupt and submit a new ELSP - that 95 * is the time which the GPU is idle waiting for the CPU to select the 96 * next request to execute. If the idle hysteresis is less than that 97 * interrupt service latency, the hardware will automatically gate 98 * the power well and we will then incur the wake up cost on top of 99 * the service latency. A similar guide from plane_state is that we 100 * do not want the enable hysteresis to less than the wakeup latency. 101 * 102 * igt/gem_exec_nop/sequential provides a rough estimate for the 103 * service latency, and puts it under 10us for Icelake, similar to 104 * Broadwell+, To be conservative, we want to factor in a context 105 * switch on top (due to ksoftirqd). 106 */ 107 set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60); 108 set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60); 109 110 /* 3a: Enable RC6 111 * 112 * With GuCRC, we do not enable bit 31 of RC_CTL, 113 * thus allowing GuC to control RC6 entry/exit fully instead. 114 * We will not set the HW ENABLE and EI bits 115 */ 116 if (!intel_guc_rc_enable(>->uc.guc)) 117 rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE; 118 else 119 rc6->ctl_enable = 120 GEN6_RC_CTL_HW_ENABLE | 121 GEN6_RC_CTL_RC6_ENABLE | 122 GEN6_RC_CTL_EI_MODE(1); 123 124 /* Wa_16011777198 - Render powergating must remain disabled */ 125 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || 126 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) 127 pg_enable = 128 GEN9_MEDIA_PG_ENABLE | 129 GEN11_MEDIA_SAMPLER_PG_ENABLE; 130 else 131 pg_enable = 132 GEN9_RENDER_PG_ENABLE | 133 GEN9_MEDIA_PG_ENABLE | 134 GEN11_MEDIA_SAMPLER_PG_ENABLE; 135 136 if (GRAPHICS_VER(gt->i915) >= 12) { 137 for (i = 0; i < I915_MAX_VCS; i++) 138 if (HAS_ENGINE(gt, _VCS(i))) 139 pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) | 140 VDN_MFX_POWERGATE_ENABLE(i)); 141 } 142 143 set(uncore, GEN9_PG_ENABLE, pg_enable); 144 } 145 146 static void gen9_rc6_enable(struct intel_rc6 *rc6) 147 { 148 struct intel_uncore *uncore = rc6_to_uncore(rc6); 149 struct intel_engine_cs *engine; 150 enum intel_engine_id id; 151 152 /* 2b: Program RC6 thresholds.*/ 153 if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) { 154 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); 155 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); 156 } else if (IS_SKYLAKE(rc6_to_i915(rc6))) { 157 /* 158 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only 159 * when CPG is enabled 160 */ 161 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); 162 } else { 163 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); 164 } 165 166 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 167 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 168 for_each_engine(engine, rc6_to_gt(rc6), id) 169 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 170 171 set(uncore, GUC_MAX_IDLE_COUNT, 0xA); 172 173 set(uncore, GEN6_RC_SLEEP, 0); 174 175 /* 176 * 2c: Program Coarse Power Gating Policies. 177 * 178 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we 179 * use instead is a more conservative estimate for the maximum time 180 * it takes us to service a CS interrupt and submit a new ELSP - that 181 * is the time which the GPU is idle waiting for the CPU to select the 182 * next request to execute. If the idle hysteresis is less than that 183 * interrupt service latency, the hardware will automatically gate 184 * the power well and we will then incur the wake up cost on top of 185 * the service latency. A similar guide from plane_state is that we 186 * do not want the enable hysteresis to less than the wakeup latency. 187 * 188 * igt/gem_exec_nop/sequential provides a rough estimate for the 189 * service latency, and puts it around 10us for Broadwell (and other 190 * big core) and around 40us for Broxton (and other low power cores). 191 * [Note that for legacy ringbuffer submission, this is less than 1us!] 192 * However, the wakeup latency on Broxton is closer to 100us. To be 193 * conservative, we have to factor in a context switch on top (due 194 * to ksoftirqd). 195 */ 196 set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250); 197 set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250); 198 199 /* 3a: Enable RC6 */ 200 set(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ 201 202 rc6->ctl_enable = 203 GEN6_RC_CTL_HW_ENABLE | 204 GEN6_RC_CTL_RC6_ENABLE | 205 GEN6_RC_CTL_EI_MODE(1); 206 207 /* 208 * WaRsDisableCoarsePowerGating:skl,cnl 209 * - Render/Media PG need to be disabled with RC6. 210 */ 211 if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6))) 212 set(uncore, GEN9_PG_ENABLE, 213 GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE); 214 } 215 216 static void gen8_rc6_enable(struct intel_rc6 *rc6) 217 { 218 struct intel_uncore *uncore = rc6_to_uncore(rc6); 219 struct intel_engine_cs *engine; 220 enum intel_engine_id id; 221 222 /* 2b: Program RC6 thresholds.*/ 223 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 224 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 225 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 226 for_each_engine(engine, rc6_to_gt(rc6), id) 227 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 228 set(uncore, GEN6_RC_SLEEP, 0); 229 set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ 230 231 /* 3: Enable RC6 */ 232 rc6->ctl_enable = 233 GEN6_RC_CTL_HW_ENABLE | 234 GEN7_RC_CTL_TO_MODE | 235 GEN6_RC_CTL_RC6_ENABLE; 236 } 237 238 static void gen6_rc6_enable(struct intel_rc6 *rc6) 239 { 240 struct intel_uncore *uncore = rc6_to_uncore(rc6); 241 struct drm_i915_private *i915 = rc6_to_i915(rc6); 242 struct intel_engine_cs *engine; 243 enum intel_engine_id id; 244 u32 rc6vids, rc6_mask; 245 int ret; 246 247 set(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 248 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 249 set(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 250 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); 251 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); 252 253 for_each_engine(engine, rc6_to_gt(rc6), id) 254 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 255 256 set(uncore, GEN6_RC_SLEEP, 0); 257 set(uncore, GEN6_RC1e_THRESHOLD, 1000); 258 set(uncore, GEN6_RC6_THRESHOLD, 50000); 259 set(uncore, GEN6_RC6p_THRESHOLD, 150000); 260 set(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 261 262 /* We don't use those on Haswell */ 263 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 264 if (HAS_RC6p(i915)) 265 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 266 if (HAS_RC6pp(i915)) 267 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 268 rc6->ctl_enable = 269 rc6_mask | 270 GEN6_RC_CTL_EI_MODE(1) | 271 GEN6_RC_CTL_HW_ENABLE; 272 273 rc6vids = 0; 274 ret = snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL); 275 if (GRAPHICS_VER(i915) == 6 && ret) { 276 drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n"); 277 } else if (GRAPHICS_VER(i915) == 6 && 278 (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 279 drm_dbg(&i915->drm, 280 "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 281 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 282 rc6vids &= 0xffff00; 283 rc6vids |= GEN6_ENCODE_RC6_VID(450); 284 ret = snb_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 285 if (ret) 286 drm_err(&i915->drm, 287 "Couldn't fix incorrect rc6 voltage\n"); 288 } 289 } 290 291 /* Check that the pcbr address is not empty. */ 292 static int chv_rc6_init(struct intel_rc6 *rc6) 293 { 294 struct intel_uncore *uncore = rc6_to_uncore(rc6); 295 struct drm_i915_private *i915 = rc6_to_i915(rc6); 296 resource_size_t pctx_paddr, paddr; 297 resource_size_t pctx_size = 32 * SZ_1K; 298 u32 pcbr; 299 300 pcbr = intel_uncore_read(uncore, VLV_PCBR); 301 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { 302 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); 303 paddr = i915->dsm.end + 1 - pctx_size; 304 GEM_BUG_ON(paddr > U32_MAX); 305 306 pctx_paddr = (paddr & ~4095); 307 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr); 308 } 309 310 return 0; 311 } 312 313 static int vlv_rc6_init(struct intel_rc6 *rc6) 314 { 315 struct drm_i915_private *i915 = rc6_to_i915(rc6); 316 struct intel_uncore *uncore = rc6_to_uncore(rc6); 317 struct drm_i915_gem_object *pctx; 318 resource_size_t pctx_paddr; 319 resource_size_t pctx_size = 24 * SZ_1K; 320 u32 pcbr; 321 322 pcbr = intel_uncore_read(uncore, VLV_PCBR); 323 if (pcbr) { 324 /* BIOS set it up already, grab the pre-alloc'd space */ 325 resource_size_t pcbr_offset; 326 327 pcbr_offset = (pcbr & ~4095) - i915->dsm.start; 328 pctx = i915_gem_object_create_stolen_for_preallocated(i915, 329 pcbr_offset, 330 pctx_size); 331 if (IS_ERR(pctx)) 332 return PTR_ERR(pctx); 333 334 goto out; 335 } 336 337 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); 338 339 /* 340 * From the Gunit register HAS: 341 * The Gfx driver is expected to program this register and ensure 342 * proper allocation within Gfx stolen memory. For example, this 343 * register should be programmed such than the PCBR range does not 344 * overlap with other ranges, such as the frame buffer, protected 345 * memory, or any other relevant ranges. 346 */ 347 pctx = i915_gem_object_create_stolen(i915, pctx_size); 348 if (IS_ERR(pctx)) { 349 drm_dbg(&i915->drm, 350 "not enough stolen space for PCTX, disabling\n"); 351 return PTR_ERR(pctx); 352 } 353 354 GEM_BUG_ON(range_overflows_end_t(u64, 355 i915->dsm.start, 356 pctx->stolen->start, 357 U32_MAX)); 358 pctx_paddr = i915->dsm.start + pctx->stolen->start; 359 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr); 360 361 out: 362 rc6->pctx = pctx; 363 return 0; 364 } 365 366 static void chv_rc6_enable(struct intel_rc6 *rc6) 367 { 368 struct intel_uncore *uncore = rc6_to_uncore(rc6); 369 struct intel_engine_cs *engine; 370 enum intel_engine_id id; 371 372 /* 2a: Program RC6 thresholds.*/ 373 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 374 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 375 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 376 377 for_each_engine(engine, rc6_to_gt(rc6), id) 378 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 379 set(uncore, GEN6_RC_SLEEP, 0); 380 381 /* TO threshold set to 500 us (0x186 * 1.28 us) */ 382 set(uncore, GEN6_RC6_THRESHOLD, 0x186); 383 384 /* Allows RC6 residency counter to work */ 385 set(uncore, VLV_COUNTER_CONTROL, 386 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 387 VLV_MEDIA_RC6_COUNT_EN | 388 VLV_RENDER_RC6_COUNT_EN)); 389 390 /* 3: Enable RC6 */ 391 rc6->ctl_enable = GEN7_RC_CTL_TO_MODE; 392 } 393 394 static void vlv_rc6_enable(struct intel_rc6 *rc6) 395 { 396 struct intel_uncore *uncore = rc6_to_uncore(rc6); 397 struct intel_engine_cs *engine; 398 enum intel_engine_id id; 399 400 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); 401 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); 402 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); 403 404 for_each_engine(engine, rc6_to_gt(rc6), id) 405 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 406 407 set(uncore, GEN6_RC6_THRESHOLD, 0x557); 408 409 /* Allows RC6 residency counter to work */ 410 set(uncore, VLV_COUNTER_CONTROL, 411 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 412 VLV_MEDIA_RC0_COUNT_EN | 413 VLV_RENDER_RC0_COUNT_EN | 414 VLV_MEDIA_RC6_COUNT_EN | 415 VLV_RENDER_RC6_COUNT_EN)); 416 417 rc6->ctl_enable = 418 GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; 419 } 420 421 static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6) 422 { 423 struct intel_uncore *uncore = rc6_to_uncore(rc6); 424 struct drm_i915_private *i915 = rc6_to_i915(rc6); 425 u32 rc6_ctx_base, rc_ctl, rc_sw_target; 426 bool enable_rc6 = true; 427 428 rc_ctl = intel_uncore_read(uncore, GEN6_RC_CONTROL); 429 rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE); 430 rc_sw_target &= RC_SW_TARGET_STATE_MASK; 431 rc_sw_target >>= RC_SW_TARGET_STATE_SHIFT; 432 drm_dbg(&i915->drm, "BIOS enabled RC states: " 433 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n", 434 str_on_off(rc_ctl & GEN6_RC_CTL_HW_ENABLE), 435 str_on_off(rc_ctl & GEN6_RC_CTL_RC6_ENABLE), 436 rc_sw_target); 437 438 if (!(intel_uncore_read(uncore, RC6_LOCATION) & RC6_CTX_IN_DRAM)) { 439 drm_dbg(&i915->drm, "RC6 Base location not set properly.\n"); 440 enable_rc6 = false; 441 } 442 443 /* 444 * The exact context size is not known for BXT, so assume a page size 445 * for this check. 446 */ 447 rc6_ctx_base = 448 intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK; 449 if (!(rc6_ctx_base >= i915->dsm_reserved.start && 450 rc6_ctx_base + PAGE_SIZE < i915->dsm_reserved.end)) { 451 drm_dbg(&i915->drm, "RC6 Base address not as expected.\n"); 452 enable_rc6 = false; 453 } 454 455 if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 && 456 (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 && 457 (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 && 458 (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) { 459 drm_dbg(&i915->drm, 460 "Engine Idle wait time not set properly.\n"); 461 enable_rc6 = false; 462 } 463 464 if (!intel_uncore_read(uncore, GEN8_PUSHBUS_CONTROL) || 465 !intel_uncore_read(uncore, GEN8_PUSHBUS_ENABLE) || 466 !intel_uncore_read(uncore, GEN8_PUSHBUS_SHIFT)) { 467 drm_dbg(&i915->drm, "Pushbus not setup properly.\n"); 468 enable_rc6 = false; 469 } 470 471 if (!intel_uncore_read(uncore, GEN6_GFXPAUSE)) { 472 drm_dbg(&i915->drm, "GFX pause not setup properly.\n"); 473 enable_rc6 = false; 474 } 475 476 if (!intel_uncore_read(uncore, GEN8_MISC_CTRL0)) { 477 drm_dbg(&i915->drm, "GPM control not setup properly.\n"); 478 enable_rc6 = false; 479 } 480 481 return enable_rc6; 482 } 483 484 static bool rc6_supported(struct intel_rc6 *rc6) 485 { 486 struct drm_i915_private *i915 = rc6_to_i915(rc6); 487 488 if (!HAS_RC6(i915)) 489 return false; 490 491 if (intel_vgpu_active(i915)) 492 return false; 493 494 if (is_mock_gt(rc6_to_gt(rc6))) 495 return false; 496 497 if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) { 498 drm_notice(&i915->drm, 499 "RC6 and powersaving disabled by BIOS\n"); 500 return false; 501 } 502 503 return true; 504 } 505 506 static void rpm_get(struct intel_rc6 *rc6) 507 { 508 GEM_BUG_ON(rc6->wakeref); 509 pm_runtime_get_sync(rc6_to_i915(rc6)->drm.dev); 510 rc6->wakeref = true; 511 } 512 513 static void rpm_put(struct intel_rc6 *rc6) 514 { 515 GEM_BUG_ON(!rc6->wakeref); 516 pm_runtime_put(rc6_to_i915(rc6)->drm.dev); 517 rc6->wakeref = false; 518 } 519 520 static bool pctx_corrupted(struct intel_rc6 *rc6) 521 { 522 struct drm_i915_private *i915 = rc6_to_i915(rc6); 523 524 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 525 return false; 526 527 if (intel_uncore_read(rc6_to_uncore(rc6), GEN8_RC6_CTX_INFO)) 528 return false; 529 530 drm_notice(&i915->drm, 531 "RC6 context corruption, disabling runtime power management\n"); 532 return true; 533 } 534 535 static void __intel_rc6_disable(struct intel_rc6 *rc6) 536 { 537 struct drm_i915_private *i915 = rc6_to_i915(rc6); 538 struct intel_uncore *uncore = rc6_to_uncore(rc6); 539 struct intel_gt *gt = rc6_to_gt(rc6); 540 541 /* Take control of RC6 back from GuC */ 542 intel_guc_rc_disable(>->uc.guc); 543 544 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 545 if (GRAPHICS_VER(i915) >= 9) 546 set(uncore, GEN9_PG_ENABLE, 0); 547 set(uncore, GEN6_RC_CONTROL, 0); 548 set(uncore, GEN6_RC_STATE, 0); 549 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 550 } 551 552 void intel_rc6_init(struct intel_rc6 *rc6) 553 { 554 struct drm_i915_private *i915 = rc6_to_i915(rc6); 555 int err; 556 557 /* Disable runtime-pm until we can save the GPU state with rc6 pctx */ 558 rpm_get(rc6); 559 560 if (!rc6_supported(rc6)) 561 return; 562 563 if (IS_CHERRYVIEW(i915)) 564 err = chv_rc6_init(rc6); 565 else if (IS_VALLEYVIEW(i915)) 566 err = vlv_rc6_init(rc6); 567 else 568 err = 0; 569 570 /* Sanitize rc6, ensure it is disabled before we are ready. */ 571 __intel_rc6_disable(rc6); 572 573 rc6->supported = err == 0; 574 } 575 576 void intel_rc6_sanitize(struct intel_rc6 *rc6) 577 { 578 memset(rc6->prev_hw_residency, 0, sizeof(rc6->prev_hw_residency)); 579 580 if (rc6->enabled) { /* unbalanced suspend/resume */ 581 rpm_get(rc6); 582 rc6->enabled = false; 583 } 584 585 if (rc6->supported) 586 __intel_rc6_disable(rc6); 587 } 588 589 void intel_rc6_enable(struct intel_rc6 *rc6) 590 { 591 struct drm_i915_private *i915 = rc6_to_i915(rc6); 592 struct intel_uncore *uncore = rc6_to_uncore(rc6); 593 594 if (!rc6->supported) 595 return; 596 597 GEM_BUG_ON(rc6->enabled); 598 599 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 600 601 if (IS_CHERRYVIEW(i915)) 602 chv_rc6_enable(rc6); 603 else if (IS_VALLEYVIEW(i915)) 604 vlv_rc6_enable(rc6); 605 else if (GRAPHICS_VER(i915) >= 11) 606 gen11_rc6_enable(rc6); 607 else if (GRAPHICS_VER(i915) >= 9) 608 gen9_rc6_enable(rc6); 609 else if (IS_BROADWELL(i915)) 610 gen8_rc6_enable(rc6); 611 else if (GRAPHICS_VER(i915) >= 6) 612 gen6_rc6_enable(rc6); 613 614 rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE; 615 if (NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 616 rc6->ctl_enable = 0; 617 618 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 619 620 if (unlikely(pctx_corrupted(rc6))) 621 return; 622 623 /* rc6 is ready, runtime-pm is go! */ 624 rpm_put(rc6); 625 rc6->enabled = true; 626 } 627 628 void intel_rc6_unpark(struct intel_rc6 *rc6) 629 { 630 struct intel_uncore *uncore = rc6_to_uncore(rc6); 631 632 if (!rc6->enabled) 633 return; 634 635 /* Restore HW timers for automatic RC6 entry while busy */ 636 set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable); 637 } 638 639 void intel_rc6_park(struct intel_rc6 *rc6) 640 { 641 struct intel_uncore *uncore = rc6_to_uncore(rc6); 642 unsigned int target; 643 644 if (!rc6->enabled) 645 return; 646 647 if (unlikely(pctx_corrupted(rc6))) { 648 intel_rc6_disable(rc6); 649 return; 650 } 651 652 if (!rc6->manual) 653 return; 654 655 /* Turn off the HW timers and go directly to rc6 */ 656 set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE); 657 658 if (HAS_RC6pp(rc6_to_i915(rc6))) 659 target = 0x6; /* deepest rc6 */ 660 else if (HAS_RC6p(rc6_to_i915(rc6))) 661 target = 0x5; /* deep rc6 */ 662 else 663 target = 0x4; /* normal rc6 */ 664 set(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT); 665 } 666 667 void intel_rc6_disable(struct intel_rc6 *rc6) 668 { 669 if (!rc6->enabled) 670 return; 671 672 rpm_get(rc6); 673 rc6->enabled = false; 674 675 __intel_rc6_disable(rc6); 676 } 677 678 void intel_rc6_fini(struct intel_rc6 *rc6) 679 { 680 struct drm_i915_gem_object *pctx; 681 682 intel_rc6_disable(rc6); 683 684 pctx = fetch_and_zero(&rc6->pctx); 685 if (pctx) 686 i915_gem_object_put(pctx); 687 688 if (rc6->wakeref) 689 rpm_put(rc6); 690 } 691 692 static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg) 693 { 694 u32 lower, upper, tmp; 695 int loop = 2; 696 697 /* 698 * The register accessed do not need forcewake. We borrow 699 * uncore lock to prevent concurrent access to range reg. 700 */ 701 lockdep_assert_held(&uncore->lock); 702 703 /* 704 * vlv and chv residency counters are 40 bits in width. 705 * With a control bit, we can choose between upper or lower 706 * 32bit window into this counter. 707 * 708 * Although we always use the counter in high-range mode elsewhere, 709 * userspace may attempt to read the value before rc6 is initialised, 710 * before we have set the default VLV_COUNTER_CONTROL value. So always 711 * set the high bit to be safe. 712 */ 713 set(uncore, VLV_COUNTER_CONTROL, 714 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); 715 upper = intel_uncore_read_fw(uncore, reg); 716 do { 717 tmp = upper; 718 719 set(uncore, VLV_COUNTER_CONTROL, 720 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); 721 lower = intel_uncore_read_fw(uncore, reg); 722 723 set(uncore, VLV_COUNTER_CONTROL, 724 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); 725 upper = intel_uncore_read_fw(uncore, reg); 726 } while (upper != tmp && --loop); 727 728 /* 729 * Everywhere else we always use VLV_COUNTER_CONTROL with the 730 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set 731 * now. 732 */ 733 734 return lower | (u64)upper << 8; 735 } 736 737 u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) 738 { 739 struct drm_i915_private *i915 = rc6_to_i915(rc6); 740 struct intel_uncore *uncore = rc6_to_uncore(rc6); 741 u64 time_hw, prev_hw, overflow_hw; 742 unsigned int fw_domains; 743 unsigned long flags; 744 unsigned int i; 745 u32 mul, div; 746 747 if (!rc6->supported) 748 return 0; 749 750 /* 751 * Store previous hw counter values for counter wrap-around handling. 752 * 753 * There are only four interesting registers and they live next to each 754 * other so we can use the relative address, compared to the smallest 755 * one as the index into driver storage. 756 */ 757 i = (i915_mmio_reg_offset(reg) - 758 i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32); 759 if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency))) 760 return 0; 761 762 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); 763 764 spin_lock_irqsave(&uncore->lock, flags); 765 intel_uncore_forcewake_get__locked(uncore, fw_domains); 766 767 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ 768 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 769 mul = 1000000; 770 div = i915->czclk_freq; 771 overflow_hw = BIT_ULL(40); 772 time_hw = vlv_residency_raw(uncore, reg); 773 } else { 774 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */ 775 if (IS_GEN9_LP(i915)) { 776 mul = 10000; 777 div = 12; 778 } else { 779 mul = 1280; 780 div = 1; 781 } 782 783 overflow_hw = BIT_ULL(32); 784 time_hw = intel_uncore_read_fw(uncore, reg); 785 } 786 787 /* 788 * Counter wrap handling. 789 * 790 * But relying on a sufficient frequency of queries otherwise counters 791 * can still wrap. 792 */ 793 prev_hw = rc6->prev_hw_residency[i]; 794 rc6->prev_hw_residency[i] = time_hw; 795 796 /* RC6 delta from last sample. */ 797 if (time_hw >= prev_hw) 798 time_hw -= prev_hw; 799 else 800 time_hw += overflow_hw - prev_hw; 801 802 /* Add delta to RC6 extended raw driver copy. */ 803 time_hw += rc6->cur_residency[i]; 804 rc6->cur_residency[i] = time_hw; 805 806 intel_uncore_forcewake_put__locked(uncore, fw_domains); 807 spin_unlock_irqrestore(&uncore->lock, flags); 808 809 return mul_u64_u32_div(time_hw, mul, div); 810 } 811 812 u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg) 813 { 814 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000); 815 } 816 817 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 818 #include "selftest_rc6.c" 819 #endif 820