1 /* 2 * Copyright (c) 2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: * 10 * The above copyright notice and this permission notice (including the next 11 * paragraph) shall be included in all copies or substantial portions of the 12 * Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23 #include "i915_drv.h" 24 25 #include "intel_engine.h" 26 #include "intel_gt.h" 27 #include "intel_mocs.h" 28 #include "intel_lrc.h" 29 #include "intel_ring.h" 30 31 /* structures required */ 32 struct drm_i915_mocs_entry { 33 u32 control_value; 34 u16 l3cc_value; 35 u16 used; 36 }; 37 38 struct drm_i915_mocs_table { 39 unsigned int size; 40 unsigned int n_entries; 41 const struct drm_i915_mocs_entry *table; 42 }; 43 44 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */ 45 #define _LE_CACHEABILITY(value) ((value) << 0) 46 #define _LE_TGT_CACHE(value) ((value) << 2) 47 #define LE_LRUM(value) ((value) << 4) 48 #define LE_AOM(value) ((value) << 6) 49 #define LE_RSC(value) ((value) << 7) 50 #define LE_SCC(value) ((value) << 8) 51 #define LE_PFM(value) ((value) << 11) 52 #define LE_SCF(value) ((value) << 14) 53 #define LE_COS(value) ((value) << 15) 54 #define LE_SSE(value) ((value) << 17) 55 56 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */ 57 #define L3_ESC(value) ((value) << 0) 58 #define L3_SCC(value) ((value) << 1) 59 #define _L3_CACHEABILITY(value) ((value) << 4) 60 61 /* Helper defines */ 62 #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */ 63 #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */ 64 65 /* (e)LLC caching options */ 66 /* 67 * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means 68 * the same as LE_UC 69 */ 70 #define LE_0_PAGETABLE _LE_CACHEABILITY(0) 71 #define LE_1_UC _LE_CACHEABILITY(1) 72 #define LE_2_WT _LE_CACHEABILITY(2) 73 #define LE_3_WB _LE_CACHEABILITY(3) 74 75 /* Target cache */ 76 #define LE_TC_0_PAGETABLE _LE_TGT_CACHE(0) 77 #define LE_TC_1_LLC _LE_TGT_CACHE(1) 78 #define LE_TC_2_LLC_ELLC _LE_TGT_CACHE(2) 79 #define LE_TC_3_LLC_ELLC_ALT _LE_TGT_CACHE(3) 80 81 /* L3 caching options */ 82 #define L3_0_DIRECT _L3_CACHEABILITY(0) 83 #define L3_1_UC _L3_CACHEABILITY(1) 84 #define L3_2_RESERVED _L3_CACHEABILITY(2) 85 #define L3_3_WB _L3_CACHEABILITY(3) 86 87 #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \ 88 [__idx] = { \ 89 .control_value = __control_value, \ 90 .l3cc_value = __l3cc_value, \ 91 .used = 1, \ 92 } 93 94 /* 95 * MOCS tables 96 * 97 * These are the MOCS tables that are programmed across all the rings. 98 * The control value is programmed to all the rings that support the 99 * MOCS registers. While the l3cc_values are only programmed to the 100 * LNCFCMOCS0 - LNCFCMOCS32 registers. 101 * 102 * These tables are intended to be kept reasonably consistent across 103 * HW platforms, and for ICL+, be identical across OSes. To achieve 104 * that, for Icelake and above, list of entries is published as part 105 * of bspec. 106 * 107 * Entries not part of the following tables are undefined as far as 108 * userspace is concerned and shouldn't be relied upon. For Gen < 12 109 * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for 110 * PTE and will be initialized to an invalid value. 111 * 112 * The last two entries are reserved by the hardware. For ICL+ they 113 * should be initialized according to bspec and never used, for older 114 * platforms they should never be written to. 115 * 116 * NOTE: These tables are part of bspec and defined as part of hardware 117 * interface for ICL+. For older platforms, they are part of kernel 118 * ABI. It is expected that, for specific hardware platform, existing 119 * entries will remain constant and the table will only be updated by 120 * adding new entries, filling unused positions. 121 */ 122 #define GEN9_MOCS_ENTRIES \ 123 MOCS_ENTRY(I915_MOCS_UNCACHED, \ 124 LE_1_UC | LE_TC_2_LLC_ELLC, \ 125 L3_1_UC), \ 126 MOCS_ENTRY(I915_MOCS_PTE, \ 127 LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \ 128 L3_3_WB) 129 130 static const struct drm_i915_mocs_entry skl_mocs_table[] = { 131 GEN9_MOCS_ENTRIES, 132 MOCS_ENTRY(I915_MOCS_CACHED, 133 LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3), 134 L3_3_WB), 135 136 /* 137 * mocs:63 138 * - used by the L3 for all of its evictions. 139 * Thus it is expected to allow LLC cacheability to enable coherent 140 * flows to be maintained. 141 * - used to force L3 uncachable cycles. 142 * Thus it is expected to make the surface L3 uncacheable. 143 */ 144 MOCS_ENTRY(63, 145 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), 146 L3_1_UC) 147 }; 148 149 /* NOTE: the LE_TGT_CACHE is not used on Broxton */ 150 static const struct drm_i915_mocs_entry broxton_mocs_table[] = { 151 GEN9_MOCS_ENTRIES, 152 MOCS_ENTRY(I915_MOCS_CACHED, 153 LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3), 154 L3_3_WB) 155 }; 156 157 #define GEN11_MOCS_ENTRIES \ 158 /* Entries 0 and 1 are defined per-platform */ \ 159 /* Base - L3 + LLC */ \ 160 MOCS_ENTRY(2, \ 161 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ 162 L3_3_WB), \ 163 /* Base - Uncached */ \ 164 MOCS_ENTRY(3, \ 165 LE_1_UC | LE_TC_1_LLC, \ 166 L3_1_UC), \ 167 /* Base - L3 */ \ 168 MOCS_ENTRY(4, \ 169 LE_1_UC | LE_TC_1_LLC, \ 170 L3_3_WB), \ 171 /* Base - LLC */ \ 172 MOCS_ENTRY(5, \ 173 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ 174 L3_1_UC), \ 175 /* Age 0 - LLC */ \ 176 MOCS_ENTRY(6, \ 177 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \ 178 L3_1_UC), \ 179 /* Age 0 - L3 + LLC */ \ 180 MOCS_ENTRY(7, \ 181 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \ 182 L3_3_WB), \ 183 /* Age: Don't Chg. - LLC */ \ 184 MOCS_ENTRY(8, \ 185 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \ 186 L3_1_UC), \ 187 /* Age: Don't Chg. - L3 + LLC */ \ 188 MOCS_ENTRY(9, \ 189 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \ 190 L3_3_WB), \ 191 /* No AOM - LLC */ \ 192 MOCS_ENTRY(10, \ 193 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \ 194 L3_1_UC), \ 195 /* No AOM - L3 + LLC */ \ 196 MOCS_ENTRY(11, \ 197 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \ 198 L3_3_WB), \ 199 /* No AOM; Age 0 - LLC */ \ 200 MOCS_ENTRY(12, \ 201 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \ 202 L3_1_UC), \ 203 /* No AOM; Age 0 - L3 + LLC */ \ 204 MOCS_ENTRY(13, \ 205 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \ 206 L3_3_WB), \ 207 /* No AOM; Age:DC - LLC */ \ 208 MOCS_ENTRY(14, \ 209 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \ 210 L3_1_UC), \ 211 /* No AOM; Age:DC - L3 + LLC */ \ 212 MOCS_ENTRY(15, \ 213 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \ 214 L3_3_WB), \ 215 /* Self-Snoop - L3 + LLC */ \ 216 MOCS_ENTRY(18, \ 217 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \ 218 L3_3_WB), \ 219 /* Skip Caching - L3 + LLC(12.5%) */ \ 220 MOCS_ENTRY(19, \ 221 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \ 222 L3_3_WB), \ 223 /* Skip Caching - L3 + LLC(25%) */ \ 224 MOCS_ENTRY(20, \ 225 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \ 226 L3_3_WB), \ 227 /* Skip Caching - L3 + LLC(50%) */ \ 228 MOCS_ENTRY(21, \ 229 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \ 230 L3_3_WB), \ 231 /* Skip Caching - L3 + LLC(75%) */ \ 232 MOCS_ENTRY(22, \ 233 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \ 234 L3_3_WB), \ 235 /* Skip Caching - L3 + LLC(87.5%) */ \ 236 MOCS_ENTRY(23, \ 237 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \ 238 L3_3_WB), \ 239 /* HW Reserved - SW program but never use */ \ 240 MOCS_ENTRY(62, \ 241 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ 242 L3_1_UC), \ 243 /* HW Reserved - SW program but never use */ \ 244 MOCS_ENTRY(63, \ 245 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ 246 L3_1_UC) 247 248 static const struct drm_i915_mocs_entry tgl_mocs_table[] = { 249 /* 250 * NOTE: 251 * Reserved and unspecified MOCS indices have been set to (L3 + LCC). 252 * These reserved entries should never be used, they may be changed 253 * to low performant variants with better coherency in the future if 254 * more entries are needed. We are programming index I915_MOCS_PTE(1) 255 * only, __init_mocs_table() take care to program unused index with 256 * this entry. 257 */ 258 MOCS_ENTRY(I915_MOCS_PTE, 259 LE_0_PAGETABLE | LE_TC_0_PAGETABLE, 260 L3_1_UC), 261 GEN11_MOCS_ENTRIES, 262 263 /* Implicitly enable L1 - HDC:L1 + L3 + LLC */ 264 MOCS_ENTRY(48, 265 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), 266 L3_3_WB), 267 /* Implicitly enable L1 - HDC:L1 + L3 */ 268 MOCS_ENTRY(49, 269 LE_1_UC | LE_TC_1_LLC, 270 L3_3_WB), 271 /* Implicitly enable L1 - HDC:L1 + LLC */ 272 MOCS_ENTRY(50, 273 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), 274 L3_1_UC), 275 /* Implicitly enable L1 - HDC:L1 */ 276 MOCS_ENTRY(51, 277 LE_1_UC | LE_TC_1_LLC, 278 L3_1_UC), 279 /* HW Special Case (CCS) */ 280 MOCS_ENTRY(60, 281 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), 282 L3_1_UC), 283 /* HW Special Case (Displayable) */ 284 MOCS_ENTRY(61, 285 LE_1_UC | LE_TC_1_LLC, 286 L3_3_WB), 287 }; 288 289 static const struct drm_i915_mocs_entry icl_mocs_table[] = { 290 /* Base - Uncached (Deprecated) */ 291 MOCS_ENTRY(I915_MOCS_UNCACHED, 292 LE_1_UC | LE_TC_1_LLC, 293 L3_1_UC), 294 /* Base - L3 + LeCC:PAT (Deprecated) */ 295 MOCS_ENTRY(I915_MOCS_PTE, 296 LE_0_PAGETABLE | LE_TC_1_LLC, 297 L3_3_WB), 298 299 GEN11_MOCS_ENTRIES 300 }; 301 302 enum { 303 HAS_GLOBAL_MOCS = BIT(0), 304 HAS_ENGINE_MOCS = BIT(1), 305 HAS_RENDER_L3CC = BIT(2), 306 }; 307 308 static bool has_l3cc(const struct drm_i915_private *i915) 309 { 310 return true; 311 } 312 313 static bool has_global_mocs(const struct drm_i915_private *i915) 314 { 315 return HAS_GLOBAL_MOCS_REGISTERS(i915); 316 } 317 318 static bool has_mocs(const struct drm_i915_private *i915) 319 { 320 return !IS_DGFX(i915); 321 } 322 323 static unsigned int get_mocs_settings(const struct drm_i915_private *i915, 324 struct drm_i915_mocs_table *table) 325 { 326 unsigned int flags; 327 328 if (INTEL_GEN(i915) >= 12) { 329 table->size = ARRAY_SIZE(tgl_mocs_table); 330 table->table = tgl_mocs_table; 331 table->n_entries = GEN11_NUM_MOCS_ENTRIES; 332 } else if (IS_GEN(i915, 11)) { 333 table->size = ARRAY_SIZE(icl_mocs_table); 334 table->table = icl_mocs_table; 335 table->n_entries = GEN11_NUM_MOCS_ENTRIES; 336 } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) { 337 table->size = ARRAY_SIZE(skl_mocs_table); 338 table->n_entries = GEN9_NUM_MOCS_ENTRIES; 339 table->table = skl_mocs_table; 340 } else if (IS_GEN9_LP(i915)) { 341 table->size = ARRAY_SIZE(broxton_mocs_table); 342 table->n_entries = GEN9_NUM_MOCS_ENTRIES; 343 table->table = broxton_mocs_table; 344 } else { 345 drm_WARN_ONCE(&i915->drm, INTEL_GEN(i915) >= 9, 346 "Platform that should have a MOCS table does not.\n"); 347 return 0; 348 } 349 350 if (GEM_DEBUG_WARN_ON(table->size > table->n_entries)) 351 return 0; 352 353 /* WaDisableSkipCaching:skl,bxt,kbl,glk */ 354 if (IS_GEN(i915, 9)) { 355 int i; 356 357 for (i = 0; i < table->size; i++) 358 if (GEM_DEBUG_WARN_ON(table->table[i].l3cc_value & 359 (L3_ESC(1) | L3_SCC(0x7)))) 360 return 0; 361 } 362 363 flags = 0; 364 if (has_mocs(i915)) { 365 if (has_global_mocs(i915)) 366 flags |= HAS_GLOBAL_MOCS; 367 else 368 flags |= HAS_ENGINE_MOCS; 369 } 370 if (has_l3cc(i915)) 371 flags |= HAS_RENDER_L3CC; 372 373 return flags; 374 } 375 376 /* 377 * Get control_value from MOCS entry taking into account when it's not used: 378 * I915_MOCS_PTE's value is returned in this case. 379 */ 380 static u32 get_entry_control(const struct drm_i915_mocs_table *table, 381 unsigned int index) 382 { 383 if (index < table->size && table->table[index].used) 384 return table->table[index].control_value; 385 386 return table->table[I915_MOCS_PTE].control_value; 387 } 388 389 #define for_each_mocs(mocs, t, i) \ 390 for (i = 0; \ 391 i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\ 392 i++) 393 394 static void __init_mocs_table(struct intel_uncore *uncore, 395 const struct drm_i915_mocs_table *table, 396 u32 addr) 397 { 398 unsigned int i; 399 u32 mocs; 400 401 for_each_mocs(mocs, table, i) 402 intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs); 403 } 404 405 static u32 mocs_offset(const struct intel_engine_cs *engine) 406 { 407 static const u32 offset[] = { 408 [RCS0] = __GEN9_RCS0_MOCS0, 409 [VCS0] = __GEN9_VCS0_MOCS0, 410 [VCS1] = __GEN9_VCS1_MOCS0, 411 [VECS0] = __GEN9_VECS0_MOCS0, 412 [BCS0] = __GEN9_BCS0_MOCS0, 413 [VCS2] = __GEN11_VCS2_MOCS0, 414 }; 415 416 GEM_BUG_ON(engine->id >= ARRAY_SIZE(offset)); 417 return offset[engine->id]; 418 } 419 420 static void init_mocs_table(struct intel_engine_cs *engine, 421 const struct drm_i915_mocs_table *table) 422 { 423 __init_mocs_table(engine->uncore, table, mocs_offset(engine)); 424 } 425 426 /* 427 * Get l3cc_value from MOCS entry taking into account when it's not used: 428 * I915_MOCS_PTE's value is returned in this case. 429 */ 430 static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table, 431 unsigned int index) 432 { 433 if (index < table->size && table->table[index].used) 434 return table->table[index].l3cc_value; 435 436 return table->table[I915_MOCS_PTE].l3cc_value; 437 } 438 439 static inline u32 l3cc_combine(u16 low, u16 high) 440 { 441 return low | (u32)high << 16; 442 } 443 444 #define for_each_l3cc(l3cc, t, i) \ 445 for (i = 0; \ 446 i < ((t)->n_entries + 1) / 2 ? \ 447 (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \ 448 get_entry_l3cc((t), 2 * i + 1))), 1 : \ 449 0; \ 450 i++) 451 452 static void init_l3cc_table(struct intel_engine_cs *engine, 453 const struct drm_i915_mocs_table *table) 454 { 455 struct intel_uncore *uncore = engine->uncore; 456 unsigned int i; 457 u32 l3cc; 458 459 for_each_l3cc(l3cc, table, i) 460 intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc); 461 } 462 463 void intel_mocs_init_engine(struct intel_engine_cs *engine) 464 { 465 struct drm_i915_mocs_table table; 466 unsigned int flags; 467 468 /* Called under a blanket forcewake */ 469 assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL); 470 471 flags = get_mocs_settings(engine->i915, &table); 472 if (!flags) 473 return; 474 475 /* Platforms with global MOCS do not need per-engine initialization. */ 476 if (flags & HAS_ENGINE_MOCS) 477 init_mocs_table(engine, &table); 478 479 if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS) 480 init_l3cc_table(engine, &table); 481 } 482 483 static u32 global_mocs_offset(void) 484 { 485 return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0)); 486 } 487 488 void intel_mocs_init(struct intel_gt *gt) 489 { 490 struct drm_i915_mocs_table table; 491 unsigned int flags; 492 493 /* 494 * LLC and eDRAM control values are not applicable to dgfx 495 */ 496 flags = get_mocs_settings(gt->i915, &table); 497 if (flags & HAS_GLOBAL_MOCS) 498 __init_mocs_table(gt->uncore, &table, global_mocs_offset()); 499 } 500 501 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 502 #include "selftest_mocs.c" 503 #endif 504