1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2015 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 8 #include "intel_engine.h" 9 #include "intel_gt.h" 10 #include "intel_gt_regs.h" 11 #include "intel_mocs.h" 12 #include "intel_ring.h" 13 14 /* structures required */ 15 struct drm_i915_mocs_entry { 16 u32 control_value; 17 u16 l3cc_value; 18 u16 used; 19 }; 20 21 struct drm_i915_mocs_table { 22 unsigned int size; 23 unsigned int n_entries; 24 const struct drm_i915_mocs_entry *table; 25 u8 uc_index; 26 u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */ 27 u8 unused_entries_index; 28 }; 29 30 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */ 31 #define _LE_CACHEABILITY(value) ((value) << 0) 32 #define _LE_TGT_CACHE(value) ((value) << 2) 33 #define LE_LRUM(value) ((value) << 4) 34 #define LE_AOM(value) ((value) << 6) 35 #define LE_RSC(value) ((value) << 7) 36 #define LE_SCC(value) ((value) << 8) 37 #define LE_PFM(value) ((value) << 11) 38 #define LE_SCF(value) ((value) << 14) 39 #define LE_COS(value) ((value) << 15) 40 #define LE_SSE(value) ((value) << 17) 41 42 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */ 43 #define L3_ESC(value) ((value) << 0) 44 #define L3_SCC(value) ((value) << 1) 45 #define _L3_CACHEABILITY(value) ((value) << 4) 46 #define L3_GLBGO(value) ((value) << 6) 47 #define L3_LKUP(value) ((value) << 7) 48 49 /* Helper defines */ 50 #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */ 51 #define PVC_NUM_MOCS_ENTRIES 3 52 53 /* (e)LLC caching options */ 54 /* 55 * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means 56 * the same as LE_UC 57 */ 58 #define LE_0_PAGETABLE _LE_CACHEABILITY(0) 59 #define LE_1_UC _LE_CACHEABILITY(1) 60 #define LE_2_WT _LE_CACHEABILITY(2) 61 #define LE_3_WB _LE_CACHEABILITY(3) 62 63 /* Target cache */ 64 #define LE_TC_0_PAGETABLE _LE_TGT_CACHE(0) 65 #define LE_TC_1_LLC _LE_TGT_CACHE(1) 66 #define LE_TC_2_LLC_ELLC _LE_TGT_CACHE(2) 67 #define LE_TC_3_LLC_ELLC_ALT _LE_TGT_CACHE(3) 68 69 /* L3 caching options */ 70 #define L3_0_DIRECT _L3_CACHEABILITY(0) 71 #define L3_1_UC _L3_CACHEABILITY(1) 72 #define L3_2_RESERVED _L3_CACHEABILITY(2) 73 #define L3_3_WB _L3_CACHEABILITY(3) 74 75 #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \ 76 [__idx] = { \ 77 .control_value = __control_value, \ 78 .l3cc_value = __l3cc_value, \ 79 .used = 1, \ 80 } 81 82 /* 83 * MOCS tables 84 * 85 * These are the MOCS tables that are programmed across all the rings. 86 * The control value is programmed to all the rings that support the 87 * MOCS registers. While the l3cc_values are only programmed to the 88 * LNCFCMOCS0 - LNCFCMOCS32 registers. 89 * 90 * These tables are intended to be kept reasonably consistent across 91 * HW platforms, and for ICL+, be identical across OSes. To achieve 92 * that, for Icelake and above, list of entries is published as part 93 * of bspec. 94 * 95 * Entries not part of the following tables are undefined as far as 96 * userspace is concerned and shouldn't be relied upon. For Gen < 12 97 * they will be initialized to PTE. Gen >= 12 don't have a setting for 98 * PTE and those platforms except TGL/RKL will be initialized L3 WB to 99 * catch accidental use of reserved and unused mocs indexes. 100 * 101 * The last few entries are reserved by the hardware. For ICL+ they 102 * should be initialized according to bspec and never used, for older 103 * platforms they should never be written to. 104 * 105 * NOTE1: These tables are part of bspec and defined as part of hardware 106 * interface for ICL+. For older platforms, they are part of kernel 107 * ABI. It is expected that, for specific hardware platform, existing 108 * entries will remain constant and the table will only be updated by 109 * adding new entries, filling unused positions. 110 * 111 * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified MOCS 112 * indices have been set to L3 WB. These reserved entries should never 113 * be used, they may be changed to low performant variants with better 114 * coherency in the future if more entries are needed. 115 * For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC. 116 */ 117 #define GEN9_MOCS_ENTRIES \ 118 MOCS_ENTRY(I915_MOCS_UNCACHED, \ 119 LE_1_UC | LE_TC_2_LLC_ELLC, \ 120 L3_1_UC), \ 121 MOCS_ENTRY(I915_MOCS_PTE, \ 122 LE_0_PAGETABLE | LE_TC_0_PAGETABLE | LE_LRUM(3), \ 123 L3_3_WB) 124 125 static const struct drm_i915_mocs_entry skl_mocs_table[] = { 126 GEN9_MOCS_ENTRIES, 127 MOCS_ENTRY(I915_MOCS_CACHED, 128 LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3), 129 L3_3_WB), 130 131 /* 132 * mocs:63 133 * - used by the L3 for all of its evictions. 134 * Thus it is expected to allow LLC cacheability to enable coherent 135 * flows to be maintained. 136 * - used to force L3 uncachable cycles. 137 * Thus it is expected to make the surface L3 uncacheable. 138 */ 139 MOCS_ENTRY(63, 140 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), 141 L3_1_UC) 142 }; 143 144 /* NOTE: the LE_TGT_CACHE is not used on Broxton */ 145 static const struct drm_i915_mocs_entry broxton_mocs_table[] = { 146 GEN9_MOCS_ENTRIES, 147 MOCS_ENTRY(I915_MOCS_CACHED, 148 LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3), 149 L3_3_WB) 150 }; 151 152 #define GEN11_MOCS_ENTRIES \ 153 /* Entries 0 and 1 are defined per-platform */ \ 154 /* Base - L3 + LLC */ \ 155 MOCS_ENTRY(2, \ 156 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ 157 L3_3_WB), \ 158 /* Base - Uncached */ \ 159 MOCS_ENTRY(3, \ 160 LE_1_UC | LE_TC_1_LLC, \ 161 L3_1_UC), \ 162 /* Base - L3 */ \ 163 MOCS_ENTRY(4, \ 164 LE_1_UC | LE_TC_1_LLC, \ 165 L3_3_WB), \ 166 /* Base - LLC */ \ 167 MOCS_ENTRY(5, \ 168 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ 169 L3_1_UC), \ 170 /* Age 0 - LLC */ \ 171 MOCS_ENTRY(6, \ 172 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \ 173 L3_1_UC), \ 174 /* Age 0 - L3 + LLC */ \ 175 MOCS_ENTRY(7, \ 176 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \ 177 L3_3_WB), \ 178 /* Age: Don't Chg. - LLC */ \ 179 MOCS_ENTRY(8, \ 180 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \ 181 L3_1_UC), \ 182 /* Age: Don't Chg. - L3 + LLC */ \ 183 MOCS_ENTRY(9, \ 184 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \ 185 L3_3_WB), \ 186 /* No AOM - LLC */ \ 187 MOCS_ENTRY(10, \ 188 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \ 189 L3_1_UC), \ 190 /* No AOM - L3 + LLC */ \ 191 MOCS_ENTRY(11, \ 192 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \ 193 L3_3_WB), \ 194 /* No AOM; Age 0 - LLC */ \ 195 MOCS_ENTRY(12, \ 196 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \ 197 L3_1_UC), \ 198 /* No AOM; Age 0 - L3 + LLC */ \ 199 MOCS_ENTRY(13, \ 200 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \ 201 L3_3_WB), \ 202 /* No AOM; Age:DC - LLC */ \ 203 MOCS_ENTRY(14, \ 204 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \ 205 L3_1_UC), \ 206 /* No AOM; Age:DC - L3 + LLC */ \ 207 MOCS_ENTRY(15, \ 208 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \ 209 L3_3_WB), \ 210 /* Self-Snoop - L3 + LLC */ \ 211 MOCS_ENTRY(18, \ 212 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \ 213 L3_3_WB), \ 214 /* Skip Caching - L3 + LLC(12.5%) */ \ 215 MOCS_ENTRY(19, \ 216 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \ 217 L3_3_WB), \ 218 /* Skip Caching - L3 + LLC(25%) */ \ 219 MOCS_ENTRY(20, \ 220 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \ 221 L3_3_WB), \ 222 /* Skip Caching - L3 + LLC(50%) */ \ 223 MOCS_ENTRY(21, \ 224 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \ 225 L3_3_WB), \ 226 /* Skip Caching - L3 + LLC(75%) */ \ 227 MOCS_ENTRY(22, \ 228 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \ 229 L3_3_WB), \ 230 /* Skip Caching - L3 + LLC(87.5%) */ \ 231 MOCS_ENTRY(23, \ 232 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \ 233 L3_3_WB), \ 234 /* HW Reserved - SW program but never use */ \ 235 MOCS_ENTRY(62, \ 236 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ 237 L3_1_UC), \ 238 /* HW Reserved - SW program but never use */ \ 239 MOCS_ENTRY(63, \ 240 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ 241 L3_1_UC) 242 243 static const struct drm_i915_mocs_entry tgl_mocs_table[] = { 244 /* 245 * NOTE: 246 * Reserved and unspecified MOCS indices have been set to (L3 + LCC). 247 * These reserved entries should never be used, they may be changed 248 * to low performant variants with better coherency in the future if 249 * more entries are needed. We are programming index I915_MOCS_PTE(1) 250 * only, __init_mocs_table() take care to program unused index with 251 * this entry. 252 */ 253 MOCS_ENTRY(I915_MOCS_PTE, 254 LE_0_PAGETABLE | LE_TC_0_PAGETABLE, 255 L3_1_UC), 256 GEN11_MOCS_ENTRIES, 257 258 /* Implicitly enable L1 - HDC:L1 + L3 + LLC */ 259 MOCS_ENTRY(48, 260 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), 261 L3_3_WB), 262 /* Implicitly enable L1 - HDC:L1 + L3 */ 263 MOCS_ENTRY(49, 264 LE_1_UC | LE_TC_1_LLC, 265 L3_3_WB), 266 /* Implicitly enable L1 - HDC:L1 + LLC */ 267 MOCS_ENTRY(50, 268 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), 269 L3_1_UC), 270 /* Implicitly enable L1 - HDC:L1 */ 271 MOCS_ENTRY(51, 272 LE_1_UC | LE_TC_1_LLC, 273 L3_1_UC), 274 /* HW Special Case (CCS) */ 275 MOCS_ENTRY(60, 276 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), 277 L3_1_UC), 278 /* HW Special Case (Displayable) */ 279 MOCS_ENTRY(61, 280 LE_1_UC | LE_TC_1_LLC, 281 L3_3_WB), 282 }; 283 284 static const struct drm_i915_mocs_entry icl_mocs_table[] = { 285 /* Base - Uncached (Deprecated) */ 286 MOCS_ENTRY(I915_MOCS_UNCACHED, 287 LE_1_UC | LE_TC_1_LLC, 288 L3_1_UC), 289 /* Base - L3 + LeCC:PAT (Deprecated) */ 290 MOCS_ENTRY(I915_MOCS_PTE, 291 LE_0_PAGETABLE | LE_TC_0_PAGETABLE, 292 L3_3_WB), 293 294 GEN11_MOCS_ENTRIES 295 }; 296 297 static const struct drm_i915_mocs_entry dg1_mocs_table[] = { 298 299 /* UC */ 300 MOCS_ENTRY(1, 0, L3_1_UC), 301 /* WB - L3 */ 302 MOCS_ENTRY(5, 0, L3_3_WB), 303 /* WB - L3 50% */ 304 MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB), 305 /* WB - L3 25% */ 306 MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB), 307 /* WB - L3 12.5% */ 308 MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB), 309 310 /* HDC:L1 + L3 */ 311 MOCS_ENTRY(48, 0, L3_3_WB), 312 /* HDC:L1 */ 313 MOCS_ENTRY(49, 0, L3_1_UC), 314 315 /* HW Reserved */ 316 MOCS_ENTRY(60, 0, L3_1_UC), 317 MOCS_ENTRY(61, 0, L3_1_UC), 318 MOCS_ENTRY(62, 0, L3_1_UC), 319 MOCS_ENTRY(63, 0, L3_1_UC), 320 }; 321 322 static const struct drm_i915_mocs_entry gen12_mocs_table[] = { 323 GEN11_MOCS_ENTRIES, 324 /* Implicitly enable L1 - HDC:L1 + L3 + LLC */ 325 MOCS_ENTRY(48, 326 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), 327 L3_3_WB), 328 /* Implicitly enable L1 - HDC:L1 + L3 */ 329 MOCS_ENTRY(49, 330 LE_1_UC | LE_TC_1_LLC, 331 L3_3_WB), 332 /* Implicitly enable L1 - HDC:L1 + LLC */ 333 MOCS_ENTRY(50, 334 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), 335 L3_1_UC), 336 /* Implicitly enable L1 - HDC:L1 */ 337 MOCS_ENTRY(51, 338 LE_1_UC | LE_TC_1_LLC, 339 L3_1_UC), 340 /* HW Special Case (CCS) */ 341 MOCS_ENTRY(60, 342 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), 343 L3_1_UC), 344 /* HW Special Case (Displayable) */ 345 MOCS_ENTRY(61, 346 LE_1_UC | LE_TC_1_LLC, 347 L3_3_WB), 348 }; 349 350 static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = { 351 /* wa_1608975824 */ 352 MOCS_ENTRY(0, 0, L3_3_WB | L3_LKUP(1)), 353 354 /* UC - Coherent; GO:L3 */ 355 MOCS_ENTRY(1, 0, L3_1_UC | L3_LKUP(1)), 356 /* UC - Coherent; GO:Memory */ 357 MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)), 358 /* UC - Non-Coherent; GO:Memory */ 359 MOCS_ENTRY(3, 0, L3_1_UC | L3_GLBGO(1)), 360 /* UC - Non-Coherent; GO:L3 */ 361 MOCS_ENTRY(4, 0, L3_1_UC), 362 363 /* WB */ 364 MOCS_ENTRY(5, 0, L3_3_WB | L3_LKUP(1)), 365 366 /* HW Reserved - SW program but never use. */ 367 MOCS_ENTRY(48, 0, L3_3_WB | L3_LKUP(1)), 368 MOCS_ENTRY(49, 0, L3_1_UC | L3_LKUP(1)), 369 MOCS_ENTRY(60, 0, L3_1_UC), 370 MOCS_ENTRY(61, 0, L3_1_UC), 371 MOCS_ENTRY(62, 0, L3_1_UC), 372 MOCS_ENTRY(63, 0, L3_1_UC), 373 }; 374 375 static const struct drm_i915_mocs_entry dg2_mocs_table[] = { 376 /* UC - Coherent; GO:L3 */ 377 MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)), 378 /* UC - Coherent; GO:Memory */ 379 MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)), 380 /* UC - Non-Coherent; GO:Memory */ 381 MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)), 382 383 /* WB - LC */ 384 MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)), 385 }; 386 387 static const struct drm_i915_mocs_entry dg2_mocs_table_g10_ax[] = { 388 /* Wa_14011441408: Set Go to Memory for MOCS#0 */ 389 MOCS_ENTRY(0, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)), 390 /* UC - Coherent; GO:Memory */ 391 MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)), 392 /* UC - Non-Coherent; GO:Memory */ 393 MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)), 394 395 /* WB - LC */ 396 MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)), 397 }; 398 399 static const struct drm_i915_mocs_entry pvc_mocs_table[] = { 400 /* Error */ 401 MOCS_ENTRY(0, 0, L3_3_WB), 402 403 /* UC */ 404 MOCS_ENTRY(1, 0, L3_1_UC), 405 406 /* WB */ 407 MOCS_ENTRY(2, 0, L3_3_WB), 408 }; 409 410 enum { 411 HAS_GLOBAL_MOCS = BIT(0), 412 HAS_ENGINE_MOCS = BIT(1), 413 HAS_RENDER_L3CC = BIT(2), 414 }; 415 416 static bool has_l3cc(const struct drm_i915_private *i915) 417 { 418 return true; 419 } 420 421 static bool has_global_mocs(const struct drm_i915_private *i915) 422 { 423 return HAS_GLOBAL_MOCS_REGISTERS(i915); 424 } 425 426 static bool has_mocs(const struct drm_i915_private *i915) 427 { 428 return !IS_DGFX(i915); 429 } 430 431 static unsigned int get_mocs_settings(const struct drm_i915_private *i915, 432 struct drm_i915_mocs_table *table) 433 { 434 unsigned int flags; 435 436 memset(table, 0, sizeof(struct drm_i915_mocs_table)); 437 438 table->unused_entries_index = I915_MOCS_PTE; 439 if (IS_PONTEVECCHIO(i915)) { 440 table->size = ARRAY_SIZE(pvc_mocs_table); 441 table->table = pvc_mocs_table; 442 table->n_entries = PVC_NUM_MOCS_ENTRIES; 443 table->uc_index = 1; 444 table->wb_index = 2; 445 table->unused_entries_index = 2; 446 } else if (IS_DG2(i915)) { 447 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 448 table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax); 449 table->table = dg2_mocs_table_g10_ax; 450 } else { 451 table->size = ARRAY_SIZE(dg2_mocs_table); 452 table->table = dg2_mocs_table; 453 } 454 table->uc_index = 1; 455 table->n_entries = GEN9_NUM_MOCS_ENTRIES; 456 table->unused_entries_index = 3; 457 } else if (IS_XEHPSDV(i915)) { 458 table->size = ARRAY_SIZE(xehpsdv_mocs_table); 459 table->table = xehpsdv_mocs_table; 460 table->uc_index = 2; 461 table->n_entries = GEN9_NUM_MOCS_ENTRIES; 462 table->unused_entries_index = 5; 463 } else if (IS_DG1(i915)) { 464 table->size = ARRAY_SIZE(dg1_mocs_table); 465 table->table = dg1_mocs_table; 466 table->uc_index = 1; 467 table->n_entries = GEN9_NUM_MOCS_ENTRIES; 468 table->uc_index = 1; 469 table->unused_entries_index = 5; 470 } else if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) { 471 /* For TGL/RKL, Can't be changed now for ABI reasons */ 472 table->size = ARRAY_SIZE(tgl_mocs_table); 473 table->table = tgl_mocs_table; 474 table->n_entries = GEN9_NUM_MOCS_ENTRIES; 475 table->uc_index = 3; 476 } else if (GRAPHICS_VER(i915) >= 12) { 477 table->size = ARRAY_SIZE(gen12_mocs_table); 478 table->table = gen12_mocs_table; 479 table->n_entries = GEN9_NUM_MOCS_ENTRIES; 480 table->uc_index = 3; 481 table->unused_entries_index = 2; 482 } else if (GRAPHICS_VER(i915) == 11) { 483 table->size = ARRAY_SIZE(icl_mocs_table); 484 table->table = icl_mocs_table; 485 table->n_entries = GEN9_NUM_MOCS_ENTRIES; 486 } else if (IS_GEN9_BC(i915)) { 487 table->size = ARRAY_SIZE(skl_mocs_table); 488 table->n_entries = GEN9_NUM_MOCS_ENTRIES; 489 table->table = skl_mocs_table; 490 } else if (IS_GEN9_LP(i915)) { 491 table->size = ARRAY_SIZE(broxton_mocs_table); 492 table->n_entries = GEN9_NUM_MOCS_ENTRIES; 493 table->table = broxton_mocs_table; 494 } else { 495 drm_WARN_ONCE(&i915->drm, GRAPHICS_VER(i915) >= 9, 496 "Platform that should have a MOCS table does not.\n"); 497 return 0; 498 } 499 500 if (GEM_DEBUG_WARN_ON(table->size > table->n_entries)) 501 return 0; 502 503 /* WaDisableSkipCaching:skl,bxt,kbl,glk */ 504 if (GRAPHICS_VER(i915) == 9) { 505 int i; 506 507 for (i = 0; i < table->size; i++) 508 if (GEM_DEBUG_WARN_ON(table->table[i].l3cc_value & 509 (L3_ESC(1) | L3_SCC(0x7)))) 510 return 0; 511 } 512 513 flags = 0; 514 if (has_mocs(i915)) { 515 if (has_global_mocs(i915)) 516 flags |= HAS_GLOBAL_MOCS; 517 else 518 flags |= HAS_ENGINE_MOCS; 519 } 520 if (has_l3cc(i915)) 521 flags |= HAS_RENDER_L3CC; 522 523 return flags; 524 } 525 526 /* 527 * Get control_value from MOCS entry taking into account when it's not used 528 * then if unused_entries_index is non-zero then its value will be returned 529 * otherwise I915_MOCS_PTE's value is returned in this case. 530 */ 531 static u32 get_entry_control(const struct drm_i915_mocs_table *table, 532 unsigned int index) 533 { 534 if (index < table->size && table->table[index].used) 535 return table->table[index].control_value; 536 return table->table[table->unused_entries_index].control_value; 537 } 538 539 #define for_each_mocs(mocs, t, i) \ 540 for (i = 0; \ 541 i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\ 542 i++) 543 544 static void __init_mocs_table(struct intel_uncore *uncore, 545 const struct drm_i915_mocs_table *table, 546 u32 addr) 547 { 548 unsigned int i; 549 u32 mocs; 550 551 drm_WARN_ONCE(&uncore->i915->drm, !table->unused_entries_index, 552 "Unused entries index should have been defined\n"); 553 for_each_mocs(mocs, table, i) 554 intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs); 555 } 556 557 static u32 mocs_offset(const struct intel_engine_cs *engine) 558 { 559 static const u32 offset[] = { 560 [RCS0] = __GEN9_RCS0_MOCS0, 561 [VCS0] = __GEN9_VCS0_MOCS0, 562 [VCS1] = __GEN9_VCS1_MOCS0, 563 [VECS0] = __GEN9_VECS0_MOCS0, 564 [BCS0] = __GEN9_BCS0_MOCS0, 565 [VCS2] = __GEN11_VCS2_MOCS0, 566 }; 567 568 GEM_BUG_ON(engine->id >= ARRAY_SIZE(offset)); 569 return offset[engine->id]; 570 } 571 572 static void init_mocs_table(struct intel_engine_cs *engine, 573 const struct drm_i915_mocs_table *table) 574 { 575 __init_mocs_table(engine->uncore, table, mocs_offset(engine)); 576 } 577 578 /* 579 * Get l3cc_value from MOCS entry taking into account when it's not used 580 * then if unused_entries_index is not zero then its value will be returned 581 * otherwise I915_MOCS_PTE's value is returned in this case. 582 */ 583 static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table, 584 unsigned int index) 585 { 586 if (index < table->size && table->table[index].used) 587 return table->table[index].l3cc_value; 588 return table->table[table->unused_entries_index].l3cc_value; 589 } 590 591 static u32 l3cc_combine(u16 low, u16 high) 592 { 593 return low | (u32)high << 16; 594 } 595 596 #define for_each_l3cc(l3cc, t, i) \ 597 for (i = 0; \ 598 i < ((t)->n_entries + 1) / 2 ? \ 599 (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \ 600 get_entry_l3cc((t), 2 * i + 1))), 1 : \ 601 0; \ 602 i++) 603 604 static void init_l3cc_table(struct intel_uncore *uncore, 605 const struct drm_i915_mocs_table *table) 606 { 607 unsigned int i; 608 u32 l3cc; 609 610 for_each_l3cc(l3cc, table, i) 611 intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc); 612 } 613 614 void intel_mocs_init_engine(struct intel_engine_cs *engine) 615 { 616 struct drm_i915_mocs_table table; 617 unsigned int flags; 618 619 /* Called under a blanket forcewake */ 620 assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL); 621 622 flags = get_mocs_settings(engine->i915, &table); 623 if (!flags) 624 return; 625 626 /* Platforms with global MOCS do not need per-engine initialization. */ 627 if (flags & HAS_ENGINE_MOCS) 628 init_mocs_table(engine, &table); 629 630 if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS) 631 init_l3cc_table(engine->uncore, &table); 632 } 633 634 static u32 global_mocs_offset(void) 635 { 636 return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0)); 637 } 638 639 void intel_set_mocs_index(struct intel_gt *gt) 640 { 641 struct drm_i915_mocs_table table; 642 643 get_mocs_settings(gt->i915, &table); 644 gt->mocs.uc_index = table.uc_index; 645 if (HAS_L3_CCS_READ(gt->i915)) 646 gt->mocs.wb_index = table.wb_index; 647 } 648 649 void intel_mocs_init(struct intel_gt *gt) 650 { 651 struct drm_i915_mocs_table table; 652 unsigned int flags; 653 654 /* 655 * LLC and eDRAM control values are not applicable to dgfx 656 */ 657 flags = get_mocs_settings(gt->i915, &table); 658 if (flags & HAS_GLOBAL_MOCS) 659 __init_mocs_table(gt->uncore, &table, global_mocs_offset()); 660 661 /* 662 * Initialize the L3CC table as part of mocs initalization to make 663 * sure the LNCFCMOCSx registers are programmed for the subsequent 664 * memory transactions including guc transactions 665 */ 666 if (flags & HAS_RENDER_L3CC) 667 init_l3cc_table(gt->uncore, &table); 668 } 669 670 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 671 #include "selftest_mocs.c" 672 #endif 673