1 /*
2  * SPDX-License-Identifier: MIT
3  *
4  * Copyright © 2014-2018 Intel Corporation
5  */
6 
7 #ifndef _INTEL_LRC_REG_H_
8 #define _INTEL_LRC_REG_H_
9 
10 #include <linux/types.h>
11 
12 /* GEN8 to GEN11 Reg State Context */
13 #define CTX_CONTEXT_CONTROL		(0x02 + 1)
14 #define CTX_RING_HEAD			(0x04 + 1)
15 #define CTX_RING_TAIL			(0x06 + 1)
16 #define CTX_RING_START			(0x08 + 1)
17 #define CTX_RING_CTL			(0x0a + 1)
18 #define CTX_BB_STATE			(0x10 + 1)
19 #define CTX_BB_PER_CTX_PTR		(0x18 + 1)
20 #define CTX_TIMESTAMP			(0x22 + 1)
21 #define CTX_PDP3_UDW			(0x24 + 1)
22 #define CTX_PDP3_LDW			(0x26 + 1)
23 #define CTX_PDP2_UDW			(0x28 + 1)
24 #define CTX_PDP2_LDW			(0x2a + 1)
25 #define CTX_PDP1_UDW			(0x2c + 1)
26 #define CTX_PDP1_LDW			(0x2e + 1)
27 #define CTX_PDP0_UDW			(0x30 + 1)
28 #define CTX_PDP0_LDW			(0x32 + 1)
29 #define CTX_R_PWR_CLK_STATE		(0x42 + 1)
30 
31 #define GEN9_CTX_RING_MI_MODE		0x54
32 
33 /* GEN12+ Reg State Context */
34 #define GEN12_CTX_BB_PER_CTX_PTR		(0x12 + 1)
35 
36 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
37 	u32 *reg_state__ = (reg_state); \
38 	const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \
39 	(reg_state__)[CTX_PDP ## n ## _UDW] = upper_32_bits(addr__); \
40 	(reg_state__)[CTX_PDP ## n ## _LDW] = lower_32_bits(addr__); \
41 } while (0)
42 
43 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
44 	u32 *reg_state__ = (reg_state); \
45 	const u64 addr__ = px_dma(ppgtt->pd); \
46 	(reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \
47 	(reg_state__)[CTX_PDP0_LDW] = lower_32_bits(addr__); \
48 } while (0)
49 
50 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
51 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
52 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x19
53 #define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x1A
54 #define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0xD
55 
56 #endif /* _INTEL_LRC_REG_H_ */
57