1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2014-2018 Intel Corporation 5 */ 6 7 #ifndef _INTEL_LRC_REG_H_ 8 #define _INTEL_LRC_REG_H_ 9 10 #include <linux/types.h> 11 12 #define CTX_DESC_FORCE_RESTORE BIT_ULL(2) 13 14 /* GEN8 to GEN12 Reg State Context */ 15 #define CTX_CONTEXT_CONTROL (0x02 + 1) 16 #define CTX_RING_HEAD (0x04 + 1) 17 #define CTX_RING_TAIL (0x06 + 1) 18 #define CTX_RING_START (0x08 + 1) 19 #define CTX_RING_CTL (0x0a + 1) 20 #define CTX_BB_STATE (0x10 + 1) 21 #define CTX_TIMESTAMP (0x22 + 1) 22 #define CTX_PDP3_UDW (0x24 + 1) 23 #define CTX_PDP3_LDW (0x26 + 1) 24 #define CTX_PDP2_UDW (0x28 + 1) 25 #define CTX_PDP2_LDW (0x2a + 1) 26 #define CTX_PDP1_UDW (0x2c + 1) 27 #define CTX_PDP1_LDW (0x2e + 1) 28 #define CTX_PDP0_UDW (0x30 + 1) 29 #define CTX_PDP0_LDW (0x32 + 1) 30 #define CTX_R_PWR_CLK_STATE (0x42 + 1) 31 32 #define GEN9_CTX_RING_MI_MODE 0x54 33 34 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ 35 u32 *reg_state__ = (reg_state); \ 36 const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \ 37 (reg_state__)[CTX_PDP ## n ## _UDW] = upper_32_bits(addr__); \ 38 (reg_state__)[CTX_PDP ## n ## _LDW] = lower_32_bits(addr__); \ 39 } while (0) 40 41 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ 42 u32 *reg_state__ = (reg_state); \ 43 const u64 addr__ = px_dma(ppgtt->pd); \ 44 (reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \ 45 (reg_state__)[CTX_PDP0_LDW] = lower_32_bits(addr__); \ 46 } while (0) 47 48 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 49 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 50 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19 51 #define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1A 52 #define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0xD 53 54 #define GEN8_EXECLISTS_STATUS_BUF 0x370 55 #define GEN11_EXECLISTS_STATUS_BUF2 0x3c0 56 57 /* Execlists regs */ 58 #define RING_ELSP(base) _MMIO((base) + 0x230) 59 #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234) 60 #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4) 61 #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244) 62 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0) 63 #define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1) 64 #define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2) 65 #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3) 66 #define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8) 67 #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0) 68 #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510) 69 #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550) 70 #define EL_CTRL_LOAD REG_BIT(0) 71 72 /* 73 * The docs specify that the write pointer wraps around after 5h, "After status 74 * is written out to the last available status QW at offset 5h, this pointer 75 * wraps to 0." 76 * 77 * Therefore, one must infer than even though there are 3 bits available, 6 and 78 * 7 appear to be * reserved. 79 */ 80 #define GEN8_CSB_ENTRIES 6 81 #define GEN8_CSB_PTR_MASK 0x7 82 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8) 83 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0) 84 85 #define GEN11_CSB_ENTRIES 12 86 #define GEN11_CSB_PTR_MASK 0xf 87 #define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8) 88 #define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0) 89 90 #define MAX_CONTEXT_HW_ID (1 << 21) /* exclusive */ 91 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */ 92 #define GEN11_MAX_CONTEXT_HW_ID (1 << 11) /* exclusive */ 93 /* in Gen12 ID 0x7FF is reserved to indicate idle */ 94 #define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1) 95 96 #endif /* _INTEL_LRC_REG_H_ */ 97