1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014 Intel Corporation 4 */ 5 6 #ifndef __INTEL_LRC_H__ 7 #define __INTEL_LRC_H__ 8 9 #include "i915_priolist_types.h" 10 11 #include <linux/bitfield.h> 12 #include <linux/types.h> 13 14 #include "intel_context.h" 15 16 struct drm_i915_gem_object; 17 struct i915_gem_ww_ctx; 18 struct intel_engine_cs; 19 struct intel_ring; 20 struct kref; 21 22 /* At the start of the context image is its per-process HWS page */ 23 #define LRC_PPHWSP_PN (0) 24 #define LRC_PPHWSP_SZ (1) 25 /* After the PPHWSP we have the logical state for the context */ 26 #define LRC_STATE_PN (LRC_PPHWSP_PN + LRC_PPHWSP_SZ) 27 #define LRC_STATE_OFFSET (LRC_STATE_PN * PAGE_SIZE) 28 29 /* Space within PPHWSP reserved to be used as scratch */ 30 #define LRC_PPHWSP_SCRATCH 0x34 31 #define LRC_PPHWSP_SCRATCH_ADDR (LRC_PPHWSP_SCRATCH * sizeof(u32)) 32 33 void lrc_init_wa_ctx(struct intel_engine_cs *engine); 34 void lrc_fini_wa_ctx(struct intel_engine_cs *engine); 35 36 int lrc_alloc(struct intel_context *ce, 37 struct intel_engine_cs *engine); 38 void lrc_reset(struct intel_context *ce); 39 void lrc_fini(struct intel_context *ce); 40 void lrc_destroy(struct kref *kref); 41 42 int 43 lrc_pre_pin(struct intel_context *ce, 44 struct intel_engine_cs *engine, 45 struct i915_gem_ww_ctx *ww, 46 void **vaddr); 47 int 48 lrc_pin(struct intel_context *ce, 49 struct intel_engine_cs *engine, 50 void *vaddr); 51 void lrc_unpin(struct intel_context *ce); 52 void lrc_post_unpin(struct intel_context *ce); 53 54 void lrc_init_state(struct intel_context *ce, 55 struct intel_engine_cs *engine, 56 void *state); 57 58 void lrc_init_regs(const struct intel_context *ce, 59 const struct intel_engine_cs *engine, 60 bool clear); 61 void lrc_reset_regs(const struct intel_context *ce, 62 const struct intel_engine_cs *engine); 63 64 u32 lrc_update_regs(const struct intel_context *ce, 65 const struct intel_engine_cs *engine, 66 u32 head); 67 void lrc_update_offsets(struct intel_context *ce, 68 struct intel_engine_cs *engine); 69 70 void lrc_check_regs(const struct intel_context *ce, 71 const struct intel_engine_cs *engine, 72 const char *when); 73 74 void lrc_update_runtime(struct intel_context *ce); 75 76 enum { 77 INTEL_ADVANCED_CONTEXT = 0, 78 INTEL_LEGACY_32B_CONTEXT, 79 INTEL_ADVANCED_AD_CONTEXT, 80 INTEL_LEGACY_64B_CONTEXT 81 }; 82 83 enum { 84 FAULT_AND_HANG = 0, 85 FAULT_AND_HALT, /* Debug only */ 86 FAULT_AND_STREAM, 87 FAULT_AND_CONTINUE /* Unsupported */ 88 }; 89 90 #define CTX_GTT_ADDRESS_MASK GENMASK(31, 12) 91 #define GEN8_CTX_VALID (1 << 0) 92 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1) 93 #define GEN8_CTX_FORCE_RESTORE (1 << 2) 94 #define GEN8_CTX_L3LLC_COHERENT (1 << 5) 95 #define GEN8_CTX_PRIVILEGE (1 << 8) 96 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 97 #define GEN12_CTX_PRIORITY_MASK GENMASK(10, 9) 98 #define GEN12_CTX_PRIORITY_HIGH FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2) 99 #define GEN12_CTX_PRIORITY_NORMAL FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1) 100 #define GEN12_CTX_PRIORITY_LOW FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0) 101 #define GEN8_CTX_ID_SHIFT 32 102 #define GEN8_CTX_ID_WIDTH 21 103 #define GEN11_SW_CTX_ID_SHIFT 37 104 #define GEN11_SW_CTX_ID_WIDTH 11 105 #define GEN11_ENGINE_CLASS_SHIFT 61 106 #define GEN11_ENGINE_CLASS_WIDTH 3 107 #define GEN11_ENGINE_INSTANCE_SHIFT 48 108 #define GEN11_ENGINE_INSTANCE_WIDTH 6 109 #define XEHP_SW_CTX_ID_SHIFT 39 110 #define XEHP_SW_CTX_ID_WIDTH 16 111 #define XEHP_SW_COUNTER_SHIFT 58 112 #define XEHP_SW_COUNTER_WIDTH 6 113 #define GEN12_GUC_SW_CTX_ID_SHIFT 39 114 #define GEN12_GUC_SW_CTX_ID_WIDTH 16 115 116 static inline void lrc_runtime_start(struct intel_context *ce) 117 { 118 struct intel_context_stats *stats = &ce->stats; 119 120 if (intel_context_is_barrier(ce)) 121 return; 122 123 if (stats->active) 124 return; 125 126 WRITE_ONCE(stats->active, intel_context_clock()); 127 } 128 129 static inline void lrc_runtime_stop(struct intel_context *ce) 130 { 131 struct intel_context_stats *stats = &ce->stats; 132 133 if (!stats->active) 134 return; 135 136 lrc_update_runtime(ce); 137 WRITE_ONCE(stats->active, 0); 138 } 139 140 #define DG2_PREDICATE_RESULT_WA (PAGE_SIZE - sizeof(u64)) 141 #define DG2_PREDICATE_RESULT_BB (2048) 142 143 u32 lrc_indirect_bb(const struct intel_context *ce); 144 145 #endif /* __INTEL_LRC_H__ */ 146