1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _INTEL_LRC_H_ 25 #define _INTEL_LRC_H_ 26 27 #include <linux/types.h> 28 29 struct drm_printer; 30 31 struct drm_i915_private; 32 struct i915_gem_context; 33 struct i915_request; 34 struct intel_context; 35 struct intel_engine_cs; 36 37 /* Execlists regs */ 38 #define RING_ELSP(base) _MMIO((base) + 0x230) 39 #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234) 40 #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4) 41 #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244) 42 #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3) 43 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0) 44 #define CTX_CTRL_RS_CTX_ENABLE (1 << 1) 45 #define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2) 46 #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0) 47 #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510) 48 #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550) 49 50 #define EL_CTRL_LOAD (1 << 0) 51 52 /* The docs specify that the write pointer wraps around after 5h, "After status 53 * is written out to the last available status QW at offset 5h, this pointer 54 * wraps to 0." 55 * 56 * Therefore, one must infer than even though there are 3 bits available, 6 and 57 * 7 appear to be * reserved. 58 */ 59 #define GEN8_CSB_ENTRIES 6 60 #define GEN8_CSB_PTR_MASK 0x7 61 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8) 62 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0) 63 64 #define GEN11_CSB_ENTRIES 12 65 #define GEN11_CSB_PTR_MASK 0xf 66 #define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8) 67 #define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0) 68 69 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ 70 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */ 71 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ 72 /* in Gen12 ID 0x7FF is reserved to indicate idle */ 73 #define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1) 74 75 enum { 76 INTEL_CONTEXT_SCHEDULE_IN = 0, 77 INTEL_CONTEXT_SCHEDULE_OUT, 78 INTEL_CONTEXT_SCHEDULE_PREEMPTED, 79 }; 80 81 /* Logical Rings */ 82 void intel_logical_ring_cleanup(struct intel_engine_cs *engine); 83 84 int intel_execlists_submission_setup(struct intel_engine_cs *engine); 85 int intel_execlists_submission_init(struct intel_engine_cs *engine); 86 87 /* Logical Ring Contexts */ 88 89 /* 90 * We allocate a header at the start of the context image for our own 91 * use, therefore the actual location of the logical state is offset 92 * from the start of the VMA. The layout is 93 * 94 * | [guc] | [hwsp] [logical state] | 95 * |<- our header ->|<- context image ->| 96 * 97 */ 98 /* The first page is used for sharing data with the GuC */ 99 #define LRC_GUCSHR_PN (0) 100 #define LRC_GUCSHR_SZ (1) 101 /* At the start of the context image is its per-process HWS page */ 102 #define LRC_PPHWSP_PN (LRC_GUCSHR_PN + LRC_GUCSHR_SZ) 103 #define LRC_PPHWSP_SZ (1) 104 /* Finally we have the logical state for the context */ 105 #define LRC_STATE_PN (LRC_PPHWSP_PN + LRC_PPHWSP_SZ) 106 107 /* 108 * Currently we include the PPHWSP in __intel_engine_context_size() so 109 * the size of the header is synonymous with the start of the PPHWSP. 110 */ 111 #define LRC_HEADER_PAGES LRC_PPHWSP_PN 112 113 /* Space within PPHWSP reserved to be used as scratch */ 114 #define LRC_PPHWSP_SCRATCH 0x34 115 #define LRC_PPHWSP_SCRATCH_ADDR (LRC_PPHWSP_SCRATCH * sizeof(u32)) 116 117 void intel_execlists_set_default_submission(struct intel_engine_cs *engine); 118 119 void intel_lr_context_reset(struct intel_engine_cs *engine, 120 struct intel_context *ce, 121 u32 head, 122 bool scrub); 123 124 void intel_execlists_show_requests(struct intel_engine_cs *engine, 125 struct drm_printer *m, 126 void (*show_request)(struct drm_printer *m, 127 struct i915_request *rq, 128 const char *prefix), 129 unsigned int max); 130 131 struct intel_context * 132 intel_execlists_create_virtual(struct i915_gem_context *ctx, 133 struct intel_engine_cs **siblings, 134 unsigned int count); 135 136 struct intel_context * 137 intel_execlists_clone_virtual(struct i915_gem_context *ctx, 138 struct intel_engine_cs *src); 139 140 int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine, 141 const struct intel_engine_cs *master, 142 const struct intel_engine_cs *sibling); 143 144 struct intel_engine_cs * 145 intel_virtual_engine_get_sibling(struct intel_engine_cs *engine, 146 unsigned int sibling); 147 148 #endif /* _INTEL_LRC_H_ */ 149