1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014 Intel Corporation 4 */ 5 6 #ifndef __INTEL_LRC_H__ 7 #define __INTEL_LRC_H__ 8 9 #include "i915_priolist_types.h" 10 11 #include <linux/bitfield.h> 12 #include <linux/types.h> 13 14 struct drm_i915_gem_object; 15 struct i915_gem_ww_ctx; 16 struct intel_context; 17 struct intel_engine_cs; 18 struct intel_ring; 19 struct kref; 20 21 /* At the start of the context image is its per-process HWS page */ 22 #define LRC_PPHWSP_PN (0) 23 #define LRC_PPHWSP_SZ (1) 24 /* After the PPHWSP we have the logical state for the context */ 25 #define LRC_STATE_PN (LRC_PPHWSP_PN + LRC_PPHWSP_SZ) 26 #define LRC_STATE_OFFSET (LRC_STATE_PN * PAGE_SIZE) 27 28 /* Space within PPHWSP reserved to be used as scratch */ 29 #define LRC_PPHWSP_SCRATCH 0x34 30 #define LRC_PPHWSP_SCRATCH_ADDR (LRC_PPHWSP_SCRATCH * sizeof(u32)) 31 32 void lrc_init_wa_ctx(struct intel_engine_cs *engine); 33 void lrc_fini_wa_ctx(struct intel_engine_cs *engine); 34 35 int lrc_alloc(struct intel_context *ce, 36 struct intel_engine_cs *engine); 37 void lrc_reset(struct intel_context *ce); 38 void lrc_fini(struct intel_context *ce); 39 void lrc_destroy(struct kref *kref); 40 41 int 42 lrc_pre_pin(struct intel_context *ce, 43 struct intel_engine_cs *engine, 44 struct i915_gem_ww_ctx *ww, 45 void **vaddr); 46 int 47 lrc_pin(struct intel_context *ce, 48 struct intel_engine_cs *engine, 49 void *vaddr); 50 void lrc_unpin(struct intel_context *ce); 51 void lrc_post_unpin(struct intel_context *ce); 52 53 void lrc_init_state(struct intel_context *ce, 54 struct intel_engine_cs *engine, 55 void *state); 56 57 void lrc_init_regs(const struct intel_context *ce, 58 const struct intel_engine_cs *engine, 59 bool clear); 60 void lrc_reset_regs(const struct intel_context *ce, 61 const struct intel_engine_cs *engine); 62 63 u32 lrc_update_regs(const struct intel_context *ce, 64 const struct intel_engine_cs *engine, 65 u32 head); 66 void lrc_update_offsets(struct intel_context *ce, 67 struct intel_engine_cs *engine); 68 69 void lrc_check_regs(const struct intel_context *ce, 70 const struct intel_engine_cs *engine, 71 const char *when); 72 73 void lrc_update_runtime(struct intel_context *ce); 74 75 enum { 76 INTEL_ADVANCED_CONTEXT = 0, 77 INTEL_LEGACY_32B_CONTEXT, 78 INTEL_ADVANCED_AD_CONTEXT, 79 INTEL_LEGACY_64B_CONTEXT 80 }; 81 82 enum { 83 FAULT_AND_HANG = 0, 84 FAULT_AND_HALT, /* Debug only */ 85 FAULT_AND_STREAM, 86 FAULT_AND_CONTINUE /* Unsupported */ 87 }; 88 89 #define CTX_GTT_ADDRESS_MASK GENMASK(31, 12) 90 #define GEN8_CTX_VALID (1 << 0) 91 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1) 92 #define GEN8_CTX_FORCE_RESTORE (1 << 2) 93 #define GEN8_CTX_L3LLC_COHERENT (1 << 5) 94 #define GEN8_CTX_PRIVILEGE (1 << 8) 95 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 96 #define GEN12_CTX_PRIORITY_MASK GENMASK(10, 9) 97 #define GEN12_CTX_PRIORITY_HIGH FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2) 98 #define GEN12_CTX_PRIORITY_NORMAL FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1) 99 #define GEN12_CTX_PRIORITY_LOW FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0) 100 #define GEN8_CTX_ID_SHIFT 32 101 #define GEN8_CTX_ID_WIDTH 21 102 #define GEN11_SW_CTX_ID_SHIFT 37 103 #define GEN11_SW_CTX_ID_WIDTH 11 104 #define GEN11_ENGINE_CLASS_SHIFT 61 105 #define GEN11_ENGINE_CLASS_WIDTH 3 106 #define GEN11_ENGINE_INSTANCE_SHIFT 48 107 #define GEN11_ENGINE_INSTANCE_WIDTH 6 108 #define XEHP_SW_CTX_ID_SHIFT 39 109 #define XEHP_SW_CTX_ID_WIDTH 16 110 #define XEHP_SW_COUNTER_SHIFT 58 111 #define XEHP_SW_COUNTER_WIDTH 6 112 113 static inline u32 lrc_desc_priority(int prio) 114 { 115 if (prio > I915_PRIORITY_NORMAL) 116 return GEN12_CTX_PRIORITY_HIGH; 117 else if (prio < I915_PRIORITY_NORMAL) 118 return GEN12_CTX_PRIORITY_LOW; 119 else 120 return GEN12_CTX_PRIORITY_NORMAL; 121 } 122 123 #endif /* __INTEL_LRC_H__ */ 124