1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * Michel Thierry <michel.thierry@intel.com> 26 * Thomas Daniel <thomas.daniel@intel.com> 27 * Oscar Mateo <oscar.mateo@intel.com> 28 * 29 */ 30 31 /** 32 * DOC: Logical Rings, Logical Ring Contexts and Execlists 33 * 34 * Motivation: 35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". 36 * These expanded contexts enable a number of new abilities, especially 37 * "Execlists" (also implemented in this file). 38 * 39 * One of the main differences with the legacy HW contexts is that logical 40 * ring contexts incorporate many more things to the context's state, like 41 * PDPs or ringbuffer control registers: 42 * 43 * The reason why PDPs are included in the context is straightforward: as 44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs 45 * contained there mean you don't need to do a ppgtt->switch_mm yourself, 46 * instead, the GPU will do it for you on the context switch. 47 * 48 * But, what about the ringbuffer control registers (head, tail, etc..)? 49 * shouldn't we just need a set of those per engine command streamer? This is 50 * where the name "Logical Rings" starts to make sense: by virtualizing the 51 * rings, the engine cs shifts to a new "ring buffer" with every context 52 * switch. When you want to submit a workload to the GPU you: A) choose your 53 * context, B) find its appropriate virtualized ring, C) write commands to it 54 * and then, finally, D) tell the GPU to switch to that context. 55 * 56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch 57 * to a contexts is via a context execution list, ergo "Execlists". 58 * 59 * LRC implementation: 60 * Regarding the creation of contexts, we have: 61 * 62 * - One global default context. 63 * - One local default context for each opened fd. 64 * - One local extra context for each context create ioctl call. 65 * 66 * Now that ringbuffers belong per-context (and not per-engine, like before) 67 * and that contexts are uniquely tied to a given engine (and not reusable, 68 * like before) we need: 69 * 70 * - One ringbuffer per-engine inside each context. 71 * - One backing object per-engine inside each context. 72 * 73 * The global default context starts its life with these new objects fully 74 * allocated and populated. The local default context for each opened fd is 75 * more complex, because we don't know at creation time which engine is going 76 * to use them. To handle this, we have implemented a deferred creation of LR 77 * contexts: 78 * 79 * The local context starts its life as a hollow or blank holder, that only 80 * gets populated for a given engine once we receive an execbuffer. If later 81 * on we receive another execbuffer ioctl for the same context but a different 82 * engine, we allocate/populate a new ringbuffer and context backing object and 83 * so on. 84 * 85 * Finally, regarding local contexts created using the ioctl call: as they are 86 * only allowed with the render ring, we can allocate & populate them right 87 * away (no need to defer anything, at least for now). 88 * 89 * Execlists implementation: 90 * Execlists are the new method by which, on gen8+ hardware, workloads are 91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method). 92 * This method works as follows: 93 * 94 * When a request is committed, its commands (the BB start and any leading or 95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer 96 * for the appropriate context. The tail pointer in the hardware context is not 97 * updated at this time, but instead, kept by the driver in the ringbuffer 98 * structure. A structure representing this request is added to a request queue 99 * for the appropriate engine: this structure contains a copy of the context's 100 * tail after the request was written to the ring buffer and a pointer to the 101 * context itself. 102 * 103 * If the engine's request queue was empty before the request was added, the 104 * queue is processed immediately. Otherwise the queue will be processed during 105 * a context switch interrupt. In any case, elements on the queue will get sent 106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a 107 * globally unique 20-bits submission ID. 108 * 109 * When execution of a request completes, the GPU updates the context status 110 * buffer with a context complete event and generates a context switch interrupt. 111 * During the interrupt handling, the driver examines the events in the buffer: 112 * for each context complete event, if the announced ID matches that on the head 113 * of the request queue, then that request is retired and removed from the queue. 114 * 115 * After processing, if any requests were retired and the queue is not empty 116 * then a new execution list can be submitted. The two requests at the front of 117 * the queue are next to be submitted but since a context may not occur twice in 118 * an execution list, if subsequent requests have the same ID as the first then 119 * the two requests must be combined. This is done simply by discarding requests 120 * at the head of the queue until either only one requests is left (in which case 121 * we use a NULL second context) or the first two requests have unique IDs. 122 * 123 * By always executing the first two requests in the queue the driver ensures 124 * that the GPU is kept as busy as possible. In the case where a single context 125 * completes but a second context is still executing, the request for this second 126 * context will be at the head of the queue when we remove the first one. This 127 * request will then be resubmitted along with a new request for a different context, 128 * which will cause the hardware to continue executing the second request and queue 129 * the new request (the GPU detects the condition of a context getting preempted 130 * with the same context and optimizes the context switch flow by not doing 131 * preemption, but just sampling the new tail pointer). 132 * 133 */ 134 #include <linux/interrupt.h> 135 136 #include "i915_drv.h" 137 #include "i915_gem_render_state.h" 138 #include "i915_vgpu.h" 139 #include "intel_engine_pm.h" 140 #include "intel_lrc_reg.h" 141 #include "intel_mocs.h" 142 #include "intel_reset.h" 143 #include "intel_workarounds.h" 144 145 #define RING_EXECLIST_QFULL (1 << 0x2) 146 #define RING_EXECLIST1_VALID (1 << 0x3) 147 #define RING_EXECLIST0_VALID (1 << 0x4) 148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) 149 #define RING_EXECLIST1_ACTIVE (1 << 0x11) 150 #define RING_EXECLIST0_ACTIVE (1 << 0x12) 151 152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) 153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) 154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) 155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) 156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4) 157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) 158 159 #define GEN8_CTX_STATUS_COMPLETED_MASK \ 160 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED) 161 162 /* Typical size of the average request (2 pipecontrols and a MI_BB) */ 163 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ 164 #define WA_TAIL_DWORDS 2 165 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS) 166 167 #define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT | I915_PRIORITY_NOSEMAPHORE) 168 169 static int execlists_context_deferred_alloc(struct intel_context *ce, 170 struct intel_engine_cs *engine); 171 static void execlists_init_reg_state(u32 *reg_state, 172 struct intel_context *ce, 173 struct intel_engine_cs *engine, 174 struct intel_ring *ring); 175 176 static inline struct i915_priolist *to_priolist(struct rb_node *rb) 177 { 178 return rb_entry(rb, struct i915_priolist, node); 179 } 180 181 static inline int rq_prio(const struct i915_request *rq) 182 { 183 return rq->sched.attr.priority; 184 } 185 186 static int effective_prio(const struct i915_request *rq) 187 { 188 int prio = rq_prio(rq); 189 190 /* 191 * On unwinding the active request, we give it a priority bump 192 * equivalent to a freshly submitted request. This protects it from 193 * being gazumped again, but it would be preferable if we didn't 194 * let it be gazumped in the first place! 195 * 196 * See __unwind_incomplete_requests() 197 */ 198 if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(rq)) { 199 /* 200 * After preemption, we insert the active request at the 201 * end of the new priority level. This means that we will be 202 * _lower_ priority than the preemptee all things equal (and 203 * so the preemption is valid), so adjust our comparison 204 * accordingly. 205 */ 206 prio |= ACTIVE_PRIORITY; 207 prio--; 208 } 209 210 /* Restrict mere WAIT boosts from triggering preemption */ 211 return prio | __NO_PREEMPTION; 212 } 213 214 static int queue_prio(const struct intel_engine_execlists *execlists) 215 { 216 struct i915_priolist *p; 217 struct rb_node *rb; 218 219 rb = rb_first_cached(&execlists->queue); 220 if (!rb) 221 return INT_MIN; 222 223 /* 224 * As the priolist[] are inverted, with the highest priority in [0], 225 * we have to flip the index value to become priority. 226 */ 227 p = to_priolist(rb); 228 return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used); 229 } 230 231 static inline bool need_preempt(const struct intel_engine_cs *engine, 232 const struct i915_request *rq) 233 { 234 int last_prio; 235 236 if (!engine->preempt_context) 237 return false; 238 239 if (i915_request_completed(rq)) 240 return false; 241 242 /* 243 * Check if the current priority hint merits a preemption attempt. 244 * 245 * We record the highest value priority we saw during rescheduling 246 * prior to this dequeue, therefore we know that if it is strictly 247 * less than the current tail of ESLP[0], we do not need to force 248 * a preempt-to-idle cycle. 249 * 250 * However, the priority hint is a mere hint that we may need to 251 * preempt. If that hint is stale or we may be trying to preempt 252 * ourselves, ignore the request. 253 */ 254 last_prio = effective_prio(rq); 255 if (!__execlists_need_preempt(engine->execlists.queue_priority_hint, 256 last_prio)) 257 return false; 258 259 /* 260 * Check against the first request in ELSP[1], it will, thanks to the 261 * power of PI, be the highest priority of that context. 262 */ 263 if (!list_is_last(&rq->link, &engine->timeline.requests) && 264 rq_prio(list_next_entry(rq, link)) > last_prio) 265 return true; 266 267 /* 268 * If the inflight context did not trigger the preemption, then maybe 269 * it was the set of queued requests? Pick the highest priority in 270 * the queue (the first active priolist) and see if it deserves to be 271 * running instead of ELSP[0]. 272 * 273 * The highest priority request in the queue can not be either 274 * ELSP[0] or ELSP[1] as, thanks again to PI, if it was the same 275 * context, it's priority would not exceed ELSP[0] aka last_prio. 276 */ 277 return queue_prio(&engine->execlists) > last_prio; 278 } 279 280 __maybe_unused static inline bool 281 assert_priority_queue(const struct i915_request *prev, 282 const struct i915_request *next) 283 { 284 const struct intel_engine_execlists *execlists = 285 &prev->engine->execlists; 286 287 /* 288 * Without preemption, the prev may refer to the still active element 289 * which we refuse to let go. 290 * 291 * Even with preemption, there are times when we think it is better not 292 * to preempt and leave an ostensibly lower priority request in flight. 293 */ 294 if (port_request(execlists->port) == prev) 295 return true; 296 297 return rq_prio(prev) >= rq_prio(next); 298 } 299 300 /* 301 * The context descriptor encodes various attributes of a context, 302 * including its GTT address and some flags. Because it's fairly 303 * expensive to calculate, we'll just do it once and cache the result, 304 * which remains valid until the context is unpinned. 305 * 306 * This is what a descriptor looks like, from LSB to MSB:: 307 * 308 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template) 309 * bits 12-31: LRCA, GTT address of (the HWSP of) this context 310 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC) 311 * bits 53-54: mbz, reserved for use by hardware 312 * bits 55-63: group ID, currently unused and set to 0 313 * 314 * Starting from Gen11, the upper dword of the descriptor has a new format: 315 * 316 * bits 32-36: reserved 317 * bits 37-47: SW context ID 318 * bits 48:53: engine instance 319 * bit 54: mbz, reserved for use by hardware 320 * bits 55-60: SW counter 321 * bits 61-63: engine class 322 * 323 * engine info, SW context ID and SW counter need to form a unique number 324 * (Context ID) per lrc. 325 */ 326 static u64 327 lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine) 328 { 329 struct i915_gem_context *ctx = ce->gem_context; 330 u64 desc; 331 332 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH))); 333 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH))); 334 335 desc = ctx->desc_template; /* bits 0-11 */ 336 GEM_BUG_ON(desc & GENMASK_ULL(63, 12)); 337 338 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE; 339 /* bits 12-31 */ 340 GEM_BUG_ON(desc & GENMASK_ULL(63, 32)); 341 342 /* 343 * The following 32bits are copied into the OA reports (dword 2). 344 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing 345 * anything below. 346 */ 347 if (INTEL_GEN(engine->i915) >= 11) { 348 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH)); 349 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT; 350 /* bits 37-47 */ 351 352 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT; 353 /* bits 48-53 */ 354 355 /* TODO: decide what to do with SW counter (bits 55-60) */ 356 357 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT; 358 /* bits 61-63 */ 359 } else { 360 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH)); 361 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ 362 } 363 364 return desc; 365 } 366 367 static void unwind_wa_tail(struct i915_request *rq) 368 { 369 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES); 370 assert_ring_tail_valid(rq->ring, rq->tail); 371 } 372 373 static struct i915_request * 374 __unwind_incomplete_requests(struct intel_engine_cs *engine) 375 { 376 struct i915_request *rq, *rn, *active = NULL; 377 struct list_head *uninitialized_var(pl); 378 int prio = I915_PRIORITY_INVALID | ACTIVE_PRIORITY; 379 380 lockdep_assert_held(&engine->timeline.lock); 381 382 list_for_each_entry_safe_reverse(rq, rn, 383 &engine->timeline.requests, 384 link) { 385 if (i915_request_completed(rq)) 386 break; 387 388 __i915_request_unsubmit(rq); 389 unwind_wa_tail(rq); 390 391 GEM_BUG_ON(rq->hw_context->active); 392 393 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); 394 if (rq_prio(rq) != prio) { 395 prio = rq_prio(rq); 396 pl = i915_sched_lookup_priolist(engine, prio); 397 } 398 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); 399 400 list_add(&rq->sched.link, pl); 401 402 active = rq; 403 } 404 405 /* 406 * The active request is now effectively the start of a new client 407 * stream, so give it the equivalent small priority bump to prevent 408 * it being gazumped a second time by another peer. 409 * 410 * Note we have to be careful not to apply a priority boost to a request 411 * still spinning on its semaphores. If the request hasn't started, that 412 * means it is still waiting for its dependencies to be signaled, and 413 * if we apply a priority boost to this request, we will boost it past 414 * its signalers and so break PI. 415 * 416 * One consequence of this preemption boost is that we may jump 417 * over lesser priorities (such as I915_PRIORITY_WAIT), effectively 418 * making those priorities non-preemptible. They will be moved forward 419 * in the priority queue, but they will not gain immediate access to 420 * the GPU. 421 */ 422 if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(active)) { 423 prio |= ACTIVE_PRIORITY; 424 active->sched.attr.priority = prio; 425 list_move_tail(&active->sched.link, 426 i915_sched_lookup_priolist(engine, prio)); 427 } 428 429 return active; 430 } 431 432 struct i915_request * 433 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists) 434 { 435 struct intel_engine_cs *engine = 436 container_of(execlists, typeof(*engine), execlists); 437 438 return __unwind_incomplete_requests(engine); 439 } 440 441 static inline void 442 execlists_context_status_change(struct i915_request *rq, unsigned long status) 443 { 444 /* 445 * Only used when GVT-g is enabled now. When GVT-g is disabled, 446 * The compiler should eliminate this function as dead-code. 447 */ 448 if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) 449 return; 450 451 atomic_notifier_call_chain(&rq->engine->context_status_notifier, 452 status, rq); 453 } 454 455 inline void 456 execlists_user_begin(struct intel_engine_execlists *execlists, 457 const struct execlist_port *port) 458 { 459 execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER); 460 } 461 462 inline void 463 execlists_user_end(struct intel_engine_execlists *execlists) 464 { 465 execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER); 466 } 467 468 static inline void 469 execlists_context_schedule_in(struct i915_request *rq) 470 { 471 GEM_BUG_ON(rq->hw_context->active); 472 473 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); 474 intel_engine_context_in(rq->engine); 475 rq->hw_context->active = rq->engine; 476 } 477 478 static inline void 479 execlists_context_schedule_out(struct i915_request *rq, unsigned long status) 480 { 481 rq->hw_context->active = NULL; 482 intel_engine_context_out(rq->engine); 483 execlists_context_status_change(rq, status); 484 trace_i915_request_out(rq); 485 } 486 487 static u64 execlists_update_context(struct i915_request *rq) 488 { 489 struct intel_context *ce = rq->hw_context; 490 491 ce->lrc_reg_state[CTX_RING_TAIL + 1] = 492 intel_ring_set_tail(rq->ring, rq->tail); 493 494 /* 495 * Make sure the context image is complete before we submit it to HW. 496 * 497 * Ostensibly, writes (including the WCB) should be flushed prior to 498 * an uncached write such as our mmio register access, the empirical 499 * evidence (esp. on Braswell) suggests that the WC write into memory 500 * may not be visible to the HW prior to the completion of the UC 501 * register write and that we may begin execution from the context 502 * before its image is complete leading to invalid PD chasing. 503 * 504 * Furthermore, Braswell, at least, wants a full mb to be sure that 505 * the writes are coherent in memory (visible to the GPU) prior to 506 * execution, and not just visible to other CPUs (as is the result of 507 * wmb). 508 */ 509 mb(); 510 return ce->lrc_desc; 511 } 512 513 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port) 514 { 515 if (execlists->ctrl_reg) { 516 writel(lower_32_bits(desc), execlists->submit_reg + port * 2); 517 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1); 518 } else { 519 writel(upper_32_bits(desc), execlists->submit_reg); 520 writel(lower_32_bits(desc), execlists->submit_reg); 521 } 522 } 523 524 static void execlists_submit_ports(struct intel_engine_cs *engine) 525 { 526 struct intel_engine_execlists *execlists = &engine->execlists; 527 struct execlist_port *port = execlists->port; 528 unsigned int n; 529 530 /* 531 * We can skip acquiring intel_runtime_pm_get() here as it was taken 532 * on our behalf by the request (see i915_gem_mark_busy()) and it will 533 * not be relinquished until the device is idle (see 534 * i915_gem_idle_work_handler()). As a precaution, we make sure 535 * that all ELSP are drained i.e. we have processed the CSB, 536 * before allowing ourselves to idle and calling intel_runtime_pm_put(). 537 */ 538 GEM_BUG_ON(!intel_wakeref_active(&engine->wakeref)); 539 540 /* 541 * ELSQ note: the submit queue is not cleared after being submitted 542 * to the HW so we need to make sure we always clean it up. This is 543 * currently ensured by the fact that we always write the same number 544 * of elsq entries, keep this in mind before changing the loop below. 545 */ 546 for (n = execlists_num_ports(execlists); n--; ) { 547 struct i915_request *rq; 548 unsigned int count; 549 u64 desc; 550 551 rq = port_unpack(&port[n], &count); 552 if (rq) { 553 GEM_BUG_ON(count > !n); 554 if (!count++) 555 execlists_context_schedule_in(rq); 556 port_set(&port[n], port_pack(rq, count)); 557 desc = execlists_update_context(rq); 558 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); 559 560 GEM_TRACE("%s in[%d]: ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n", 561 engine->name, n, 562 port[n].context_id, count, 563 rq->fence.context, rq->fence.seqno, 564 hwsp_seqno(rq), 565 rq_prio(rq)); 566 } else { 567 GEM_BUG_ON(!n); 568 desc = 0; 569 } 570 571 write_desc(execlists, desc, n); 572 } 573 574 /* we need to manually load the submit queue */ 575 if (execlists->ctrl_reg) 576 writel(EL_CTRL_LOAD, execlists->ctrl_reg); 577 578 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); 579 } 580 581 static bool ctx_single_port_submission(const struct intel_context *ce) 582 { 583 return (IS_ENABLED(CONFIG_DRM_I915_GVT) && 584 i915_gem_context_force_single_submission(ce->gem_context)); 585 } 586 587 static bool can_merge_ctx(const struct intel_context *prev, 588 const struct intel_context *next) 589 { 590 if (prev != next) 591 return false; 592 593 if (ctx_single_port_submission(prev)) 594 return false; 595 596 return true; 597 } 598 599 static bool can_merge_rq(const struct i915_request *prev, 600 const struct i915_request *next) 601 { 602 GEM_BUG_ON(!assert_priority_queue(prev, next)); 603 604 if (!can_merge_ctx(prev->hw_context, next->hw_context)) 605 return false; 606 607 return true; 608 } 609 610 static void port_assign(struct execlist_port *port, struct i915_request *rq) 611 { 612 GEM_BUG_ON(rq == port_request(port)); 613 614 if (port_isset(port)) 615 i915_request_put(port_request(port)); 616 617 port_set(port, port_pack(i915_request_get(rq), port_count(port))); 618 } 619 620 static void inject_preempt_context(struct intel_engine_cs *engine) 621 { 622 struct intel_engine_execlists *execlists = &engine->execlists; 623 struct intel_context *ce = engine->preempt_context; 624 unsigned int n; 625 626 GEM_BUG_ON(execlists->preempt_complete_status != 627 upper_32_bits(ce->lrc_desc)); 628 629 /* 630 * Switch to our empty preempt context so 631 * the state of the GPU is known (idle). 632 */ 633 GEM_TRACE("%s\n", engine->name); 634 for (n = execlists_num_ports(execlists); --n; ) 635 write_desc(execlists, 0, n); 636 637 write_desc(execlists, ce->lrc_desc, n); 638 639 /* we need to manually load the submit queue */ 640 if (execlists->ctrl_reg) 641 writel(EL_CTRL_LOAD, execlists->ctrl_reg); 642 643 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); 644 execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT); 645 646 (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++); 647 } 648 649 static void complete_preempt_context(struct intel_engine_execlists *execlists) 650 { 651 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT)); 652 653 if (inject_preempt_hang(execlists)) 654 return; 655 656 execlists_cancel_port_requests(execlists); 657 __unwind_incomplete_requests(container_of(execlists, 658 struct intel_engine_cs, 659 execlists)); 660 } 661 662 static void execlists_dequeue(struct intel_engine_cs *engine) 663 { 664 struct intel_engine_execlists * const execlists = &engine->execlists; 665 struct execlist_port *port = execlists->port; 666 const struct execlist_port * const last_port = 667 &execlists->port[execlists->port_mask]; 668 struct i915_request *last = port_request(port); 669 struct rb_node *rb; 670 bool submit = false; 671 672 /* 673 * Hardware submission is through 2 ports. Conceptually each port 674 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is 675 * static for a context, and unique to each, so we only execute 676 * requests belonging to a single context from each ring. RING_HEAD 677 * is maintained by the CS in the context image, it marks the place 678 * where it got up to last time, and through RING_TAIL we tell the CS 679 * where we want to execute up to this time. 680 * 681 * In this list the requests are in order of execution. Consecutive 682 * requests from the same context are adjacent in the ringbuffer. We 683 * can combine these requests into a single RING_TAIL update: 684 * 685 * RING_HEAD...req1...req2 686 * ^- RING_TAIL 687 * since to execute req2 the CS must first execute req1. 688 * 689 * Our goal then is to point each port to the end of a consecutive 690 * sequence of requests as being the most optimal (fewest wake ups 691 * and context switches) submission. 692 */ 693 694 if (last) { 695 /* 696 * Don't resubmit or switch until all outstanding 697 * preemptions (lite-restore) are seen. Then we 698 * know the next preemption status we see corresponds 699 * to this ELSP update. 700 */ 701 GEM_BUG_ON(!execlists_is_active(execlists, 702 EXECLISTS_ACTIVE_USER)); 703 GEM_BUG_ON(!port_count(&port[0])); 704 705 /* 706 * If we write to ELSP a second time before the HW has had 707 * a chance to respond to the previous write, we can confuse 708 * the HW and hit "undefined behaviour". After writing to ELSP, 709 * we must then wait until we see a context-switch event from 710 * the HW to indicate that it has had a chance to respond. 711 */ 712 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK)) 713 return; 714 715 if (need_preempt(engine, last)) { 716 inject_preempt_context(engine); 717 return; 718 } 719 720 /* 721 * In theory, we could coalesce more requests onto 722 * the second port (the first port is active, with 723 * no preemptions pending). However, that means we 724 * then have to deal with the possible lite-restore 725 * of the second port (as we submit the ELSP, there 726 * may be a context-switch) but also we may complete 727 * the resubmission before the context-switch. Ergo, 728 * coalescing onto the second port will cause a 729 * preemption event, but we cannot predict whether 730 * that will affect port[0] or port[1]. 731 * 732 * If the second port is already active, we can wait 733 * until the next context-switch before contemplating 734 * new requests. The GPU will be busy and we should be 735 * able to resubmit the new ELSP before it idles, 736 * avoiding pipeline bubbles (momentary pauses where 737 * the driver is unable to keep up the supply of new 738 * work). However, we have to double check that the 739 * priorities of the ports haven't been switch. 740 */ 741 if (port_count(&port[1])) 742 return; 743 744 /* 745 * WaIdleLiteRestore:bdw,skl 746 * Apply the wa NOOPs to prevent 747 * ring:HEAD == rq:TAIL as we resubmit the 748 * request. See gen8_emit_fini_breadcrumb() for 749 * where we prepare the padding after the 750 * end of the request. 751 */ 752 last->tail = last->wa_tail; 753 } 754 755 while ((rb = rb_first_cached(&execlists->queue))) { 756 struct i915_priolist *p = to_priolist(rb); 757 struct i915_request *rq, *rn; 758 int i; 759 760 priolist_for_each_request_consume(rq, rn, p, i) { 761 /* 762 * Can we combine this request with the current port? 763 * It has to be the same context/ringbuffer and not 764 * have any exceptions (e.g. GVT saying never to 765 * combine contexts). 766 * 767 * If we can combine the requests, we can execute both 768 * by updating the RING_TAIL to point to the end of the 769 * second request, and so we never need to tell the 770 * hardware about the first. 771 */ 772 if (last && !can_merge_rq(last, rq)) { 773 /* 774 * If we are on the second port and cannot 775 * combine this request with the last, then we 776 * are done. 777 */ 778 if (port == last_port) 779 goto done; 780 781 /* 782 * We must not populate both ELSP[] with the 783 * same LRCA, i.e. we must submit 2 different 784 * contexts if we submit 2 ELSP. 785 */ 786 if (last->hw_context == rq->hw_context) 787 goto done; 788 789 /* 790 * If GVT overrides us we only ever submit 791 * port[0], leaving port[1] empty. Note that we 792 * also have to be careful that we don't queue 793 * the same context (even though a different 794 * request) to the second port. 795 */ 796 if (ctx_single_port_submission(last->hw_context) || 797 ctx_single_port_submission(rq->hw_context)) 798 goto done; 799 800 801 if (submit) 802 port_assign(port, last); 803 port++; 804 805 GEM_BUG_ON(port_isset(port)); 806 } 807 808 list_del_init(&rq->sched.link); 809 810 __i915_request_submit(rq); 811 trace_i915_request_in(rq, port_index(port, execlists)); 812 813 last = rq; 814 submit = true; 815 } 816 817 rb_erase_cached(&p->node, &execlists->queue); 818 i915_priolist_free(p); 819 } 820 821 done: 822 /* 823 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer. 824 * 825 * We choose the priority hint such that if we add a request of greater 826 * priority than this, we kick the submission tasklet to decide on 827 * the right order of submitting the requests to hardware. We must 828 * also be prepared to reorder requests as they are in-flight on the 829 * HW. We derive the priority hint then as the first "hole" in 830 * the HW submission ports and if there are no available slots, 831 * the priority of the lowest executing request, i.e. last. 832 * 833 * When we do receive a higher priority request ready to run from the 834 * user, see queue_request(), the priority hint is bumped to that 835 * request triggering preemption on the next dequeue (or subsequent 836 * interrupt for secondary ports). 837 */ 838 execlists->queue_priority_hint = queue_prio(execlists); 839 840 if (submit) { 841 port_assign(port, last); 842 execlists_submit_ports(engine); 843 } 844 845 /* We must always keep the beast fed if we have work piled up */ 846 GEM_BUG_ON(rb_first_cached(&execlists->queue) && 847 !port_isset(execlists->port)); 848 849 /* Re-evaluate the executing context setup after each preemptive kick */ 850 if (last) 851 execlists_user_begin(execlists, execlists->port); 852 853 /* If the engine is now idle, so should be the flag; and vice versa. */ 854 GEM_BUG_ON(execlists_is_active(&engine->execlists, 855 EXECLISTS_ACTIVE_USER) == 856 !port_isset(engine->execlists.port)); 857 } 858 859 void 860 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists) 861 { 862 struct execlist_port *port = execlists->port; 863 unsigned int num_ports = execlists_num_ports(execlists); 864 865 while (num_ports-- && port_isset(port)) { 866 struct i915_request *rq = port_request(port); 867 868 GEM_TRACE("%s:port%u fence %llx:%lld, (current %d)\n", 869 rq->engine->name, 870 (unsigned int)(port - execlists->port), 871 rq->fence.context, rq->fence.seqno, 872 hwsp_seqno(rq)); 873 874 GEM_BUG_ON(!execlists->active); 875 execlists_context_schedule_out(rq, 876 i915_request_completed(rq) ? 877 INTEL_CONTEXT_SCHEDULE_OUT : 878 INTEL_CONTEXT_SCHEDULE_PREEMPTED); 879 880 i915_request_put(rq); 881 882 memset(port, 0, sizeof(*port)); 883 port++; 884 } 885 886 execlists_clear_all_active(execlists); 887 } 888 889 static inline void 890 invalidate_csb_entries(const u32 *first, const u32 *last) 891 { 892 clflush((void *)first); 893 clflush((void *)last); 894 } 895 896 static inline bool 897 reset_in_progress(const struct intel_engine_execlists *execlists) 898 { 899 return unlikely(!__tasklet_is_enabled(&execlists->tasklet)); 900 } 901 902 static void process_csb(struct intel_engine_cs *engine) 903 { 904 struct intel_engine_execlists * const execlists = &engine->execlists; 905 struct execlist_port *port = execlists->port; 906 const u32 * const buf = execlists->csb_status; 907 const u8 num_entries = execlists->csb_size; 908 u8 head, tail; 909 910 lockdep_assert_held(&engine->timeline.lock); 911 912 /* 913 * Note that csb_write, csb_status may be either in HWSP or mmio. 914 * When reading from the csb_write mmio register, we have to be 915 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is 916 * the low 4bits. As it happens we know the next 4bits are always 917 * zero and so we can simply masked off the low u8 of the register 918 * and treat it identically to reading from the HWSP (without having 919 * to use explicit shifting and masking, and probably bifurcating 920 * the code to handle the legacy mmio read). 921 */ 922 head = execlists->csb_head; 923 tail = READ_ONCE(*execlists->csb_write); 924 GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail); 925 if (unlikely(head == tail)) 926 return; 927 928 /* 929 * Hopefully paired with a wmb() in HW! 930 * 931 * We must complete the read of the write pointer before any reads 932 * from the CSB, so that we do not see stale values. Without an rmb 933 * (lfence) the HW may speculatively perform the CSB[] reads *before* 934 * we perform the READ_ONCE(*csb_write). 935 */ 936 rmb(); 937 938 do { 939 struct i915_request *rq; 940 unsigned int status; 941 unsigned int count; 942 943 if (++head == num_entries) 944 head = 0; 945 946 /* 947 * We are flying near dragons again. 948 * 949 * We hold a reference to the request in execlist_port[] 950 * but no more than that. We are operating in softirq 951 * context and so cannot hold any mutex or sleep. That 952 * prevents us stopping the requests we are processing 953 * in port[] from being retired simultaneously (the 954 * breadcrumb will be complete before we see the 955 * context-switch). As we only hold the reference to the 956 * request, any pointer chasing underneath the request 957 * is subject to a potential use-after-free. Thus we 958 * store all of the bookkeeping within port[] as 959 * required, and avoid using unguarded pointers beneath 960 * request itself. The same applies to the atomic 961 * status notifier. 962 */ 963 964 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n", 965 engine->name, head, 966 buf[2 * head + 0], buf[2 * head + 1], 967 execlists->active); 968 969 status = buf[2 * head]; 970 if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE | 971 GEN8_CTX_STATUS_PREEMPTED)) 972 execlists_set_active(execlists, 973 EXECLISTS_ACTIVE_HWACK); 974 if (status & GEN8_CTX_STATUS_ACTIVE_IDLE) 975 execlists_clear_active(execlists, 976 EXECLISTS_ACTIVE_HWACK); 977 978 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) 979 continue; 980 981 /* We should never get a COMPLETED | IDLE_ACTIVE! */ 982 GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE); 983 984 if (status & GEN8_CTX_STATUS_COMPLETE && 985 buf[2*head + 1] == execlists->preempt_complete_status) { 986 GEM_TRACE("%s preempt-idle\n", engine->name); 987 complete_preempt_context(execlists); 988 continue; 989 } 990 991 if (status & GEN8_CTX_STATUS_PREEMPTED && 992 execlists_is_active(execlists, 993 EXECLISTS_ACTIVE_PREEMPT)) 994 continue; 995 996 GEM_BUG_ON(!execlists_is_active(execlists, 997 EXECLISTS_ACTIVE_USER)); 998 999 rq = port_unpack(port, &count); 1000 GEM_TRACE("%s out[0]: ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n", 1001 engine->name, 1002 port->context_id, count, 1003 rq ? rq->fence.context : 0, 1004 rq ? rq->fence.seqno : 0, 1005 rq ? hwsp_seqno(rq) : 0, 1006 rq ? rq_prio(rq) : 0); 1007 1008 /* Check the context/desc id for this event matches */ 1009 GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id); 1010 1011 GEM_BUG_ON(count == 0); 1012 if (--count == 0) { 1013 /* 1014 * On the final event corresponding to the 1015 * submission of this context, we expect either 1016 * an element-switch event or a completion 1017 * event (and on completion, the active-idle 1018 * marker). No more preemptions, lite-restore 1019 * or otherwise. 1020 */ 1021 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); 1022 GEM_BUG_ON(port_isset(&port[1]) && 1023 !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH)); 1024 GEM_BUG_ON(!port_isset(&port[1]) && 1025 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); 1026 1027 /* 1028 * We rely on the hardware being strongly 1029 * ordered, that the breadcrumb write is 1030 * coherent (visible from the CPU) before the 1031 * user interrupt and CSB is processed. 1032 */ 1033 GEM_BUG_ON(!i915_request_completed(rq)); 1034 1035 execlists_context_schedule_out(rq, 1036 INTEL_CONTEXT_SCHEDULE_OUT); 1037 i915_request_put(rq); 1038 1039 GEM_TRACE("%s completed ctx=%d\n", 1040 engine->name, port->context_id); 1041 1042 port = execlists_port_complete(execlists, port); 1043 if (port_isset(port)) 1044 execlists_user_begin(execlists, port); 1045 else 1046 execlists_user_end(execlists); 1047 } else { 1048 port_set(port, port_pack(rq, count)); 1049 } 1050 } while (head != tail); 1051 1052 execlists->csb_head = head; 1053 1054 /* 1055 * Gen11 has proven to fail wrt global observation point between 1056 * entry and tail update, failing on the ordering and thus 1057 * we see an old entry in the context status buffer. 1058 * 1059 * Forcibly evict out entries for the next gpu csb update, 1060 * to increase the odds that we get a fresh entries with non 1061 * working hardware. The cost for doing so comes out mostly with 1062 * the wash as hardware, working or not, will need to do the 1063 * invalidation before. 1064 */ 1065 invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); 1066 } 1067 1068 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) 1069 { 1070 lockdep_assert_held(&engine->timeline.lock); 1071 1072 process_csb(engine); 1073 if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT)) 1074 execlists_dequeue(engine); 1075 } 1076 1077 /* 1078 * Check the unread Context Status Buffers and manage the submission of new 1079 * contexts to the ELSP accordingly. 1080 */ 1081 static void execlists_submission_tasklet(unsigned long data) 1082 { 1083 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; 1084 unsigned long flags; 1085 1086 GEM_TRACE("%s awake?=%d, active=%x\n", 1087 engine->name, 1088 !!intel_wakeref_active(&engine->wakeref), 1089 engine->execlists.active); 1090 1091 spin_lock_irqsave(&engine->timeline.lock, flags); 1092 __execlists_submission_tasklet(engine); 1093 spin_unlock_irqrestore(&engine->timeline.lock, flags); 1094 } 1095 1096 static void queue_request(struct intel_engine_cs *engine, 1097 struct i915_sched_node *node, 1098 int prio) 1099 { 1100 list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio)); 1101 } 1102 1103 static void __submit_queue_imm(struct intel_engine_cs *engine) 1104 { 1105 struct intel_engine_execlists * const execlists = &engine->execlists; 1106 1107 if (reset_in_progress(execlists)) 1108 return; /* defer until we restart the engine following reset */ 1109 1110 if (execlists->tasklet.func == execlists_submission_tasklet) 1111 __execlists_submission_tasklet(engine); 1112 else 1113 tasklet_hi_schedule(&execlists->tasklet); 1114 } 1115 1116 static void submit_queue(struct intel_engine_cs *engine, int prio) 1117 { 1118 if (prio > engine->execlists.queue_priority_hint) { 1119 engine->execlists.queue_priority_hint = prio; 1120 __submit_queue_imm(engine); 1121 } 1122 } 1123 1124 static void execlists_submit_request(struct i915_request *request) 1125 { 1126 struct intel_engine_cs *engine = request->engine; 1127 unsigned long flags; 1128 1129 /* Will be called from irq-context when using foreign fences. */ 1130 spin_lock_irqsave(&engine->timeline.lock, flags); 1131 1132 queue_request(engine, &request->sched, rq_prio(request)); 1133 1134 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); 1135 GEM_BUG_ON(list_empty(&request->sched.link)); 1136 1137 submit_queue(engine, rq_prio(request)); 1138 1139 spin_unlock_irqrestore(&engine->timeline.lock, flags); 1140 } 1141 1142 static void __execlists_context_fini(struct intel_context *ce) 1143 { 1144 intel_ring_put(ce->ring); 1145 1146 GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj)); 1147 i915_gem_object_put(ce->state->obj); 1148 } 1149 1150 static void execlists_context_destroy(struct kref *kref) 1151 { 1152 struct intel_context *ce = container_of(kref, typeof(*ce), ref); 1153 1154 GEM_BUG_ON(intel_context_is_pinned(ce)); 1155 1156 if (ce->state) 1157 __execlists_context_fini(ce); 1158 1159 intel_context_free(ce); 1160 } 1161 1162 static int __context_pin(struct i915_vma *vma) 1163 { 1164 unsigned int flags; 1165 int err; 1166 1167 flags = PIN_GLOBAL | PIN_HIGH; 1168 flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); 1169 1170 err = i915_vma_pin(vma, 0, 0, flags); 1171 if (err) 1172 return err; 1173 1174 vma->obj->pin_global++; 1175 vma->obj->mm.dirty = true; 1176 1177 return 0; 1178 } 1179 1180 static void __context_unpin(struct i915_vma *vma) 1181 { 1182 vma->obj->pin_global--; 1183 __i915_vma_unpin(vma); 1184 } 1185 1186 static void execlists_context_unpin(struct intel_context *ce) 1187 { 1188 struct intel_engine_cs *engine; 1189 1190 /* 1191 * The tasklet may still be using a pointer to our state, via an 1192 * old request. However, since we know we only unpin the context 1193 * on retirement of the following request, we know that the last 1194 * request referencing us will have had a completion CS interrupt. 1195 * If we see that it is still active, it means that the tasklet hasn't 1196 * had the chance to run yet; let it run before we teardown the 1197 * reference it may use. 1198 */ 1199 engine = READ_ONCE(ce->active); 1200 if (unlikely(engine)) { 1201 unsigned long flags; 1202 1203 spin_lock_irqsave(&engine->timeline.lock, flags); 1204 process_csb(engine); 1205 spin_unlock_irqrestore(&engine->timeline.lock, flags); 1206 1207 GEM_BUG_ON(READ_ONCE(ce->active)); 1208 } 1209 1210 i915_gem_context_unpin_hw_id(ce->gem_context); 1211 1212 intel_ring_unpin(ce->ring); 1213 1214 i915_gem_object_unpin_map(ce->state->obj); 1215 __context_unpin(ce->state); 1216 } 1217 1218 static void 1219 __execlists_update_reg_state(struct intel_context *ce, 1220 struct intel_engine_cs *engine) 1221 { 1222 struct intel_ring *ring = ce->ring; 1223 u32 *regs = ce->lrc_reg_state; 1224 1225 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); 1226 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); 1227 1228 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma); 1229 regs[CTX_RING_HEAD + 1] = ring->head; 1230 regs[CTX_RING_TAIL + 1] = ring->tail; 1231 1232 /* RPCS */ 1233 if (engine->class == RENDER_CLASS) 1234 regs[CTX_R_PWR_CLK_STATE + 1] = 1235 intel_sseu_make_rpcs(engine->i915, &ce->sseu); 1236 } 1237 1238 static int 1239 __execlists_context_pin(struct intel_context *ce, 1240 struct intel_engine_cs *engine) 1241 { 1242 void *vaddr; 1243 int ret; 1244 1245 GEM_BUG_ON(!ce->gem_context->ppgtt); 1246 1247 ret = execlists_context_deferred_alloc(ce, engine); 1248 if (ret) 1249 goto err; 1250 GEM_BUG_ON(!ce->state); 1251 1252 ret = __context_pin(ce->state); 1253 if (ret) 1254 goto err; 1255 1256 vaddr = i915_gem_object_pin_map(ce->state->obj, 1257 i915_coherent_map_type(engine->i915) | 1258 I915_MAP_OVERRIDE); 1259 if (IS_ERR(vaddr)) { 1260 ret = PTR_ERR(vaddr); 1261 goto unpin_vma; 1262 } 1263 1264 ret = intel_ring_pin(ce->ring); 1265 if (ret) 1266 goto unpin_map; 1267 1268 ret = i915_gem_context_pin_hw_id(ce->gem_context); 1269 if (ret) 1270 goto unpin_ring; 1271 1272 ce->lrc_desc = lrc_descriptor(ce, engine); 1273 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; 1274 __execlists_update_reg_state(ce, engine); 1275 1276 return 0; 1277 1278 unpin_ring: 1279 intel_ring_unpin(ce->ring); 1280 unpin_map: 1281 i915_gem_object_unpin_map(ce->state->obj); 1282 unpin_vma: 1283 __context_unpin(ce->state); 1284 err: 1285 return ret; 1286 } 1287 1288 static int execlists_context_pin(struct intel_context *ce) 1289 { 1290 return __execlists_context_pin(ce, ce->engine); 1291 } 1292 1293 static void execlists_context_reset(struct intel_context *ce) 1294 { 1295 /* 1296 * Because we emit WA_TAIL_DWORDS there may be a disparity 1297 * between our bookkeeping in ce->ring->head and ce->ring->tail and 1298 * that stored in context. As we only write new commands from 1299 * ce->ring->tail onwards, everything before that is junk. If the GPU 1300 * starts reading from its RING_HEAD from the context, it may try to 1301 * execute that junk and die. 1302 * 1303 * The contexts that are stilled pinned on resume belong to the 1304 * kernel, and are local to each engine. All other contexts will 1305 * have their head/tail sanitized upon pinning before use, so they 1306 * will never see garbage, 1307 * 1308 * So to avoid that we reset the context images upon resume. For 1309 * simplicity, we just zero everything out. 1310 */ 1311 intel_ring_reset(ce->ring, 0); 1312 __execlists_update_reg_state(ce, ce->engine); 1313 } 1314 1315 static const struct intel_context_ops execlists_context_ops = { 1316 .pin = execlists_context_pin, 1317 .unpin = execlists_context_unpin, 1318 1319 .enter = intel_context_enter_engine, 1320 .exit = intel_context_exit_engine, 1321 1322 .reset = execlists_context_reset, 1323 .destroy = execlists_context_destroy, 1324 }; 1325 1326 static int gen8_emit_init_breadcrumb(struct i915_request *rq) 1327 { 1328 u32 *cs; 1329 1330 GEM_BUG_ON(!rq->timeline->has_initial_breadcrumb); 1331 1332 cs = intel_ring_begin(rq, 6); 1333 if (IS_ERR(cs)) 1334 return PTR_ERR(cs); 1335 1336 /* 1337 * Check if we have been preempted before we even get started. 1338 * 1339 * After this point i915_request_started() reports true, even if 1340 * we get preempted and so are no longer running. 1341 */ 1342 *cs++ = MI_ARB_CHECK; 1343 *cs++ = MI_NOOP; 1344 1345 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; 1346 *cs++ = rq->timeline->hwsp_offset; 1347 *cs++ = 0; 1348 *cs++ = rq->fence.seqno - 1; 1349 1350 intel_ring_advance(rq, cs); 1351 1352 /* Record the updated position of the request's payload */ 1353 rq->infix = intel_ring_offset(rq, cs); 1354 1355 return 0; 1356 } 1357 1358 static int emit_pdps(struct i915_request *rq) 1359 { 1360 const struct intel_engine_cs * const engine = rq->engine; 1361 struct i915_hw_ppgtt * const ppgtt = rq->gem_context->ppgtt; 1362 int err, i; 1363 u32 *cs; 1364 1365 GEM_BUG_ON(intel_vgpu_active(rq->i915)); 1366 1367 /* 1368 * Beware ye of the dragons, this sequence is magic! 1369 * 1370 * Small changes to this sequence can cause anything from 1371 * GPU hangs to forcewake errors and machine lockups! 1372 */ 1373 1374 /* Flush any residual operations from the context load */ 1375 err = engine->emit_flush(rq, EMIT_FLUSH); 1376 if (err) 1377 return err; 1378 1379 /* Magic required to prevent forcewake errors! */ 1380 err = engine->emit_flush(rq, EMIT_INVALIDATE); 1381 if (err) 1382 return err; 1383 1384 cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2); 1385 if (IS_ERR(cs)) 1386 return PTR_ERR(cs); 1387 1388 /* Ensure the LRI have landed before we invalidate & continue */ 1389 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED; 1390 for (i = GEN8_3LVL_PDPES; i--; ) { 1391 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); 1392 u32 base = engine->mmio_base; 1393 1394 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i)); 1395 *cs++ = upper_32_bits(pd_daddr); 1396 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i)); 1397 *cs++ = lower_32_bits(pd_daddr); 1398 } 1399 *cs++ = MI_NOOP; 1400 1401 intel_ring_advance(rq, cs); 1402 1403 /* Be doubly sure the LRI have landed before proceeding */ 1404 err = engine->emit_flush(rq, EMIT_FLUSH); 1405 if (err) 1406 return err; 1407 1408 /* Re-invalidate the TLB for luck */ 1409 return engine->emit_flush(rq, EMIT_INVALIDATE); 1410 } 1411 1412 static int execlists_request_alloc(struct i915_request *request) 1413 { 1414 int ret; 1415 1416 GEM_BUG_ON(!intel_context_is_pinned(request->hw_context)); 1417 1418 /* 1419 * Flush enough space to reduce the likelihood of waiting after 1420 * we start building the request - in which case we will just 1421 * have to repeat work. 1422 */ 1423 request->reserved_space += EXECLISTS_REQUEST_SIZE; 1424 1425 /* 1426 * Note that after this point, we have committed to using 1427 * this request as it is being used to both track the 1428 * state of engine initialisation and liveness of the 1429 * golden renderstate above. Think twice before you try 1430 * to cancel/unwind this request now. 1431 */ 1432 1433 /* Unconditionally invalidate GPU caches and TLBs. */ 1434 if (i915_vm_is_4lvl(&request->gem_context->ppgtt->vm)) 1435 ret = request->engine->emit_flush(request, EMIT_INVALIDATE); 1436 else 1437 ret = emit_pdps(request); 1438 if (ret) 1439 return ret; 1440 1441 request->reserved_space -= EXECLISTS_REQUEST_SIZE; 1442 return 0; 1443 } 1444 1445 /* 1446 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after 1447 * PIPE_CONTROL instruction. This is required for the flush to happen correctly 1448 * but there is a slight complication as this is applied in WA batch where the 1449 * values are only initialized once so we cannot take register value at the 1450 * beginning and reuse it further; hence we save its value to memory, upload a 1451 * constant value with bit21 set and then we restore it back with the saved value. 1452 * To simplify the WA, a constant value is formed by using the default value 1453 * of this register. This shouldn't be a problem because we are only modifying 1454 * it for a short period and this batch in non-premptible. We can ofcourse 1455 * use additional instructions that read the actual value of the register 1456 * at that time and set our bit of interest but it makes the WA complicated. 1457 * 1458 * This WA is also required for Gen9 so extracting as a function avoids 1459 * code duplication. 1460 */ 1461 static u32 * 1462 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) 1463 { 1464 /* NB no one else is allowed to scribble over scratch + 256! */ 1465 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; 1466 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); 1467 *batch++ = i915_scratch_offset(engine->i915) + 256; 1468 *batch++ = 0; 1469 1470 *batch++ = MI_LOAD_REGISTER_IMM(1); 1471 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); 1472 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; 1473 1474 batch = gen8_emit_pipe_control(batch, 1475 PIPE_CONTROL_CS_STALL | 1476 PIPE_CONTROL_DC_FLUSH_ENABLE, 1477 0); 1478 1479 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; 1480 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); 1481 *batch++ = i915_scratch_offset(engine->i915) + 256; 1482 *batch++ = 0; 1483 1484 return batch; 1485 } 1486 1487 /* 1488 * Typically we only have one indirect_ctx and per_ctx batch buffer which are 1489 * initialized at the beginning and shared across all contexts but this field 1490 * helps us to have multiple batches at different offsets and select them based 1491 * on a criteria. At the moment this batch always start at the beginning of the page 1492 * and at this point we don't have multiple wa_ctx batch buffers. 1493 * 1494 * The number of WA applied are not known at the beginning; we use this field 1495 * to return the no of DWORDS written. 1496 * 1497 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END 1498 * so it adds NOOPs as padding to make it cacheline aligned. 1499 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together 1500 * makes a complete batch buffer. 1501 */ 1502 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) 1503 { 1504 /* WaDisableCtxRestoreArbitration:bdw,chv */ 1505 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 1506 1507 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ 1508 if (IS_BROADWELL(engine->i915)) 1509 batch = gen8_emit_flush_coherentl3_wa(engine, batch); 1510 1511 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ 1512 /* Actual scratch location is at 128 bytes offset */ 1513 batch = gen8_emit_pipe_control(batch, 1514 PIPE_CONTROL_FLUSH_L3 | 1515 PIPE_CONTROL_GLOBAL_GTT_IVB | 1516 PIPE_CONTROL_CS_STALL | 1517 PIPE_CONTROL_QW_WRITE, 1518 i915_scratch_offset(engine->i915) + 1519 2 * CACHELINE_BYTES); 1520 1521 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 1522 1523 /* Pad to end of cacheline */ 1524 while ((unsigned long)batch % CACHELINE_BYTES) 1525 *batch++ = MI_NOOP; 1526 1527 /* 1528 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because 1529 * execution depends on the length specified in terms of cache lines 1530 * in the register CTX_RCS_INDIRECT_CTX 1531 */ 1532 1533 return batch; 1534 } 1535 1536 struct lri { 1537 i915_reg_t reg; 1538 u32 value; 1539 }; 1540 1541 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count) 1542 { 1543 GEM_BUG_ON(!count || count > 63); 1544 1545 *batch++ = MI_LOAD_REGISTER_IMM(count); 1546 do { 1547 *batch++ = i915_mmio_reg_offset(lri->reg); 1548 *batch++ = lri->value; 1549 } while (lri++, --count); 1550 *batch++ = MI_NOOP; 1551 1552 return batch; 1553 } 1554 1555 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) 1556 { 1557 static const struct lri lri[] = { 1558 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ 1559 { 1560 COMMON_SLICE_CHICKEN2, 1561 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE, 1562 0), 1563 }, 1564 1565 /* BSpec: 11391 */ 1566 { 1567 FF_SLICE_CHICKEN, 1568 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX, 1569 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX), 1570 }, 1571 1572 /* BSpec: 11299 */ 1573 { 1574 _3D_CHICKEN3, 1575 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX, 1576 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX), 1577 } 1578 }; 1579 1580 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 1581 1582 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ 1583 batch = gen8_emit_flush_coherentl3_wa(engine, batch); 1584 1585 batch = emit_lri(batch, lri, ARRAY_SIZE(lri)); 1586 1587 /* WaMediaPoolStateCmdInWABB:bxt,glk */ 1588 if (HAS_POOLED_EU(engine->i915)) { 1589 /* 1590 * EU pool configuration is setup along with golden context 1591 * during context initialization. This value depends on 1592 * device type (2x6 or 3x6) and needs to be updated based 1593 * on which subslice is disabled especially for 2x6 1594 * devices, however it is safe to load default 1595 * configuration of 3x6 device instead of masking off 1596 * corresponding bits because HW ignores bits of a disabled 1597 * subslice and drops down to appropriate config. Please 1598 * see render_state_setup() in i915_gem_render_state.c for 1599 * possible configurations, to avoid duplication they are 1600 * not shown here again. 1601 */ 1602 *batch++ = GEN9_MEDIA_POOL_STATE; 1603 *batch++ = GEN9_MEDIA_POOL_ENABLE; 1604 *batch++ = 0x00777000; 1605 *batch++ = 0; 1606 *batch++ = 0; 1607 *batch++ = 0; 1608 } 1609 1610 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 1611 1612 /* Pad to end of cacheline */ 1613 while ((unsigned long)batch % CACHELINE_BYTES) 1614 *batch++ = MI_NOOP; 1615 1616 return batch; 1617 } 1618 1619 static u32 * 1620 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) 1621 { 1622 int i; 1623 1624 /* 1625 * WaPipeControlBefore3DStateSamplePattern: cnl 1626 * 1627 * Ensure the engine is idle prior to programming a 1628 * 3DSTATE_SAMPLE_PATTERN during a context restore. 1629 */ 1630 batch = gen8_emit_pipe_control(batch, 1631 PIPE_CONTROL_CS_STALL, 1632 0); 1633 /* 1634 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for 1635 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in 1636 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is 1637 * confusing. Since gen8_emit_pipe_control() already advances the 1638 * batch by 6 dwords, we advance the other 10 here, completing a 1639 * cacheline. It's not clear if the workaround requires this padding 1640 * before other commands, or if it's just the regular padding we would 1641 * already have for the workaround bb, so leave it here for now. 1642 */ 1643 for (i = 0; i < 10; i++) 1644 *batch++ = MI_NOOP; 1645 1646 /* Pad to end of cacheline */ 1647 while ((unsigned long)batch % CACHELINE_BYTES) 1648 *batch++ = MI_NOOP; 1649 1650 return batch; 1651 } 1652 1653 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE) 1654 1655 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) 1656 { 1657 struct drm_i915_gem_object *obj; 1658 struct i915_vma *vma; 1659 int err; 1660 1661 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE); 1662 if (IS_ERR(obj)) 1663 return PTR_ERR(obj); 1664 1665 vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL); 1666 if (IS_ERR(vma)) { 1667 err = PTR_ERR(vma); 1668 goto err; 1669 } 1670 1671 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); 1672 if (err) 1673 goto err; 1674 1675 engine->wa_ctx.vma = vma; 1676 return 0; 1677 1678 err: 1679 i915_gem_object_put(obj); 1680 return err; 1681 } 1682 1683 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine) 1684 { 1685 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); 1686 } 1687 1688 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch); 1689 1690 static int intel_init_workaround_bb(struct intel_engine_cs *engine) 1691 { 1692 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; 1693 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx, 1694 &wa_ctx->per_ctx }; 1695 wa_bb_func_t wa_bb_fn[2]; 1696 struct page *page; 1697 void *batch, *batch_ptr; 1698 unsigned int i; 1699 int ret; 1700 1701 if (engine->class != RENDER_CLASS) 1702 return 0; 1703 1704 switch (INTEL_GEN(engine->i915)) { 1705 case 11: 1706 return 0; 1707 case 10: 1708 wa_bb_fn[0] = gen10_init_indirectctx_bb; 1709 wa_bb_fn[1] = NULL; 1710 break; 1711 case 9: 1712 wa_bb_fn[0] = gen9_init_indirectctx_bb; 1713 wa_bb_fn[1] = NULL; 1714 break; 1715 case 8: 1716 wa_bb_fn[0] = gen8_init_indirectctx_bb; 1717 wa_bb_fn[1] = NULL; 1718 break; 1719 default: 1720 MISSING_CASE(INTEL_GEN(engine->i915)); 1721 return 0; 1722 } 1723 1724 ret = lrc_setup_wa_ctx(engine); 1725 if (ret) { 1726 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); 1727 return ret; 1728 } 1729 1730 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); 1731 batch = batch_ptr = kmap_atomic(page); 1732 1733 /* 1734 * Emit the two workaround batch buffers, recording the offset from the 1735 * start of the workaround batch buffer object for each and their 1736 * respective sizes. 1737 */ 1738 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) { 1739 wa_bb[i]->offset = batch_ptr - batch; 1740 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, 1741 CACHELINE_BYTES))) { 1742 ret = -EINVAL; 1743 break; 1744 } 1745 if (wa_bb_fn[i]) 1746 batch_ptr = wa_bb_fn[i](engine, batch_ptr); 1747 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset); 1748 } 1749 1750 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE); 1751 1752 kunmap_atomic(batch); 1753 if (ret) 1754 lrc_destroy_wa_ctx(engine); 1755 1756 return ret; 1757 } 1758 1759 static void enable_execlists(struct intel_engine_cs *engine) 1760 { 1761 struct drm_i915_private *dev_priv = engine->i915; 1762 1763 intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */ 1764 1765 if (INTEL_GEN(dev_priv) >= 11) 1766 I915_WRITE(RING_MODE_GEN7(engine), 1767 _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); 1768 else 1769 I915_WRITE(RING_MODE_GEN7(engine), 1770 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); 1771 1772 I915_WRITE(RING_MI_MODE(engine->mmio_base), 1773 _MASKED_BIT_DISABLE(STOP_RING)); 1774 1775 I915_WRITE(RING_HWS_PGA(engine->mmio_base), 1776 i915_ggtt_offset(engine->status_page.vma)); 1777 POSTING_READ(RING_HWS_PGA(engine->mmio_base)); 1778 } 1779 1780 static bool unexpected_starting_state(struct intel_engine_cs *engine) 1781 { 1782 struct drm_i915_private *dev_priv = engine->i915; 1783 bool unexpected = false; 1784 1785 if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) { 1786 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n"); 1787 unexpected = true; 1788 } 1789 1790 return unexpected; 1791 } 1792 1793 static int execlists_resume(struct intel_engine_cs *engine) 1794 { 1795 intel_engine_apply_workarounds(engine); 1796 intel_engine_apply_whitelist(engine); 1797 1798 intel_mocs_init_engine(engine); 1799 1800 intel_engine_reset_breadcrumbs(engine); 1801 1802 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) { 1803 struct drm_printer p = drm_debug_printer(__func__); 1804 1805 intel_engine_dump(engine, &p, NULL); 1806 } 1807 1808 enable_execlists(engine); 1809 1810 return 0; 1811 } 1812 1813 static void execlists_reset_prepare(struct intel_engine_cs *engine) 1814 { 1815 struct intel_engine_execlists * const execlists = &engine->execlists; 1816 unsigned long flags; 1817 1818 GEM_TRACE("%s: depth<-%d\n", engine->name, 1819 atomic_read(&execlists->tasklet.count)); 1820 1821 /* 1822 * Prevent request submission to the hardware until we have 1823 * completed the reset in i915_gem_reset_finish(). If a request 1824 * is completed by one engine, it may then queue a request 1825 * to a second via its execlists->tasklet *just* as we are 1826 * calling engine->resume() and also writing the ELSP. 1827 * Turning off the execlists->tasklet until the reset is over 1828 * prevents the race. 1829 */ 1830 __tasklet_disable_sync_once(&execlists->tasklet); 1831 GEM_BUG_ON(!reset_in_progress(execlists)); 1832 1833 intel_engine_stop_cs(engine); 1834 1835 /* And flush any current direct submission. */ 1836 spin_lock_irqsave(&engine->timeline.lock, flags); 1837 spin_unlock_irqrestore(&engine->timeline.lock, flags); 1838 } 1839 1840 static bool lrc_regs_ok(const struct i915_request *rq) 1841 { 1842 const struct intel_ring *ring = rq->ring; 1843 const u32 *regs = rq->hw_context->lrc_reg_state; 1844 1845 /* Quick spot check for the common signs of context corruption */ 1846 1847 if (regs[CTX_RING_BUFFER_CONTROL + 1] != 1848 (RING_CTL_SIZE(ring->size) | RING_VALID)) 1849 return false; 1850 1851 if (regs[CTX_RING_BUFFER_START + 1] != i915_ggtt_offset(ring->vma)) 1852 return false; 1853 1854 return true; 1855 } 1856 1857 static void reset_csb_pointers(struct intel_engine_execlists *execlists) 1858 { 1859 const unsigned int reset_value = execlists->csb_size - 1; 1860 1861 /* 1862 * After a reset, the HW starts writing into CSB entry [0]. We 1863 * therefore have to set our HEAD pointer back one entry so that 1864 * the *first* entry we check is entry 0. To complicate this further, 1865 * as we don't wait for the first interrupt after reset, we have to 1866 * fake the HW write to point back to the last entry so that our 1867 * inline comparison of our cached head position against the last HW 1868 * write works even before the first interrupt. 1869 */ 1870 execlists->csb_head = reset_value; 1871 WRITE_ONCE(*execlists->csb_write, reset_value); 1872 wmb(); /* Make sure this is visible to HW (paranoia?) */ 1873 1874 invalidate_csb_entries(&execlists->csb_status[0], 1875 &execlists->csb_status[reset_value]); 1876 } 1877 1878 static void __execlists_reset(struct intel_engine_cs *engine, bool stalled) 1879 { 1880 struct intel_engine_execlists * const execlists = &engine->execlists; 1881 struct intel_context *ce; 1882 struct i915_request *rq; 1883 u32 *regs; 1884 1885 process_csb(engine); /* drain preemption events */ 1886 1887 /* Following the reset, we need to reload the CSB read/write pointers */ 1888 reset_csb_pointers(&engine->execlists); 1889 1890 /* 1891 * Save the currently executing context, even if we completed 1892 * its request, it was still running at the time of the 1893 * reset and will have been clobbered. 1894 */ 1895 if (!port_isset(execlists->port)) 1896 goto out_clear; 1897 1898 ce = port_request(execlists->port)->hw_context; 1899 1900 /* 1901 * Catch up with any missed context-switch interrupts. 1902 * 1903 * Ideally we would just read the remaining CSB entries now that we 1904 * know the gpu is idle. However, the CSB registers are sometimes^W 1905 * often trashed across a GPU reset! Instead we have to rely on 1906 * guessing the missed context-switch events by looking at what 1907 * requests were completed. 1908 */ 1909 execlists_cancel_port_requests(execlists); 1910 1911 /* Push back any incomplete requests for replay after the reset. */ 1912 rq = __unwind_incomplete_requests(engine); 1913 if (!rq) 1914 goto out_replay; 1915 1916 if (rq->hw_context != ce) { /* caught just before a CS event */ 1917 rq = NULL; 1918 goto out_replay; 1919 } 1920 1921 /* 1922 * If this request hasn't started yet, e.g. it is waiting on a 1923 * semaphore, we need to avoid skipping the request or else we 1924 * break the signaling chain. However, if the context is corrupt 1925 * the request will not restart and we will be stuck with a wedged 1926 * device. It is quite often the case that if we issue a reset 1927 * while the GPU is loading the context image, that the context 1928 * image becomes corrupt. 1929 * 1930 * Otherwise, if we have not started yet, the request should replay 1931 * perfectly and we do not need to flag the result as being erroneous. 1932 */ 1933 if (!i915_request_started(rq) && lrc_regs_ok(rq)) 1934 goto out_replay; 1935 1936 /* 1937 * If the request was innocent, we leave the request in the ELSP 1938 * and will try to replay it on restarting. The context image may 1939 * have been corrupted by the reset, in which case we may have 1940 * to service a new GPU hang, but more likely we can continue on 1941 * without impact. 1942 * 1943 * If the request was guilty, we presume the context is corrupt 1944 * and have to at least restore the RING register in the context 1945 * image back to the expected values to skip over the guilty request. 1946 */ 1947 i915_reset_request(rq, stalled); 1948 if (!stalled && lrc_regs_ok(rq)) 1949 goto out_replay; 1950 1951 /* 1952 * We want a simple context + ring to execute the breadcrumb update. 1953 * We cannot rely on the context being intact across the GPU hang, 1954 * so clear it and rebuild just what we need for the breadcrumb. 1955 * All pending requests for this context will be zapped, and any 1956 * future request will be after userspace has had the opportunity 1957 * to recreate its own state. 1958 */ 1959 regs = ce->lrc_reg_state; 1960 if (engine->pinned_default_state) { 1961 memcpy(regs, /* skip restoring the vanilla PPHWSP */ 1962 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE, 1963 engine->context_size - PAGE_SIZE); 1964 } 1965 execlists_init_reg_state(regs, ce, engine, ce->ring); 1966 1967 /* Rerun the request; its payload has been neutered (if guilty). */ 1968 out_replay: 1969 ce->ring->head = 1970 rq ? intel_ring_wrap(ce->ring, rq->head) : ce->ring->tail; 1971 intel_ring_update_space(ce->ring); 1972 __execlists_update_reg_state(ce, engine); 1973 1974 out_clear: 1975 execlists_clear_all_active(execlists); 1976 } 1977 1978 static void execlists_reset(struct intel_engine_cs *engine, bool stalled) 1979 { 1980 unsigned long flags; 1981 1982 GEM_TRACE("%s\n", engine->name); 1983 1984 spin_lock_irqsave(&engine->timeline.lock, flags); 1985 1986 __execlists_reset(engine, stalled); 1987 1988 spin_unlock_irqrestore(&engine->timeline.lock, flags); 1989 } 1990 1991 static void nop_submission_tasklet(unsigned long data) 1992 { 1993 /* The driver is wedged; don't process any more events. */ 1994 } 1995 1996 static void execlists_cancel_requests(struct intel_engine_cs *engine) 1997 { 1998 struct intel_engine_execlists * const execlists = &engine->execlists; 1999 struct i915_request *rq, *rn; 2000 struct rb_node *rb; 2001 unsigned long flags; 2002 2003 GEM_TRACE("%s\n", engine->name); 2004 2005 /* 2006 * Before we call engine->cancel_requests(), we should have exclusive 2007 * access to the submission state. This is arranged for us by the 2008 * caller disabling the interrupt generation, the tasklet and other 2009 * threads that may then access the same state, giving us a free hand 2010 * to reset state. However, we still need to let lockdep be aware that 2011 * we know this state may be accessed in hardirq context, so we 2012 * disable the irq around this manipulation and we want to keep 2013 * the spinlock focused on its duties and not accidentally conflate 2014 * coverage to the submission's irq state. (Similarly, although we 2015 * shouldn't need to disable irq around the manipulation of the 2016 * submission's irq state, we also wish to remind ourselves that 2017 * it is irq state.) 2018 */ 2019 spin_lock_irqsave(&engine->timeline.lock, flags); 2020 2021 __execlists_reset(engine, true); 2022 2023 /* Mark all executing requests as skipped. */ 2024 list_for_each_entry(rq, &engine->timeline.requests, link) { 2025 if (!i915_request_signaled(rq)) 2026 dma_fence_set_error(&rq->fence, -EIO); 2027 2028 i915_request_mark_complete(rq); 2029 } 2030 2031 /* Flush the queued requests to the timeline list (for retiring). */ 2032 while ((rb = rb_first_cached(&execlists->queue))) { 2033 struct i915_priolist *p = to_priolist(rb); 2034 int i; 2035 2036 priolist_for_each_request_consume(rq, rn, p, i) { 2037 list_del_init(&rq->sched.link); 2038 __i915_request_submit(rq); 2039 dma_fence_set_error(&rq->fence, -EIO); 2040 i915_request_mark_complete(rq); 2041 } 2042 2043 rb_erase_cached(&p->node, &execlists->queue); 2044 i915_priolist_free(p); 2045 } 2046 2047 /* Remaining _unready_ requests will be nop'ed when submitted */ 2048 2049 execlists->queue_priority_hint = INT_MIN; 2050 execlists->queue = RB_ROOT_CACHED; 2051 GEM_BUG_ON(port_isset(execlists->port)); 2052 2053 GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet)); 2054 execlists->tasklet.func = nop_submission_tasklet; 2055 2056 spin_unlock_irqrestore(&engine->timeline.lock, flags); 2057 } 2058 2059 static void execlists_reset_finish(struct intel_engine_cs *engine) 2060 { 2061 struct intel_engine_execlists * const execlists = &engine->execlists; 2062 2063 /* 2064 * After a GPU reset, we may have requests to replay. Do so now while 2065 * we still have the forcewake to be sure that the GPU is not allowed 2066 * to sleep before we restart and reload a context. 2067 */ 2068 GEM_BUG_ON(!reset_in_progress(execlists)); 2069 if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) 2070 execlists->tasklet.func(execlists->tasklet.data); 2071 2072 if (__tasklet_enable(&execlists->tasklet)) 2073 /* And kick in case we missed a new request submission. */ 2074 tasklet_hi_schedule(&execlists->tasklet); 2075 GEM_TRACE("%s: depth->%d\n", engine->name, 2076 atomic_read(&execlists->tasklet.count)); 2077 } 2078 2079 static int gen8_emit_bb_start(struct i915_request *rq, 2080 u64 offset, u32 len, 2081 const unsigned int flags) 2082 { 2083 u32 *cs; 2084 2085 cs = intel_ring_begin(rq, 4); 2086 if (IS_ERR(cs)) 2087 return PTR_ERR(cs); 2088 2089 /* 2090 * WaDisableCtxRestoreArbitration:bdw,chv 2091 * 2092 * We don't need to perform MI_ARB_ENABLE as often as we do (in 2093 * particular all the gen that do not need the w/a at all!), if we 2094 * took care to make sure that on every switch into this context 2095 * (both ordinary and for preemption) that arbitrartion was enabled 2096 * we would be fine. However, for gen8 there is another w/a that 2097 * requires us to not preempt inside GPGPU execution, so we keep 2098 * arbitration disabled for gen8 batches. Arbitration will be 2099 * re-enabled before we close the request 2100 * (engine->emit_fini_breadcrumb). 2101 */ 2102 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 2103 2104 /* FIXME(BDW+): Address space and security selectors. */ 2105 *cs++ = MI_BATCH_BUFFER_START_GEN8 | 2106 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); 2107 *cs++ = lower_32_bits(offset); 2108 *cs++ = upper_32_bits(offset); 2109 2110 intel_ring_advance(rq, cs); 2111 2112 return 0; 2113 } 2114 2115 static int gen9_emit_bb_start(struct i915_request *rq, 2116 u64 offset, u32 len, 2117 const unsigned int flags) 2118 { 2119 u32 *cs; 2120 2121 cs = intel_ring_begin(rq, 6); 2122 if (IS_ERR(cs)) 2123 return PTR_ERR(cs); 2124 2125 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 2126 2127 *cs++ = MI_BATCH_BUFFER_START_GEN8 | 2128 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); 2129 *cs++ = lower_32_bits(offset); 2130 *cs++ = upper_32_bits(offset); 2131 2132 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 2133 *cs++ = MI_NOOP; 2134 2135 intel_ring_advance(rq, cs); 2136 2137 return 0; 2138 } 2139 2140 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) 2141 { 2142 ENGINE_WRITE(engine, RING_IMR, 2143 ~(engine->irq_enable_mask | engine->irq_keep_mask)); 2144 ENGINE_POSTING_READ(engine, RING_IMR); 2145 } 2146 2147 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) 2148 { 2149 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); 2150 } 2151 2152 static int gen8_emit_flush(struct i915_request *request, u32 mode) 2153 { 2154 u32 cmd, *cs; 2155 2156 cs = intel_ring_begin(request, 4); 2157 if (IS_ERR(cs)) 2158 return PTR_ERR(cs); 2159 2160 cmd = MI_FLUSH_DW + 1; 2161 2162 /* We always require a command barrier so that subsequent 2163 * commands, such as breadcrumb interrupts, are strictly ordered 2164 * wrt the contents of the write cache being flushed to memory 2165 * (and thus being coherent from the CPU). 2166 */ 2167 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 2168 2169 if (mode & EMIT_INVALIDATE) { 2170 cmd |= MI_INVALIDATE_TLB; 2171 if (request->engine->class == VIDEO_DECODE_CLASS) 2172 cmd |= MI_INVALIDATE_BSD; 2173 } 2174 2175 *cs++ = cmd; 2176 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; 2177 *cs++ = 0; /* upper addr */ 2178 *cs++ = 0; /* value */ 2179 intel_ring_advance(request, cs); 2180 2181 return 0; 2182 } 2183 2184 static int gen8_emit_flush_render(struct i915_request *request, 2185 u32 mode) 2186 { 2187 struct intel_engine_cs *engine = request->engine; 2188 u32 scratch_addr = 2189 i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES; 2190 bool vf_flush_wa = false, dc_flush_wa = false; 2191 u32 *cs, flags = 0; 2192 int len; 2193 2194 flags |= PIPE_CONTROL_CS_STALL; 2195 2196 if (mode & EMIT_FLUSH) { 2197 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 2198 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 2199 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; 2200 flags |= PIPE_CONTROL_FLUSH_ENABLE; 2201 } 2202 2203 if (mode & EMIT_INVALIDATE) { 2204 flags |= PIPE_CONTROL_TLB_INVALIDATE; 2205 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 2206 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 2207 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 2208 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 2209 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 2210 flags |= PIPE_CONTROL_QW_WRITE; 2211 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; 2212 2213 /* 2214 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL 2215 * pipe control. 2216 */ 2217 if (IS_GEN(request->i915, 9)) 2218 vf_flush_wa = true; 2219 2220 /* WaForGAMHang:kbl */ 2221 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) 2222 dc_flush_wa = true; 2223 } 2224 2225 len = 6; 2226 2227 if (vf_flush_wa) 2228 len += 6; 2229 2230 if (dc_flush_wa) 2231 len += 12; 2232 2233 cs = intel_ring_begin(request, len); 2234 if (IS_ERR(cs)) 2235 return PTR_ERR(cs); 2236 2237 if (vf_flush_wa) 2238 cs = gen8_emit_pipe_control(cs, 0, 0); 2239 2240 if (dc_flush_wa) 2241 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, 2242 0); 2243 2244 cs = gen8_emit_pipe_control(cs, flags, scratch_addr); 2245 2246 if (dc_flush_wa) 2247 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); 2248 2249 intel_ring_advance(request, cs); 2250 2251 return 0; 2252 } 2253 2254 /* 2255 * Reserve space for 2 NOOPs at the end of each request to be 2256 * used as a workaround for not being allowed to do lite 2257 * restore with HEAD==TAIL (WaIdleLiteRestore). 2258 */ 2259 static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs) 2260 { 2261 /* Ensure there's always at least one preemption point per-request. */ 2262 *cs++ = MI_ARB_CHECK; 2263 *cs++ = MI_NOOP; 2264 request->wa_tail = intel_ring_offset(request, cs); 2265 2266 return cs; 2267 } 2268 2269 static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs) 2270 { 2271 cs = gen8_emit_ggtt_write(cs, 2272 request->fence.seqno, 2273 request->timeline->hwsp_offset, 2274 0); 2275 2276 cs = gen8_emit_ggtt_write(cs, 2277 intel_engine_next_hangcheck_seqno(request->engine), 2278 I915_GEM_HWS_HANGCHECK_ADDR, 2279 MI_FLUSH_DW_STORE_INDEX); 2280 2281 2282 *cs++ = MI_USER_INTERRUPT; 2283 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 2284 2285 request->tail = intel_ring_offset(request, cs); 2286 assert_ring_tail_valid(request->ring, request->tail); 2287 2288 return gen8_emit_wa_tail(request, cs); 2289 } 2290 2291 static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) 2292 { 2293 cs = gen8_emit_ggtt_write_rcs(cs, 2294 request->fence.seqno, 2295 request->timeline->hwsp_offset, 2296 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | 2297 PIPE_CONTROL_DEPTH_CACHE_FLUSH | 2298 PIPE_CONTROL_DC_FLUSH_ENABLE | 2299 PIPE_CONTROL_FLUSH_ENABLE | 2300 PIPE_CONTROL_CS_STALL); 2301 2302 cs = gen8_emit_ggtt_write_rcs(cs, 2303 intel_engine_next_hangcheck_seqno(request->engine), 2304 I915_GEM_HWS_HANGCHECK_ADDR, 2305 PIPE_CONTROL_STORE_DATA_INDEX); 2306 2307 *cs++ = MI_USER_INTERRUPT; 2308 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 2309 2310 request->tail = intel_ring_offset(request, cs); 2311 assert_ring_tail_valid(request->ring, request->tail); 2312 2313 return gen8_emit_wa_tail(request, cs); 2314 } 2315 2316 static int gen8_init_rcs_context(struct i915_request *rq) 2317 { 2318 int ret; 2319 2320 ret = intel_engine_emit_ctx_wa(rq); 2321 if (ret) 2322 return ret; 2323 2324 ret = intel_rcs_context_init_mocs(rq); 2325 /* 2326 * Failing to program the MOCS is non-fatal.The system will not 2327 * run at peak performance. So generate an error and carry on. 2328 */ 2329 if (ret) 2330 DRM_ERROR("MOCS failed to program: expect performance issues.\n"); 2331 2332 return i915_gem_render_state_emit(rq); 2333 } 2334 2335 static void execlists_park(struct intel_engine_cs *engine) 2336 { 2337 intel_engine_park(engine); 2338 } 2339 2340 void intel_execlists_set_default_submission(struct intel_engine_cs *engine) 2341 { 2342 engine->submit_request = execlists_submit_request; 2343 engine->cancel_requests = execlists_cancel_requests; 2344 engine->schedule = i915_schedule; 2345 engine->execlists.tasklet.func = execlists_submission_tasklet; 2346 2347 engine->reset.prepare = execlists_reset_prepare; 2348 engine->reset.reset = execlists_reset; 2349 engine->reset.finish = execlists_reset_finish; 2350 2351 engine->park = execlists_park; 2352 engine->unpark = NULL; 2353 2354 engine->flags |= I915_ENGINE_SUPPORTS_STATS; 2355 if (!intel_vgpu_active(engine->i915)) 2356 engine->flags |= I915_ENGINE_HAS_SEMAPHORES; 2357 if (engine->preempt_context && 2358 HAS_LOGICAL_RING_PREEMPTION(engine->i915)) 2359 engine->flags |= I915_ENGINE_HAS_PREEMPTION; 2360 } 2361 2362 static void execlists_destroy(struct intel_engine_cs *engine) 2363 { 2364 intel_engine_cleanup_common(engine); 2365 lrc_destroy_wa_ctx(engine); 2366 kfree(engine); 2367 } 2368 2369 static void 2370 logical_ring_default_vfuncs(struct intel_engine_cs *engine) 2371 { 2372 /* Default vfuncs which can be overriden by each engine. */ 2373 2374 engine->destroy = execlists_destroy; 2375 engine->resume = execlists_resume; 2376 2377 engine->reset.prepare = execlists_reset_prepare; 2378 engine->reset.reset = execlists_reset; 2379 engine->reset.finish = execlists_reset_finish; 2380 2381 engine->cops = &execlists_context_ops; 2382 engine->request_alloc = execlists_request_alloc; 2383 2384 engine->emit_flush = gen8_emit_flush; 2385 engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb; 2386 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb; 2387 2388 engine->set_default_submission = intel_execlists_set_default_submission; 2389 2390 if (INTEL_GEN(engine->i915) < 11) { 2391 engine->irq_enable = gen8_logical_ring_enable_irq; 2392 engine->irq_disable = gen8_logical_ring_disable_irq; 2393 } else { 2394 /* 2395 * TODO: On Gen11 interrupt masks need to be clear 2396 * to allow C6 entry. Keep interrupts enabled at 2397 * and take the hit of generating extra interrupts 2398 * until a more refined solution exists. 2399 */ 2400 } 2401 if (IS_GEN(engine->i915, 8)) 2402 engine->emit_bb_start = gen8_emit_bb_start; 2403 else 2404 engine->emit_bb_start = gen9_emit_bb_start; 2405 } 2406 2407 static inline void 2408 logical_ring_default_irqs(struct intel_engine_cs *engine) 2409 { 2410 unsigned int shift = 0; 2411 2412 if (INTEL_GEN(engine->i915) < 11) { 2413 const u8 irq_shifts[] = { 2414 [RCS0] = GEN8_RCS_IRQ_SHIFT, 2415 [BCS0] = GEN8_BCS_IRQ_SHIFT, 2416 [VCS0] = GEN8_VCS0_IRQ_SHIFT, 2417 [VCS1] = GEN8_VCS1_IRQ_SHIFT, 2418 [VECS0] = GEN8_VECS_IRQ_SHIFT, 2419 }; 2420 2421 shift = irq_shifts[engine->id]; 2422 } 2423 2424 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; 2425 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; 2426 } 2427 2428 int intel_execlists_submission_setup(struct intel_engine_cs *engine) 2429 { 2430 /* Intentionally left blank. */ 2431 engine->buffer = NULL; 2432 2433 tasklet_init(&engine->execlists.tasklet, 2434 execlists_submission_tasklet, (unsigned long)engine); 2435 2436 logical_ring_default_vfuncs(engine); 2437 logical_ring_default_irqs(engine); 2438 2439 if (engine->class == RENDER_CLASS) { 2440 engine->init_context = gen8_init_rcs_context; 2441 engine->emit_flush = gen8_emit_flush_render; 2442 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs; 2443 } 2444 2445 return 0; 2446 } 2447 2448 int intel_execlists_submission_init(struct intel_engine_cs *engine) 2449 { 2450 struct drm_i915_private *i915 = engine->i915; 2451 struct intel_engine_execlists * const execlists = &engine->execlists; 2452 u32 base = engine->mmio_base; 2453 int ret; 2454 2455 ret = intel_engine_init_common(engine); 2456 if (ret) 2457 return ret; 2458 2459 intel_engine_init_workarounds(engine); 2460 intel_engine_init_whitelist(engine); 2461 2462 if (intel_init_workaround_bb(engine)) 2463 /* 2464 * We continue even if we fail to initialize WA batch 2465 * because we only expect rare glitches but nothing 2466 * critical to prevent us from using GPU 2467 */ 2468 DRM_ERROR("WA batch buffer initialization failed\n"); 2469 2470 if (HAS_LOGICAL_RING_ELSQ(i915)) { 2471 execlists->submit_reg = i915->uncore.regs + 2472 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base)); 2473 execlists->ctrl_reg = i915->uncore.regs + 2474 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base)); 2475 } else { 2476 execlists->submit_reg = i915->uncore.regs + 2477 i915_mmio_reg_offset(RING_ELSP(base)); 2478 } 2479 2480 execlists->preempt_complete_status = ~0u; 2481 if (engine->preempt_context) 2482 execlists->preempt_complete_status = 2483 upper_32_bits(engine->preempt_context->lrc_desc); 2484 2485 execlists->csb_status = 2486 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; 2487 2488 execlists->csb_write = 2489 &engine->status_page.addr[intel_hws_csb_write_index(i915)]; 2490 2491 if (INTEL_GEN(engine->i915) < 11) 2492 execlists->csb_size = GEN8_CSB_ENTRIES; 2493 else 2494 execlists->csb_size = GEN11_CSB_ENTRIES; 2495 2496 reset_csb_pointers(execlists); 2497 2498 return 0; 2499 } 2500 2501 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) 2502 { 2503 u32 indirect_ctx_offset; 2504 2505 switch (INTEL_GEN(engine->i915)) { 2506 default: 2507 MISSING_CASE(INTEL_GEN(engine->i915)); 2508 /* fall through */ 2509 case 11: 2510 indirect_ctx_offset = 2511 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2512 break; 2513 case 10: 2514 indirect_ctx_offset = 2515 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2516 break; 2517 case 9: 2518 indirect_ctx_offset = 2519 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2520 break; 2521 case 8: 2522 indirect_ctx_offset = 2523 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2524 break; 2525 } 2526 2527 return indirect_ctx_offset; 2528 } 2529 2530 static void execlists_init_reg_state(u32 *regs, 2531 struct intel_context *ce, 2532 struct intel_engine_cs *engine, 2533 struct intel_ring *ring) 2534 { 2535 struct i915_hw_ppgtt *ppgtt = ce->gem_context->ppgtt; 2536 bool rcs = engine->class == RENDER_CLASS; 2537 u32 base = engine->mmio_base; 2538 2539 /* A context is actually a big batch buffer with several 2540 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The 2541 * values we are setting here are only for the first context restore: 2542 * on a subsequent save, the GPU will recreate this batchbuffer with new 2543 * values (including all the missing MI_LOAD_REGISTER_IMM commands that 2544 * we are not initializing here). 2545 */ 2546 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | 2547 MI_LRI_FORCE_POSTED; 2548 2549 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base), 2550 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) | 2551 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH)); 2552 if (INTEL_GEN(engine->i915) < 11) { 2553 regs[CTX_CONTEXT_CONTROL + 1] |= 2554 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT | 2555 CTX_CTRL_RS_CTX_ENABLE); 2556 } 2557 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0); 2558 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0); 2559 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); 2560 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), 2561 RING_CTL_SIZE(ring->size) | RING_VALID); 2562 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0); 2563 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0); 2564 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT); 2565 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0); 2566 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0); 2567 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0); 2568 if (rcs) { 2569 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; 2570 2571 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0); 2572 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET, 2573 RING_INDIRECT_CTX_OFFSET(base), 0); 2574 if (wa_ctx->indirect_ctx.size) { 2575 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); 2576 2577 regs[CTX_RCS_INDIRECT_CTX + 1] = 2578 (ggtt_offset + wa_ctx->indirect_ctx.offset) | 2579 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); 2580 2581 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = 2582 intel_lr_indirect_ctx_offset(engine) << 6; 2583 } 2584 2585 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0); 2586 if (wa_ctx->per_ctx.size) { 2587 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); 2588 2589 regs[CTX_BB_PER_CTX_PTR + 1] = 2590 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; 2591 } 2592 } 2593 2594 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; 2595 2596 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); 2597 /* PDP values well be assigned later if needed */ 2598 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0); 2599 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0); 2600 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(base, 2), 0); 2601 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(base, 2), 0); 2602 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(base, 1), 0); 2603 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(base, 1), 0); 2604 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(base, 0), 0); 2605 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(base, 0), 0); 2606 2607 if (i915_vm_is_4lvl(&ppgtt->vm)) { 2608 /* 64b PPGTT (48bit canonical) 2609 * PDP0_DESCRIPTOR contains the base address to PML4 and 2610 * other PDP Descriptors are ignored. 2611 */ 2612 ASSIGN_CTX_PML4(ppgtt, regs); 2613 } else { 2614 ASSIGN_CTX_PDP(ppgtt, regs, 3); 2615 ASSIGN_CTX_PDP(ppgtt, regs, 2); 2616 ASSIGN_CTX_PDP(ppgtt, regs, 1); 2617 ASSIGN_CTX_PDP(ppgtt, regs, 0); 2618 } 2619 2620 if (rcs) { 2621 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); 2622 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0); 2623 2624 i915_oa_init_reg_state(engine, ce, regs); 2625 } 2626 2627 regs[CTX_END] = MI_BATCH_BUFFER_END; 2628 if (INTEL_GEN(engine->i915) >= 10) 2629 regs[CTX_END] |= BIT(0); 2630 } 2631 2632 static int 2633 populate_lr_context(struct intel_context *ce, 2634 struct drm_i915_gem_object *ctx_obj, 2635 struct intel_engine_cs *engine, 2636 struct intel_ring *ring) 2637 { 2638 void *vaddr; 2639 u32 *regs; 2640 int ret; 2641 2642 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); 2643 if (IS_ERR(vaddr)) { 2644 ret = PTR_ERR(vaddr); 2645 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); 2646 return ret; 2647 } 2648 2649 if (engine->default_state) { 2650 /* 2651 * We only want to copy over the template context state; 2652 * skipping over the headers reserved for GuC communication, 2653 * leaving those as zero. 2654 */ 2655 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE; 2656 void *defaults; 2657 2658 defaults = i915_gem_object_pin_map(engine->default_state, 2659 I915_MAP_WB); 2660 if (IS_ERR(defaults)) { 2661 ret = PTR_ERR(defaults); 2662 goto err_unpin_ctx; 2663 } 2664 2665 memcpy(vaddr + start, defaults + start, engine->context_size); 2666 i915_gem_object_unpin_map(engine->default_state); 2667 } 2668 2669 /* The second page of the context object contains some fields which must 2670 * be set up prior to the first execution. */ 2671 regs = vaddr + LRC_STATE_PN * PAGE_SIZE; 2672 execlists_init_reg_state(regs, ce, engine, ring); 2673 if (!engine->default_state) 2674 regs[CTX_CONTEXT_CONTROL + 1] |= 2675 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 2676 if (ce->gem_context == engine->i915->preempt_context && 2677 INTEL_GEN(engine->i915) < 11) 2678 regs[CTX_CONTEXT_CONTROL + 1] |= 2679 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | 2680 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT); 2681 2682 ret = 0; 2683 err_unpin_ctx: 2684 __i915_gem_object_flush_map(ctx_obj, 2685 LRC_HEADER_PAGES * PAGE_SIZE, 2686 engine->context_size); 2687 i915_gem_object_unpin_map(ctx_obj); 2688 return ret; 2689 } 2690 2691 static struct i915_timeline *get_timeline(struct i915_gem_context *ctx) 2692 { 2693 if (ctx->timeline) 2694 return i915_timeline_get(ctx->timeline); 2695 else 2696 return i915_timeline_create(ctx->i915, NULL); 2697 } 2698 2699 static int execlists_context_deferred_alloc(struct intel_context *ce, 2700 struct intel_engine_cs *engine) 2701 { 2702 struct drm_i915_gem_object *ctx_obj; 2703 struct i915_vma *vma; 2704 u32 context_size; 2705 struct intel_ring *ring; 2706 struct i915_timeline *timeline; 2707 int ret; 2708 2709 if (ce->state) 2710 return 0; 2711 2712 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); 2713 2714 /* 2715 * Before the actual start of the context image, we insert a few pages 2716 * for our own use and for sharing with the GuC. 2717 */ 2718 context_size += LRC_HEADER_PAGES * PAGE_SIZE; 2719 2720 ctx_obj = i915_gem_object_create(engine->i915, context_size); 2721 if (IS_ERR(ctx_obj)) 2722 return PTR_ERR(ctx_obj); 2723 2724 vma = i915_vma_instance(ctx_obj, &engine->i915->ggtt.vm, NULL); 2725 if (IS_ERR(vma)) { 2726 ret = PTR_ERR(vma); 2727 goto error_deref_obj; 2728 } 2729 2730 timeline = get_timeline(ce->gem_context); 2731 if (IS_ERR(timeline)) { 2732 ret = PTR_ERR(timeline); 2733 goto error_deref_obj; 2734 } 2735 2736 ring = intel_engine_create_ring(engine, 2737 timeline, 2738 ce->gem_context->ring_size); 2739 i915_timeline_put(timeline); 2740 if (IS_ERR(ring)) { 2741 ret = PTR_ERR(ring); 2742 goto error_deref_obj; 2743 } 2744 2745 ret = populate_lr_context(ce, ctx_obj, engine, ring); 2746 if (ret) { 2747 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); 2748 goto error_ring_free; 2749 } 2750 2751 ce->ring = ring; 2752 ce->state = vma; 2753 2754 return 0; 2755 2756 error_ring_free: 2757 intel_ring_put(ring); 2758 error_deref_obj: 2759 i915_gem_object_put(ctx_obj); 2760 return ret; 2761 } 2762 2763 void intel_execlists_show_requests(struct intel_engine_cs *engine, 2764 struct drm_printer *m, 2765 void (*show_request)(struct drm_printer *m, 2766 struct i915_request *rq, 2767 const char *prefix), 2768 unsigned int max) 2769 { 2770 const struct intel_engine_execlists *execlists = &engine->execlists; 2771 struct i915_request *rq, *last; 2772 unsigned long flags; 2773 unsigned int count; 2774 struct rb_node *rb; 2775 2776 spin_lock_irqsave(&engine->timeline.lock, flags); 2777 2778 last = NULL; 2779 count = 0; 2780 list_for_each_entry(rq, &engine->timeline.requests, link) { 2781 if (count++ < max - 1) 2782 show_request(m, rq, "\t\tE "); 2783 else 2784 last = rq; 2785 } 2786 if (last) { 2787 if (count > max) { 2788 drm_printf(m, 2789 "\t\t...skipping %d executing requests...\n", 2790 count - max); 2791 } 2792 show_request(m, last, "\t\tE "); 2793 } 2794 2795 last = NULL; 2796 count = 0; 2797 if (execlists->queue_priority_hint != INT_MIN) 2798 drm_printf(m, "\t\tQueue priority hint: %d\n", 2799 execlists->queue_priority_hint); 2800 for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) { 2801 struct i915_priolist *p = rb_entry(rb, typeof(*p), node); 2802 int i; 2803 2804 priolist_for_each_request(rq, p, i) { 2805 if (count++ < max - 1) 2806 show_request(m, rq, "\t\tQ "); 2807 else 2808 last = rq; 2809 } 2810 } 2811 if (last) { 2812 if (count > max) { 2813 drm_printf(m, 2814 "\t\t...skipping %d queued requests...\n", 2815 count - max); 2816 } 2817 show_request(m, last, "\t\tQ "); 2818 } 2819 2820 spin_unlock_irqrestore(&engine->timeline.lock, flags); 2821 } 2822 2823 void intel_lr_context_reset(struct intel_engine_cs *engine, 2824 struct intel_context *ce, 2825 u32 head, 2826 bool scrub) 2827 { 2828 /* 2829 * We want a simple context + ring to execute the breadcrumb update. 2830 * We cannot rely on the context being intact across the GPU hang, 2831 * so clear it and rebuild just what we need for the breadcrumb. 2832 * All pending requests for this context will be zapped, and any 2833 * future request will be after userspace has had the opportunity 2834 * to recreate its own state. 2835 */ 2836 if (scrub) { 2837 u32 *regs = ce->lrc_reg_state; 2838 2839 if (engine->pinned_default_state) { 2840 memcpy(regs, /* skip restoring the vanilla PPHWSP */ 2841 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE, 2842 engine->context_size - PAGE_SIZE); 2843 } 2844 execlists_init_reg_state(regs, ce, engine, ce->ring); 2845 } 2846 2847 /* Rerun the request; its payload has been neutered (if guilty). */ 2848 ce->ring->head = head; 2849 intel_ring_update_space(ce->ring); 2850 2851 __execlists_update_reg_state(ce, engine); 2852 } 2853 2854 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2855 #include "selftest_lrc.c" 2856 #endif 2857