1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * Michel Thierry <michel.thierry@intel.com> 26 * Thomas Daniel <thomas.daniel@intel.com> 27 * Oscar Mateo <oscar.mateo@intel.com> 28 * 29 */ 30 31 /** 32 * DOC: Logical Rings, Logical Ring Contexts and Execlists 33 * 34 * Motivation: 35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". 36 * These expanded contexts enable a number of new abilities, especially 37 * "Execlists" (also implemented in this file). 38 * 39 * One of the main differences with the legacy HW contexts is that logical 40 * ring contexts incorporate many more things to the context's state, like 41 * PDPs or ringbuffer control registers: 42 * 43 * The reason why PDPs are included in the context is straightforward: as 44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs 45 * contained there mean you don't need to do a ppgtt->switch_mm yourself, 46 * instead, the GPU will do it for you on the context switch. 47 * 48 * But, what about the ringbuffer control registers (head, tail, etc..)? 49 * shouldn't we just need a set of those per engine command streamer? This is 50 * where the name "Logical Rings" starts to make sense: by virtualizing the 51 * rings, the engine cs shifts to a new "ring buffer" with every context 52 * switch. When you want to submit a workload to the GPU you: A) choose your 53 * context, B) find its appropriate virtualized ring, C) write commands to it 54 * and then, finally, D) tell the GPU to switch to that context. 55 * 56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch 57 * to a contexts is via a context execution list, ergo "Execlists". 58 * 59 * LRC implementation: 60 * Regarding the creation of contexts, we have: 61 * 62 * - One global default context. 63 * - One local default context for each opened fd. 64 * - One local extra context for each context create ioctl call. 65 * 66 * Now that ringbuffers belong per-context (and not per-engine, like before) 67 * and that contexts are uniquely tied to a given engine (and not reusable, 68 * like before) we need: 69 * 70 * - One ringbuffer per-engine inside each context. 71 * - One backing object per-engine inside each context. 72 * 73 * The global default context starts its life with these new objects fully 74 * allocated and populated. The local default context for each opened fd is 75 * more complex, because we don't know at creation time which engine is going 76 * to use them. To handle this, we have implemented a deferred creation of LR 77 * contexts: 78 * 79 * The local context starts its life as a hollow or blank holder, that only 80 * gets populated for a given engine once we receive an execbuffer. If later 81 * on we receive another execbuffer ioctl for the same context but a different 82 * engine, we allocate/populate a new ringbuffer and context backing object and 83 * so on. 84 * 85 * Finally, regarding local contexts created using the ioctl call: as they are 86 * only allowed with the render ring, we can allocate & populate them right 87 * away (no need to defer anything, at least for now). 88 * 89 * Execlists implementation: 90 * Execlists are the new method by which, on gen8+ hardware, workloads are 91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method). 92 * This method works as follows: 93 * 94 * When a request is committed, its commands (the BB start and any leading or 95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer 96 * for the appropriate context. The tail pointer in the hardware context is not 97 * updated at this time, but instead, kept by the driver in the ringbuffer 98 * structure. A structure representing this request is added to a request queue 99 * for the appropriate engine: this structure contains a copy of the context's 100 * tail after the request was written to the ring buffer and a pointer to the 101 * context itself. 102 * 103 * If the engine's request queue was empty before the request was added, the 104 * queue is processed immediately. Otherwise the queue will be processed during 105 * a context switch interrupt. In any case, elements on the queue will get sent 106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a 107 * globally unique 20-bits submission ID. 108 * 109 * When execution of a request completes, the GPU updates the context status 110 * buffer with a context complete event and generates a context switch interrupt. 111 * During the interrupt handling, the driver examines the events in the buffer: 112 * for each context complete event, if the announced ID matches that on the head 113 * of the request queue, then that request is retired and removed from the queue. 114 * 115 * After processing, if any requests were retired and the queue is not empty 116 * then a new execution list can be submitted. The two requests at the front of 117 * the queue are next to be submitted but since a context may not occur twice in 118 * an execution list, if subsequent requests have the same ID as the first then 119 * the two requests must be combined. This is done simply by discarding requests 120 * at the head of the queue until either only one requests is left (in which case 121 * we use a NULL second context) or the first two requests have unique IDs. 122 * 123 * By always executing the first two requests in the queue the driver ensures 124 * that the GPU is kept as busy as possible. In the case where a single context 125 * completes but a second context is still executing, the request for this second 126 * context will be at the head of the queue when we remove the first one. This 127 * request will then be resubmitted along with a new request for a different context, 128 * which will cause the hardware to continue executing the second request and queue 129 * the new request (the GPU detects the condition of a context getting preempted 130 * with the same context and optimizes the context switch flow by not doing 131 * preemption, but just sampling the new tail pointer). 132 * 133 */ 134 #include <linux/interrupt.h> 135 136 #include "gem/i915_gem_context.h" 137 138 #include "i915_drv.h" 139 #include "i915_gem_render_state.h" 140 #include "i915_vgpu.h" 141 #include "intel_engine_pm.h" 142 #include "intel_lrc_reg.h" 143 #include "intel_mocs.h" 144 #include "intel_reset.h" 145 #include "intel_workarounds.h" 146 147 #define RING_EXECLIST_QFULL (1 << 0x2) 148 #define RING_EXECLIST1_VALID (1 << 0x3) 149 #define RING_EXECLIST0_VALID (1 << 0x4) 150 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) 151 #define RING_EXECLIST1_ACTIVE (1 << 0x11) 152 #define RING_EXECLIST0_ACTIVE (1 << 0x12) 153 154 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) 155 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) 156 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) 157 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) 158 #define GEN8_CTX_STATUS_COMPLETE (1 << 4) 159 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) 160 161 #define GEN8_CTX_STATUS_COMPLETED_MASK \ 162 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED) 163 164 /* Typical size of the average request (2 pipecontrols and a MI_BB) */ 165 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ 166 #define WA_TAIL_DWORDS 2 167 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS) 168 169 struct virtual_engine { 170 struct intel_engine_cs base; 171 struct intel_context context; 172 173 /* 174 * We allow only a single request through the virtual engine at a time 175 * (each request in the timeline waits for the completion fence of 176 * the previous before being submitted). By restricting ourselves to 177 * only submitting a single request, each request is placed on to a 178 * physical to maximise load spreading (by virtue of the late greedy 179 * scheduling -- each real engine takes the next available request 180 * upon idling). 181 */ 182 struct i915_request *request; 183 184 /* 185 * We keep a rbtree of available virtual engines inside each physical 186 * engine, sorted by priority. Here we preallocate the nodes we need 187 * for the virtual engine, indexed by physical_engine->id. 188 */ 189 struct ve_node { 190 struct rb_node rb; 191 int prio; 192 } nodes[I915_NUM_ENGINES]; 193 194 /* 195 * Keep track of bonded pairs -- restrictions upon on our selection 196 * of physical engines any particular request may be submitted to. 197 * If we receive a submit-fence from a master engine, we will only 198 * use one of sibling_mask physical engines. 199 */ 200 struct ve_bond { 201 const struct intel_engine_cs *master; 202 intel_engine_mask_t sibling_mask; 203 } *bonds; 204 unsigned int num_bonds; 205 206 /* And finally, which physical engines this virtual engine maps onto. */ 207 unsigned int num_siblings; 208 struct intel_engine_cs *siblings[0]; 209 }; 210 211 static struct virtual_engine *to_virtual_engine(struct intel_engine_cs *engine) 212 { 213 GEM_BUG_ON(!intel_engine_is_virtual(engine)); 214 return container_of(engine, struct virtual_engine, base); 215 } 216 217 static int execlists_context_deferred_alloc(struct intel_context *ce, 218 struct intel_engine_cs *engine); 219 static void execlists_init_reg_state(u32 *reg_state, 220 struct intel_context *ce, 221 struct intel_engine_cs *engine, 222 struct intel_ring *ring); 223 224 static inline struct i915_priolist *to_priolist(struct rb_node *rb) 225 { 226 return rb_entry(rb, struct i915_priolist, node); 227 } 228 229 static inline int rq_prio(const struct i915_request *rq) 230 { 231 return rq->sched.attr.priority; 232 } 233 234 static int effective_prio(const struct i915_request *rq) 235 { 236 int prio = rq_prio(rq); 237 238 /* 239 * On unwinding the active request, we give it a priority bump 240 * if it has completed waiting on any semaphore. If we know that 241 * the request has already started, we can prevent an unwanted 242 * preempt-to-idle cycle by taking that into account now. 243 */ 244 if (__i915_request_has_started(rq)) 245 prio |= I915_PRIORITY_NOSEMAPHORE; 246 247 /* Restrict mere WAIT boosts from triggering preemption */ 248 return prio | __NO_PREEMPTION; 249 } 250 251 static int queue_prio(const struct intel_engine_execlists *execlists) 252 { 253 struct i915_priolist *p; 254 struct rb_node *rb; 255 256 rb = rb_first_cached(&execlists->queue); 257 if (!rb) 258 return INT_MIN; 259 260 /* 261 * As the priolist[] are inverted, with the highest priority in [0], 262 * we have to flip the index value to become priority. 263 */ 264 p = to_priolist(rb); 265 return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used); 266 } 267 268 static inline bool need_preempt(const struct intel_engine_cs *engine, 269 const struct i915_request *rq, 270 struct rb_node *rb) 271 { 272 int last_prio; 273 274 if (!engine->preempt_context) 275 return false; 276 277 if (i915_request_completed(rq)) 278 return false; 279 280 /* 281 * Check if the current priority hint merits a preemption attempt. 282 * 283 * We record the highest value priority we saw during rescheduling 284 * prior to this dequeue, therefore we know that if it is strictly 285 * less than the current tail of ESLP[0], we do not need to force 286 * a preempt-to-idle cycle. 287 * 288 * However, the priority hint is a mere hint that we may need to 289 * preempt. If that hint is stale or we may be trying to preempt 290 * ourselves, ignore the request. 291 */ 292 last_prio = effective_prio(rq); 293 if (!i915_scheduler_need_preempt(engine->execlists.queue_priority_hint, 294 last_prio)) 295 return false; 296 297 /* 298 * Check against the first request in ELSP[1], it will, thanks to the 299 * power of PI, be the highest priority of that context. 300 */ 301 if (!list_is_last(&rq->link, &engine->timeline.requests) && 302 rq_prio(list_next_entry(rq, link)) > last_prio) 303 return true; 304 305 if (rb) { 306 struct virtual_engine *ve = 307 rb_entry(rb, typeof(*ve), nodes[engine->id].rb); 308 bool preempt = false; 309 310 if (engine == ve->siblings[0]) { /* only preempt one sibling */ 311 struct i915_request *next; 312 313 rcu_read_lock(); 314 next = READ_ONCE(ve->request); 315 if (next) 316 preempt = rq_prio(next) > last_prio; 317 rcu_read_unlock(); 318 } 319 320 if (preempt) 321 return preempt; 322 } 323 324 /* 325 * If the inflight context did not trigger the preemption, then maybe 326 * it was the set of queued requests? Pick the highest priority in 327 * the queue (the first active priolist) and see if it deserves to be 328 * running instead of ELSP[0]. 329 * 330 * The highest priority request in the queue can not be either 331 * ELSP[0] or ELSP[1] as, thanks again to PI, if it was the same 332 * context, it's priority would not exceed ELSP[0] aka last_prio. 333 */ 334 return queue_prio(&engine->execlists) > last_prio; 335 } 336 337 __maybe_unused static inline bool 338 assert_priority_queue(const struct i915_request *prev, 339 const struct i915_request *next) 340 { 341 const struct intel_engine_execlists *execlists = 342 &prev->engine->execlists; 343 344 /* 345 * Without preemption, the prev may refer to the still active element 346 * which we refuse to let go. 347 * 348 * Even with preemption, there are times when we think it is better not 349 * to preempt and leave an ostensibly lower priority request in flight. 350 */ 351 if (port_request(execlists->port) == prev) 352 return true; 353 354 return rq_prio(prev) >= rq_prio(next); 355 } 356 357 /* 358 * The context descriptor encodes various attributes of a context, 359 * including its GTT address and some flags. Because it's fairly 360 * expensive to calculate, we'll just do it once and cache the result, 361 * which remains valid until the context is unpinned. 362 * 363 * This is what a descriptor looks like, from LSB to MSB:: 364 * 365 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template) 366 * bits 12-31: LRCA, GTT address of (the HWSP of) this context 367 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC) 368 * bits 53-54: mbz, reserved for use by hardware 369 * bits 55-63: group ID, currently unused and set to 0 370 * 371 * Starting from Gen11, the upper dword of the descriptor has a new format: 372 * 373 * bits 32-36: reserved 374 * bits 37-47: SW context ID 375 * bits 48:53: engine instance 376 * bit 54: mbz, reserved for use by hardware 377 * bits 55-60: SW counter 378 * bits 61-63: engine class 379 * 380 * engine info, SW context ID and SW counter need to form a unique number 381 * (Context ID) per lrc. 382 */ 383 static u64 384 lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine) 385 { 386 struct i915_gem_context *ctx = ce->gem_context; 387 u64 desc; 388 389 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH))); 390 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH))); 391 392 desc = ctx->desc_template; /* bits 0-11 */ 393 GEM_BUG_ON(desc & GENMASK_ULL(63, 12)); 394 395 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE; 396 /* bits 12-31 */ 397 GEM_BUG_ON(desc & GENMASK_ULL(63, 32)); 398 399 /* 400 * The following 32bits are copied into the OA reports (dword 2). 401 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing 402 * anything below. 403 */ 404 if (INTEL_GEN(engine->i915) >= 11) { 405 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH)); 406 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT; 407 /* bits 37-47 */ 408 409 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT; 410 /* bits 48-53 */ 411 412 /* TODO: decide what to do with SW counter (bits 55-60) */ 413 414 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT; 415 /* bits 61-63 */ 416 } else { 417 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH)); 418 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ 419 } 420 421 return desc; 422 } 423 424 static void unwind_wa_tail(struct i915_request *rq) 425 { 426 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES); 427 assert_ring_tail_valid(rq->ring, rq->tail); 428 } 429 430 static struct i915_request * 431 __unwind_incomplete_requests(struct intel_engine_cs *engine) 432 { 433 struct i915_request *rq, *rn, *active = NULL; 434 struct list_head *uninitialized_var(pl); 435 int prio = I915_PRIORITY_INVALID; 436 437 lockdep_assert_held(&engine->timeline.lock); 438 439 list_for_each_entry_safe_reverse(rq, rn, 440 &engine->timeline.requests, 441 link) { 442 struct intel_engine_cs *owner; 443 444 if (i915_request_completed(rq)) 445 break; 446 447 __i915_request_unsubmit(rq); 448 unwind_wa_tail(rq); 449 450 GEM_BUG_ON(rq->hw_context->inflight); 451 452 /* 453 * Push the request back into the queue for later resubmission. 454 * If this request is not native to this physical engine (i.e. 455 * it came from a virtual source), push it back onto the virtual 456 * engine so that it can be moved across onto another physical 457 * engine as load dictates. 458 */ 459 owner = rq->hw_context->engine; 460 if (likely(owner == engine)) { 461 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); 462 if (rq_prio(rq) != prio) { 463 prio = rq_prio(rq); 464 pl = i915_sched_lookup_priolist(engine, prio); 465 } 466 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); 467 468 list_add(&rq->sched.link, pl); 469 active = rq; 470 } else { 471 rq->engine = owner; 472 owner->submit_request(rq); 473 active = NULL; 474 } 475 } 476 477 return active; 478 } 479 480 struct i915_request * 481 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists) 482 { 483 struct intel_engine_cs *engine = 484 container_of(execlists, typeof(*engine), execlists); 485 486 return __unwind_incomplete_requests(engine); 487 } 488 489 static inline void 490 execlists_context_status_change(struct i915_request *rq, unsigned long status) 491 { 492 /* 493 * Only used when GVT-g is enabled now. When GVT-g is disabled, 494 * The compiler should eliminate this function as dead-code. 495 */ 496 if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) 497 return; 498 499 atomic_notifier_call_chain(&rq->engine->context_status_notifier, 500 status, rq); 501 } 502 503 inline void 504 execlists_user_begin(struct intel_engine_execlists *execlists, 505 const struct execlist_port *port) 506 { 507 execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER); 508 } 509 510 inline void 511 execlists_user_end(struct intel_engine_execlists *execlists) 512 { 513 execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER); 514 } 515 516 static inline void 517 execlists_context_schedule_in(struct i915_request *rq) 518 { 519 GEM_BUG_ON(rq->hw_context->inflight); 520 521 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); 522 intel_engine_context_in(rq->engine); 523 rq->hw_context->inflight = rq->engine; 524 } 525 526 static void kick_siblings(struct i915_request *rq) 527 { 528 struct virtual_engine *ve = to_virtual_engine(rq->hw_context->engine); 529 struct i915_request *next = READ_ONCE(ve->request); 530 531 if (next && next->execution_mask & ~rq->execution_mask) 532 tasklet_schedule(&ve->base.execlists.tasklet); 533 } 534 535 static inline void 536 execlists_context_schedule_out(struct i915_request *rq, unsigned long status) 537 { 538 rq->hw_context->inflight = NULL; 539 intel_engine_context_out(rq->engine); 540 execlists_context_status_change(rq, status); 541 trace_i915_request_out(rq); 542 543 /* 544 * If this is part of a virtual engine, its next request may have 545 * been blocked waiting for access to the active context. We have 546 * to kick all the siblings again in case we need to switch (e.g. 547 * the next request is not runnable on this engine). Hopefully, 548 * we will already have submitted the next request before the 549 * tasklet runs and do not need to rebuild each virtual tree 550 * and kick everyone again. 551 */ 552 if (rq->engine != rq->hw_context->engine) 553 kick_siblings(rq); 554 } 555 556 static u64 execlists_update_context(struct i915_request *rq) 557 { 558 struct intel_context *ce = rq->hw_context; 559 560 ce->lrc_reg_state[CTX_RING_TAIL + 1] = 561 intel_ring_set_tail(rq->ring, rq->tail); 562 563 /* 564 * Make sure the context image is complete before we submit it to HW. 565 * 566 * Ostensibly, writes (including the WCB) should be flushed prior to 567 * an uncached write such as our mmio register access, the empirical 568 * evidence (esp. on Braswell) suggests that the WC write into memory 569 * may not be visible to the HW prior to the completion of the UC 570 * register write and that we may begin execution from the context 571 * before its image is complete leading to invalid PD chasing. 572 * 573 * Furthermore, Braswell, at least, wants a full mb to be sure that 574 * the writes are coherent in memory (visible to the GPU) prior to 575 * execution, and not just visible to other CPUs (as is the result of 576 * wmb). 577 */ 578 mb(); 579 return ce->lrc_desc; 580 } 581 582 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port) 583 { 584 if (execlists->ctrl_reg) { 585 writel(lower_32_bits(desc), execlists->submit_reg + port * 2); 586 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1); 587 } else { 588 writel(upper_32_bits(desc), execlists->submit_reg); 589 writel(lower_32_bits(desc), execlists->submit_reg); 590 } 591 } 592 593 static void execlists_submit_ports(struct intel_engine_cs *engine) 594 { 595 struct intel_engine_execlists *execlists = &engine->execlists; 596 struct execlist_port *port = execlists->port; 597 unsigned int n; 598 599 /* 600 * We can skip acquiring intel_runtime_pm_get() here as it was taken 601 * on our behalf by the request (see i915_gem_mark_busy()) and it will 602 * not be relinquished until the device is idle (see 603 * i915_gem_idle_work_handler()). As a precaution, we make sure 604 * that all ELSP are drained i.e. we have processed the CSB, 605 * before allowing ourselves to idle and calling intel_runtime_pm_put(). 606 */ 607 GEM_BUG_ON(!intel_wakeref_active(&engine->wakeref)); 608 609 /* 610 * ELSQ note: the submit queue is not cleared after being submitted 611 * to the HW so we need to make sure we always clean it up. This is 612 * currently ensured by the fact that we always write the same number 613 * of elsq entries, keep this in mind before changing the loop below. 614 */ 615 for (n = execlists_num_ports(execlists); n--; ) { 616 struct i915_request *rq; 617 unsigned int count; 618 u64 desc; 619 620 rq = port_unpack(&port[n], &count); 621 if (rq) { 622 GEM_BUG_ON(count > !n); 623 if (!count++) 624 execlists_context_schedule_in(rq); 625 port_set(&port[n], port_pack(rq, count)); 626 desc = execlists_update_context(rq); 627 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); 628 629 GEM_TRACE("%s in[%d]: ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n", 630 engine->name, n, 631 port[n].context_id, count, 632 rq->fence.context, rq->fence.seqno, 633 hwsp_seqno(rq), 634 rq_prio(rq)); 635 } else { 636 GEM_BUG_ON(!n); 637 desc = 0; 638 } 639 640 write_desc(execlists, desc, n); 641 } 642 643 /* we need to manually load the submit queue */ 644 if (execlists->ctrl_reg) 645 writel(EL_CTRL_LOAD, execlists->ctrl_reg); 646 647 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); 648 } 649 650 static bool ctx_single_port_submission(const struct intel_context *ce) 651 { 652 return (IS_ENABLED(CONFIG_DRM_I915_GVT) && 653 i915_gem_context_force_single_submission(ce->gem_context)); 654 } 655 656 static bool can_merge_ctx(const struct intel_context *prev, 657 const struct intel_context *next) 658 { 659 if (prev != next) 660 return false; 661 662 if (ctx_single_port_submission(prev)) 663 return false; 664 665 return true; 666 } 667 668 static bool can_merge_rq(const struct i915_request *prev, 669 const struct i915_request *next) 670 { 671 GEM_BUG_ON(!assert_priority_queue(prev, next)); 672 673 if (!can_merge_ctx(prev->hw_context, next->hw_context)) 674 return false; 675 676 return true; 677 } 678 679 static void port_assign(struct execlist_port *port, struct i915_request *rq) 680 { 681 GEM_BUG_ON(rq == port_request(port)); 682 683 if (port_isset(port)) 684 i915_request_put(port_request(port)); 685 686 port_set(port, port_pack(i915_request_get(rq), port_count(port))); 687 } 688 689 static void inject_preempt_context(struct intel_engine_cs *engine) 690 { 691 struct intel_engine_execlists *execlists = &engine->execlists; 692 struct intel_context *ce = engine->preempt_context; 693 unsigned int n; 694 695 GEM_BUG_ON(execlists->preempt_complete_status != 696 upper_32_bits(ce->lrc_desc)); 697 698 /* 699 * Switch to our empty preempt context so 700 * the state of the GPU is known (idle). 701 */ 702 GEM_TRACE("%s\n", engine->name); 703 for (n = execlists_num_ports(execlists); --n; ) 704 write_desc(execlists, 0, n); 705 706 write_desc(execlists, ce->lrc_desc, n); 707 708 /* we need to manually load the submit queue */ 709 if (execlists->ctrl_reg) 710 writel(EL_CTRL_LOAD, execlists->ctrl_reg); 711 712 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); 713 execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT); 714 715 (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++); 716 } 717 718 static void complete_preempt_context(struct intel_engine_execlists *execlists) 719 { 720 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT)); 721 722 if (inject_preempt_hang(execlists)) 723 return; 724 725 execlists_cancel_port_requests(execlists); 726 __unwind_incomplete_requests(container_of(execlists, 727 struct intel_engine_cs, 728 execlists)); 729 } 730 731 static void virtual_update_register_offsets(u32 *regs, 732 struct intel_engine_cs *engine) 733 { 734 u32 base = engine->mmio_base; 735 736 /* Must match execlists_init_reg_state()! */ 737 738 regs[CTX_CONTEXT_CONTROL] = 739 i915_mmio_reg_offset(RING_CONTEXT_CONTROL(base)); 740 regs[CTX_RING_HEAD] = i915_mmio_reg_offset(RING_HEAD(base)); 741 regs[CTX_RING_TAIL] = i915_mmio_reg_offset(RING_TAIL(base)); 742 regs[CTX_RING_BUFFER_START] = i915_mmio_reg_offset(RING_START(base)); 743 regs[CTX_RING_BUFFER_CONTROL] = i915_mmio_reg_offset(RING_CTL(base)); 744 745 regs[CTX_BB_HEAD_U] = i915_mmio_reg_offset(RING_BBADDR_UDW(base)); 746 regs[CTX_BB_HEAD_L] = i915_mmio_reg_offset(RING_BBADDR(base)); 747 regs[CTX_BB_STATE] = i915_mmio_reg_offset(RING_BBSTATE(base)); 748 regs[CTX_SECOND_BB_HEAD_U] = 749 i915_mmio_reg_offset(RING_SBBADDR_UDW(base)); 750 regs[CTX_SECOND_BB_HEAD_L] = i915_mmio_reg_offset(RING_SBBADDR(base)); 751 regs[CTX_SECOND_BB_STATE] = i915_mmio_reg_offset(RING_SBBSTATE(base)); 752 753 regs[CTX_CTX_TIMESTAMP] = 754 i915_mmio_reg_offset(RING_CTX_TIMESTAMP(base)); 755 regs[CTX_PDP3_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 3)); 756 regs[CTX_PDP3_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 3)); 757 regs[CTX_PDP2_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 2)); 758 regs[CTX_PDP2_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 2)); 759 regs[CTX_PDP1_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 1)); 760 regs[CTX_PDP1_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 1)); 761 regs[CTX_PDP0_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0)); 762 regs[CTX_PDP0_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0)); 763 764 if (engine->class == RENDER_CLASS) { 765 regs[CTX_RCS_INDIRECT_CTX] = 766 i915_mmio_reg_offset(RING_INDIRECT_CTX(base)); 767 regs[CTX_RCS_INDIRECT_CTX_OFFSET] = 768 i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(base)); 769 regs[CTX_BB_PER_CTX_PTR] = 770 i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(base)); 771 772 regs[CTX_R_PWR_CLK_STATE] = 773 i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE); 774 } 775 } 776 777 static bool virtual_matches(const struct virtual_engine *ve, 778 const struct i915_request *rq, 779 const struct intel_engine_cs *engine) 780 { 781 const struct intel_engine_cs *inflight; 782 783 if (!(rq->execution_mask & engine->mask)) /* We peeked too soon! */ 784 return false; 785 786 /* 787 * We track when the HW has completed saving the context image 788 * (i.e. when we have seen the final CS event switching out of 789 * the context) and must not overwrite the context image before 790 * then. This restricts us to only using the active engine 791 * while the previous virtualized request is inflight (so 792 * we reuse the register offsets). This is a very small 793 * hystersis on the greedy seelction algorithm. 794 */ 795 inflight = READ_ONCE(ve->context.inflight); 796 if (inflight && inflight != engine) 797 return false; 798 799 return true; 800 } 801 802 static void virtual_xfer_breadcrumbs(struct virtual_engine *ve, 803 struct intel_engine_cs *engine) 804 { 805 struct intel_engine_cs *old = ve->siblings[0]; 806 807 /* All unattached (rq->engine == old) must already be completed */ 808 809 spin_lock(&old->breadcrumbs.irq_lock); 810 if (!list_empty(&ve->context.signal_link)) { 811 list_move_tail(&ve->context.signal_link, 812 &engine->breadcrumbs.signalers); 813 intel_engine_queue_breadcrumbs(engine); 814 } 815 spin_unlock(&old->breadcrumbs.irq_lock); 816 } 817 818 static void execlists_dequeue(struct intel_engine_cs *engine) 819 { 820 struct intel_engine_execlists * const execlists = &engine->execlists; 821 struct execlist_port *port = execlists->port; 822 const struct execlist_port * const last_port = 823 &execlists->port[execlists->port_mask]; 824 struct i915_request *last = port_request(port); 825 struct rb_node *rb; 826 bool submit = false; 827 828 /* 829 * Hardware submission is through 2 ports. Conceptually each port 830 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is 831 * static for a context, and unique to each, so we only execute 832 * requests belonging to a single context from each ring. RING_HEAD 833 * is maintained by the CS in the context image, it marks the place 834 * where it got up to last time, and through RING_TAIL we tell the CS 835 * where we want to execute up to this time. 836 * 837 * In this list the requests are in order of execution. Consecutive 838 * requests from the same context are adjacent in the ringbuffer. We 839 * can combine these requests into a single RING_TAIL update: 840 * 841 * RING_HEAD...req1...req2 842 * ^- RING_TAIL 843 * since to execute req2 the CS must first execute req1. 844 * 845 * Our goal then is to point each port to the end of a consecutive 846 * sequence of requests as being the most optimal (fewest wake ups 847 * and context switches) submission. 848 */ 849 850 for (rb = rb_first_cached(&execlists->virtual); rb; ) { 851 struct virtual_engine *ve = 852 rb_entry(rb, typeof(*ve), nodes[engine->id].rb); 853 struct i915_request *rq = READ_ONCE(ve->request); 854 855 if (!rq) { /* lazily cleanup after another engine handled rq */ 856 rb_erase_cached(rb, &execlists->virtual); 857 RB_CLEAR_NODE(rb); 858 rb = rb_first_cached(&execlists->virtual); 859 continue; 860 } 861 862 if (!virtual_matches(ve, rq, engine)) { 863 rb = rb_next(rb); 864 continue; 865 } 866 867 break; 868 } 869 870 if (last) { 871 /* 872 * Don't resubmit or switch until all outstanding 873 * preemptions (lite-restore) are seen. Then we 874 * know the next preemption status we see corresponds 875 * to this ELSP update. 876 */ 877 GEM_BUG_ON(!execlists_is_active(execlists, 878 EXECLISTS_ACTIVE_USER)); 879 GEM_BUG_ON(!port_count(&port[0])); 880 881 /* 882 * If we write to ELSP a second time before the HW has had 883 * a chance to respond to the previous write, we can confuse 884 * the HW and hit "undefined behaviour". After writing to ELSP, 885 * we must then wait until we see a context-switch event from 886 * the HW to indicate that it has had a chance to respond. 887 */ 888 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK)) 889 return; 890 891 if (need_preempt(engine, last, rb)) { 892 inject_preempt_context(engine); 893 return; 894 } 895 896 /* 897 * In theory, we could coalesce more requests onto 898 * the second port (the first port is active, with 899 * no preemptions pending). However, that means we 900 * then have to deal with the possible lite-restore 901 * of the second port (as we submit the ELSP, there 902 * may be a context-switch) but also we may complete 903 * the resubmission before the context-switch. Ergo, 904 * coalescing onto the second port will cause a 905 * preemption event, but we cannot predict whether 906 * that will affect port[0] or port[1]. 907 * 908 * If the second port is already active, we can wait 909 * until the next context-switch before contemplating 910 * new requests. The GPU will be busy and we should be 911 * able to resubmit the new ELSP before it idles, 912 * avoiding pipeline bubbles (momentary pauses where 913 * the driver is unable to keep up the supply of new 914 * work). However, we have to double check that the 915 * priorities of the ports haven't been switch. 916 */ 917 if (port_count(&port[1])) 918 return; 919 920 /* 921 * WaIdleLiteRestore:bdw,skl 922 * Apply the wa NOOPs to prevent 923 * ring:HEAD == rq:TAIL as we resubmit the 924 * request. See gen8_emit_fini_breadcrumb() for 925 * where we prepare the padding after the 926 * end of the request. 927 */ 928 last->tail = last->wa_tail; 929 } 930 931 while (rb) { /* XXX virtual is always taking precedence */ 932 struct virtual_engine *ve = 933 rb_entry(rb, typeof(*ve), nodes[engine->id].rb); 934 struct i915_request *rq; 935 936 spin_lock(&ve->base.timeline.lock); 937 938 rq = ve->request; 939 if (unlikely(!rq)) { /* lost the race to a sibling */ 940 spin_unlock(&ve->base.timeline.lock); 941 rb_erase_cached(rb, &execlists->virtual); 942 RB_CLEAR_NODE(rb); 943 rb = rb_first_cached(&execlists->virtual); 944 continue; 945 } 946 947 GEM_BUG_ON(rq != ve->request); 948 GEM_BUG_ON(rq->engine != &ve->base); 949 GEM_BUG_ON(rq->hw_context != &ve->context); 950 951 if (rq_prio(rq) >= queue_prio(execlists)) { 952 if (!virtual_matches(ve, rq, engine)) { 953 spin_unlock(&ve->base.timeline.lock); 954 rb = rb_next(rb); 955 continue; 956 } 957 958 if (last && !can_merge_rq(last, rq)) { 959 spin_unlock(&ve->base.timeline.lock); 960 return; /* leave this rq for another engine */ 961 } 962 963 GEM_TRACE("%s: virtual rq=%llx:%lld%s, new engine? %s\n", 964 engine->name, 965 rq->fence.context, 966 rq->fence.seqno, 967 i915_request_completed(rq) ? "!" : 968 i915_request_started(rq) ? "*" : 969 "", 970 yesno(engine != ve->siblings[0])); 971 972 ve->request = NULL; 973 ve->base.execlists.queue_priority_hint = INT_MIN; 974 rb_erase_cached(rb, &execlists->virtual); 975 RB_CLEAR_NODE(rb); 976 977 GEM_BUG_ON(!(rq->execution_mask & engine->mask)); 978 rq->engine = engine; 979 980 if (engine != ve->siblings[0]) { 981 u32 *regs = ve->context.lrc_reg_state; 982 unsigned int n; 983 984 GEM_BUG_ON(READ_ONCE(ve->context.inflight)); 985 virtual_update_register_offsets(regs, engine); 986 987 if (!list_empty(&ve->context.signals)) 988 virtual_xfer_breadcrumbs(ve, engine); 989 990 /* 991 * Move the bound engine to the top of the list 992 * for future execution. We then kick this 993 * tasklet first before checking others, so that 994 * we preferentially reuse this set of bound 995 * registers. 996 */ 997 for (n = 1; n < ve->num_siblings; n++) { 998 if (ve->siblings[n] == engine) { 999 swap(ve->siblings[n], 1000 ve->siblings[0]); 1001 break; 1002 } 1003 } 1004 1005 GEM_BUG_ON(ve->siblings[0] != engine); 1006 } 1007 1008 __i915_request_submit(rq); 1009 trace_i915_request_in(rq, port_index(port, execlists)); 1010 submit = true; 1011 last = rq; 1012 } 1013 1014 spin_unlock(&ve->base.timeline.lock); 1015 break; 1016 } 1017 1018 while ((rb = rb_first_cached(&execlists->queue))) { 1019 struct i915_priolist *p = to_priolist(rb); 1020 struct i915_request *rq, *rn; 1021 int i; 1022 1023 priolist_for_each_request_consume(rq, rn, p, i) { 1024 /* 1025 * Can we combine this request with the current port? 1026 * It has to be the same context/ringbuffer and not 1027 * have any exceptions (e.g. GVT saying never to 1028 * combine contexts). 1029 * 1030 * If we can combine the requests, we can execute both 1031 * by updating the RING_TAIL to point to the end of the 1032 * second request, and so we never need to tell the 1033 * hardware about the first. 1034 */ 1035 if (last && !can_merge_rq(last, rq)) { 1036 /* 1037 * If we are on the second port and cannot 1038 * combine this request with the last, then we 1039 * are done. 1040 */ 1041 if (port == last_port) 1042 goto done; 1043 1044 /* 1045 * We must not populate both ELSP[] with the 1046 * same LRCA, i.e. we must submit 2 different 1047 * contexts if we submit 2 ELSP. 1048 */ 1049 if (last->hw_context == rq->hw_context) 1050 goto done; 1051 1052 /* 1053 * If GVT overrides us we only ever submit 1054 * port[0], leaving port[1] empty. Note that we 1055 * also have to be careful that we don't queue 1056 * the same context (even though a different 1057 * request) to the second port. 1058 */ 1059 if (ctx_single_port_submission(last->hw_context) || 1060 ctx_single_port_submission(rq->hw_context)) 1061 goto done; 1062 1063 1064 if (submit) 1065 port_assign(port, last); 1066 port++; 1067 1068 GEM_BUG_ON(port_isset(port)); 1069 } 1070 1071 list_del_init(&rq->sched.link); 1072 1073 __i915_request_submit(rq); 1074 trace_i915_request_in(rq, port_index(port, execlists)); 1075 1076 last = rq; 1077 submit = true; 1078 } 1079 1080 rb_erase_cached(&p->node, &execlists->queue); 1081 i915_priolist_free(p); 1082 } 1083 1084 done: 1085 /* 1086 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer. 1087 * 1088 * We choose the priority hint such that if we add a request of greater 1089 * priority than this, we kick the submission tasklet to decide on 1090 * the right order of submitting the requests to hardware. We must 1091 * also be prepared to reorder requests as they are in-flight on the 1092 * HW. We derive the priority hint then as the first "hole" in 1093 * the HW submission ports and if there are no available slots, 1094 * the priority of the lowest executing request, i.e. last. 1095 * 1096 * When we do receive a higher priority request ready to run from the 1097 * user, see queue_request(), the priority hint is bumped to that 1098 * request triggering preemption on the next dequeue (or subsequent 1099 * interrupt for secondary ports). 1100 */ 1101 execlists->queue_priority_hint = queue_prio(execlists); 1102 1103 if (submit) { 1104 port_assign(port, last); 1105 execlists_submit_ports(engine); 1106 } 1107 1108 /* We must always keep the beast fed if we have work piled up */ 1109 GEM_BUG_ON(rb_first_cached(&execlists->queue) && 1110 !port_isset(execlists->port)); 1111 1112 /* Re-evaluate the executing context setup after each preemptive kick */ 1113 if (last) 1114 execlists_user_begin(execlists, execlists->port); 1115 1116 /* If the engine is now idle, so should be the flag; and vice versa. */ 1117 GEM_BUG_ON(execlists_is_active(&engine->execlists, 1118 EXECLISTS_ACTIVE_USER) == 1119 !port_isset(engine->execlists.port)); 1120 } 1121 1122 void 1123 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists) 1124 { 1125 struct execlist_port *port = execlists->port; 1126 unsigned int num_ports = execlists_num_ports(execlists); 1127 1128 while (num_ports-- && port_isset(port)) { 1129 struct i915_request *rq = port_request(port); 1130 1131 GEM_TRACE("%s:port%u fence %llx:%lld, (current %d)\n", 1132 rq->engine->name, 1133 (unsigned int)(port - execlists->port), 1134 rq->fence.context, rq->fence.seqno, 1135 hwsp_seqno(rq)); 1136 1137 GEM_BUG_ON(!execlists->active); 1138 execlists_context_schedule_out(rq, 1139 i915_request_completed(rq) ? 1140 INTEL_CONTEXT_SCHEDULE_OUT : 1141 INTEL_CONTEXT_SCHEDULE_PREEMPTED); 1142 1143 i915_request_put(rq); 1144 1145 memset(port, 0, sizeof(*port)); 1146 port++; 1147 } 1148 1149 execlists_clear_all_active(execlists); 1150 } 1151 1152 static inline void 1153 invalidate_csb_entries(const u32 *first, const u32 *last) 1154 { 1155 clflush((void *)first); 1156 clflush((void *)last); 1157 } 1158 1159 static inline bool 1160 reset_in_progress(const struct intel_engine_execlists *execlists) 1161 { 1162 return unlikely(!__tasklet_is_enabled(&execlists->tasklet)); 1163 } 1164 1165 static void process_csb(struct intel_engine_cs *engine) 1166 { 1167 struct intel_engine_execlists * const execlists = &engine->execlists; 1168 struct execlist_port *port = execlists->port; 1169 const u32 * const buf = execlists->csb_status; 1170 const u8 num_entries = execlists->csb_size; 1171 u8 head, tail; 1172 1173 lockdep_assert_held(&engine->timeline.lock); 1174 1175 /* 1176 * Note that csb_write, csb_status may be either in HWSP or mmio. 1177 * When reading from the csb_write mmio register, we have to be 1178 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is 1179 * the low 4bits. As it happens we know the next 4bits are always 1180 * zero and so we can simply masked off the low u8 of the register 1181 * and treat it identically to reading from the HWSP (without having 1182 * to use explicit shifting and masking, and probably bifurcating 1183 * the code to handle the legacy mmio read). 1184 */ 1185 head = execlists->csb_head; 1186 tail = READ_ONCE(*execlists->csb_write); 1187 GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail); 1188 if (unlikely(head == tail)) 1189 return; 1190 1191 /* 1192 * Hopefully paired with a wmb() in HW! 1193 * 1194 * We must complete the read of the write pointer before any reads 1195 * from the CSB, so that we do not see stale values. Without an rmb 1196 * (lfence) the HW may speculatively perform the CSB[] reads *before* 1197 * we perform the READ_ONCE(*csb_write). 1198 */ 1199 rmb(); 1200 1201 do { 1202 struct i915_request *rq; 1203 unsigned int status; 1204 unsigned int count; 1205 1206 if (++head == num_entries) 1207 head = 0; 1208 1209 /* 1210 * We are flying near dragons again. 1211 * 1212 * We hold a reference to the request in execlist_port[] 1213 * but no more than that. We are operating in softirq 1214 * context and so cannot hold any mutex or sleep. That 1215 * prevents us stopping the requests we are processing 1216 * in port[] from being retired simultaneously (the 1217 * breadcrumb will be complete before we see the 1218 * context-switch). As we only hold the reference to the 1219 * request, any pointer chasing underneath the request 1220 * is subject to a potential use-after-free. Thus we 1221 * store all of the bookkeeping within port[] as 1222 * required, and avoid using unguarded pointers beneath 1223 * request itself. The same applies to the atomic 1224 * status notifier. 1225 */ 1226 1227 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n", 1228 engine->name, head, 1229 buf[2 * head + 0], buf[2 * head + 1], 1230 execlists->active); 1231 1232 status = buf[2 * head]; 1233 if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE | 1234 GEN8_CTX_STATUS_PREEMPTED)) 1235 execlists_set_active(execlists, 1236 EXECLISTS_ACTIVE_HWACK); 1237 if (status & GEN8_CTX_STATUS_ACTIVE_IDLE) 1238 execlists_clear_active(execlists, 1239 EXECLISTS_ACTIVE_HWACK); 1240 1241 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) 1242 continue; 1243 1244 /* We should never get a COMPLETED | IDLE_ACTIVE! */ 1245 GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE); 1246 1247 if (status & GEN8_CTX_STATUS_COMPLETE && 1248 buf[2*head + 1] == execlists->preempt_complete_status) { 1249 GEM_TRACE("%s preempt-idle\n", engine->name); 1250 complete_preempt_context(execlists); 1251 continue; 1252 } 1253 1254 if (status & GEN8_CTX_STATUS_PREEMPTED && 1255 execlists_is_active(execlists, 1256 EXECLISTS_ACTIVE_PREEMPT)) 1257 continue; 1258 1259 GEM_BUG_ON(!execlists_is_active(execlists, 1260 EXECLISTS_ACTIVE_USER)); 1261 1262 rq = port_unpack(port, &count); 1263 GEM_TRACE("%s out[0]: ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n", 1264 engine->name, 1265 port->context_id, count, 1266 rq ? rq->fence.context : 0, 1267 rq ? rq->fence.seqno : 0, 1268 rq ? hwsp_seqno(rq) : 0, 1269 rq ? rq_prio(rq) : 0); 1270 1271 /* Check the context/desc id for this event matches */ 1272 GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id); 1273 1274 GEM_BUG_ON(count == 0); 1275 if (--count == 0) { 1276 /* 1277 * On the final event corresponding to the 1278 * submission of this context, we expect either 1279 * an element-switch event or a completion 1280 * event (and on completion, the active-idle 1281 * marker). No more preemptions, lite-restore 1282 * or otherwise. 1283 */ 1284 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); 1285 GEM_BUG_ON(port_isset(&port[1]) && 1286 !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH)); 1287 GEM_BUG_ON(!port_isset(&port[1]) && 1288 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); 1289 1290 /* 1291 * We rely on the hardware being strongly 1292 * ordered, that the breadcrumb write is 1293 * coherent (visible from the CPU) before the 1294 * user interrupt and CSB is processed. 1295 */ 1296 GEM_BUG_ON(!i915_request_completed(rq)); 1297 1298 execlists_context_schedule_out(rq, 1299 INTEL_CONTEXT_SCHEDULE_OUT); 1300 i915_request_put(rq); 1301 1302 GEM_TRACE("%s completed ctx=%d\n", 1303 engine->name, port->context_id); 1304 1305 port = execlists_port_complete(execlists, port); 1306 if (port_isset(port)) 1307 execlists_user_begin(execlists, port); 1308 else 1309 execlists_user_end(execlists); 1310 } else { 1311 port_set(port, port_pack(rq, count)); 1312 } 1313 } while (head != tail); 1314 1315 execlists->csb_head = head; 1316 1317 /* 1318 * Gen11 has proven to fail wrt global observation point between 1319 * entry and tail update, failing on the ordering and thus 1320 * we see an old entry in the context status buffer. 1321 * 1322 * Forcibly evict out entries for the next gpu csb update, 1323 * to increase the odds that we get a fresh entries with non 1324 * working hardware. The cost for doing so comes out mostly with 1325 * the wash as hardware, working or not, will need to do the 1326 * invalidation before. 1327 */ 1328 invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); 1329 } 1330 1331 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) 1332 { 1333 lockdep_assert_held(&engine->timeline.lock); 1334 1335 process_csb(engine); 1336 if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT)) 1337 execlists_dequeue(engine); 1338 } 1339 1340 /* 1341 * Check the unread Context Status Buffers and manage the submission of new 1342 * contexts to the ELSP accordingly. 1343 */ 1344 static void execlists_submission_tasklet(unsigned long data) 1345 { 1346 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; 1347 unsigned long flags; 1348 1349 GEM_TRACE("%s awake?=%d, active=%x\n", 1350 engine->name, 1351 !!intel_wakeref_active(&engine->wakeref), 1352 engine->execlists.active); 1353 1354 spin_lock_irqsave(&engine->timeline.lock, flags); 1355 __execlists_submission_tasklet(engine); 1356 spin_unlock_irqrestore(&engine->timeline.lock, flags); 1357 } 1358 1359 static void queue_request(struct intel_engine_cs *engine, 1360 struct i915_sched_node *node, 1361 int prio) 1362 { 1363 list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio)); 1364 } 1365 1366 static void __submit_queue_imm(struct intel_engine_cs *engine) 1367 { 1368 struct intel_engine_execlists * const execlists = &engine->execlists; 1369 1370 if (reset_in_progress(execlists)) 1371 return; /* defer until we restart the engine following reset */ 1372 1373 if (execlists->tasklet.func == execlists_submission_tasklet) 1374 __execlists_submission_tasklet(engine); 1375 else 1376 tasklet_hi_schedule(&execlists->tasklet); 1377 } 1378 1379 static void submit_queue(struct intel_engine_cs *engine, int prio) 1380 { 1381 if (prio > engine->execlists.queue_priority_hint) { 1382 engine->execlists.queue_priority_hint = prio; 1383 __submit_queue_imm(engine); 1384 } 1385 } 1386 1387 static void execlists_submit_request(struct i915_request *request) 1388 { 1389 struct intel_engine_cs *engine = request->engine; 1390 unsigned long flags; 1391 1392 /* Will be called from irq-context when using foreign fences. */ 1393 spin_lock_irqsave(&engine->timeline.lock, flags); 1394 1395 queue_request(engine, &request->sched, rq_prio(request)); 1396 1397 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); 1398 GEM_BUG_ON(list_empty(&request->sched.link)); 1399 1400 submit_queue(engine, rq_prio(request)); 1401 1402 spin_unlock_irqrestore(&engine->timeline.lock, flags); 1403 } 1404 1405 static void __execlists_context_fini(struct intel_context *ce) 1406 { 1407 intel_ring_put(ce->ring); 1408 1409 GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj)); 1410 i915_gem_object_put(ce->state->obj); 1411 } 1412 1413 static void execlists_context_destroy(struct kref *kref) 1414 { 1415 struct intel_context *ce = container_of(kref, typeof(*ce), ref); 1416 1417 GEM_BUG_ON(intel_context_is_pinned(ce)); 1418 1419 if (ce->state) 1420 __execlists_context_fini(ce); 1421 1422 intel_context_free(ce); 1423 } 1424 1425 static int __context_pin(struct i915_vma *vma) 1426 { 1427 unsigned int flags; 1428 int err; 1429 1430 flags = PIN_GLOBAL | PIN_HIGH; 1431 flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); 1432 1433 err = i915_vma_pin(vma, 0, 0, flags); 1434 if (err) 1435 return err; 1436 1437 vma->obj->pin_global++; 1438 vma->obj->mm.dirty = true; 1439 1440 return 0; 1441 } 1442 1443 static void __context_unpin(struct i915_vma *vma) 1444 { 1445 vma->obj->pin_global--; 1446 __i915_vma_unpin(vma); 1447 } 1448 1449 static void execlists_context_unpin(struct intel_context *ce) 1450 { 1451 struct intel_engine_cs *engine; 1452 1453 /* 1454 * The tasklet may still be using a pointer to our state, via an 1455 * old request. However, since we know we only unpin the context 1456 * on retirement of the following request, we know that the last 1457 * request referencing us will have had a completion CS interrupt. 1458 * If we see that it is still active, it means that the tasklet hasn't 1459 * had the chance to run yet; let it run before we teardown the 1460 * reference it may use. 1461 */ 1462 engine = READ_ONCE(ce->inflight); 1463 if (unlikely(engine)) { 1464 unsigned long flags; 1465 1466 spin_lock_irqsave(&engine->timeline.lock, flags); 1467 process_csb(engine); 1468 spin_unlock_irqrestore(&engine->timeline.lock, flags); 1469 1470 GEM_BUG_ON(READ_ONCE(ce->inflight)); 1471 } 1472 1473 i915_gem_context_unpin_hw_id(ce->gem_context); 1474 1475 intel_ring_unpin(ce->ring); 1476 1477 i915_gem_object_unpin_map(ce->state->obj); 1478 __context_unpin(ce->state); 1479 } 1480 1481 static void 1482 __execlists_update_reg_state(struct intel_context *ce, 1483 struct intel_engine_cs *engine) 1484 { 1485 struct intel_ring *ring = ce->ring; 1486 u32 *regs = ce->lrc_reg_state; 1487 1488 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); 1489 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); 1490 1491 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma); 1492 regs[CTX_RING_HEAD + 1] = ring->head; 1493 regs[CTX_RING_TAIL + 1] = ring->tail; 1494 1495 /* RPCS */ 1496 if (engine->class == RENDER_CLASS) 1497 regs[CTX_R_PWR_CLK_STATE + 1] = 1498 intel_sseu_make_rpcs(engine->i915, &ce->sseu); 1499 } 1500 1501 static int 1502 __execlists_context_pin(struct intel_context *ce, 1503 struct intel_engine_cs *engine) 1504 { 1505 void *vaddr; 1506 int ret; 1507 1508 GEM_BUG_ON(!ce->gem_context->ppgtt); 1509 1510 ret = execlists_context_deferred_alloc(ce, engine); 1511 if (ret) 1512 goto err; 1513 GEM_BUG_ON(!ce->state); 1514 1515 ret = __context_pin(ce->state); 1516 if (ret) 1517 goto err; 1518 1519 vaddr = i915_gem_object_pin_map(ce->state->obj, 1520 i915_coherent_map_type(engine->i915) | 1521 I915_MAP_OVERRIDE); 1522 if (IS_ERR(vaddr)) { 1523 ret = PTR_ERR(vaddr); 1524 goto unpin_vma; 1525 } 1526 1527 ret = intel_ring_pin(ce->ring); 1528 if (ret) 1529 goto unpin_map; 1530 1531 ret = i915_gem_context_pin_hw_id(ce->gem_context); 1532 if (ret) 1533 goto unpin_ring; 1534 1535 ce->lrc_desc = lrc_descriptor(ce, engine); 1536 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; 1537 __execlists_update_reg_state(ce, engine); 1538 1539 return 0; 1540 1541 unpin_ring: 1542 intel_ring_unpin(ce->ring); 1543 unpin_map: 1544 i915_gem_object_unpin_map(ce->state->obj); 1545 unpin_vma: 1546 __context_unpin(ce->state); 1547 err: 1548 return ret; 1549 } 1550 1551 static int execlists_context_pin(struct intel_context *ce) 1552 { 1553 return __execlists_context_pin(ce, ce->engine); 1554 } 1555 1556 static void execlists_context_reset(struct intel_context *ce) 1557 { 1558 /* 1559 * Because we emit WA_TAIL_DWORDS there may be a disparity 1560 * between our bookkeeping in ce->ring->head and ce->ring->tail and 1561 * that stored in context. As we only write new commands from 1562 * ce->ring->tail onwards, everything before that is junk. If the GPU 1563 * starts reading from its RING_HEAD from the context, it may try to 1564 * execute that junk and die. 1565 * 1566 * The contexts that are stilled pinned on resume belong to the 1567 * kernel, and are local to each engine. All other contexts will 1568 * have their head/tail sanitized upon pinning before use, so they 1569 * will never see garbage, 1570 * 1571 * So to avoid that we reset the context images upon resume. For 1572 * simplicity, we just zero everything out. 1573 */ 1574 intel_ring_reset(ce->ring, 0); 1575 __execlists_update_reg_state(ce, ce->engine); 1576 } 1577 1578 static const struct intel_context_ops execlists_context_ops = { 1579 .pin = execlists_context_pin, 1580 .unpin = execlists_context_unpin, 1581 1582 .enter = intel_context_enter_engine, 1583 .exit = intel_context_exit_engine, 1584 1585 .reset = execlists_context_reset, 1586 .destroy = execlists_context_destroy, 1587 }; 1588 1589 static int gen8_emit_init_breadcrumb(struct i915_request *rq) 1590 { 1591 u32 *cs; 1592 1593 GEM_BUG_ON(!rq->timeline->has_initial_breadcrumb); 1594 1595 cs = intel_ring_begin(rq, 6); 1596 if (IS_ERR(cs)) 1597 return PTR_ERR(cs); 1598 1599 /* 1600 * Check if we have been preempted before we even get started. 1601 * 1602 * After this point i915_request_started() reports true, even if 1603 * we get preempted and so are no longer running. 1604 */ 1605 *cs++ = MI_ARB_CHECK; 1606 *cs++ = MI_NOOP; 1607 1608 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; 1609 *cs++ = rq->timeline->hwsp_offset; 1610 *cs++ = 0; 1611 *cs++ = rq->fence.seqno - 1; 1612 1613 intel_ring_advance(rq, cs); 1614 1615 /* Record the updated position of the request's payload */ 1616 rq->infix = intel_ring_offset(rq, cs); 1617 1618 return 0; 1619 } 1620 1621 static int emit_pdps(struct i915_request *rq) 1622 { 1623 const struct intel_engine_cs * const engine = rq->engine; 1624 struct i915_hw_ppgtt * const ppgtt = rq->gem_context->ppgtt; 1625 int err, i; 1626 u32 *cs; 1627 1628 GEM_BUG_ON(intel_vgpu_active(rq->i915)); 1629 1630 /* 1631 * Beware ye of the dragons, this sequence is magic! 1632 * 1633 * Small changes to this sequence can cause anything from 1634 * GPU hangs to forcewake errors and machine lockups! 1635 */ 1636 1637 /* Flush any residual operations from the context load */ 1638 err = engine->emit_flush(rq, EMIT_FLUSH); 1639 if (err) 1640 return err; 1641 1642 /* Magic required to prevent forcewake errors! */ 1643 err = engine->emit_flush(rq, EMIT_INVALIDATE); 1644 if (err) 1645 return err; 1646 1647 cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2); 1648 if (IS_ERR(cs)) 1649 return PTR_ERR(cs); 1650 1651 /* Ensure the LRI have landed before we invalidate & continue */ 1652 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED; 1653 for (i = GEN8_3LVL_PDPES; i--; ) { 1654 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); 1655 u32 base = engine->mmio_base; 1656 1657 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i)); 1658 *cs++ = upper_32_bits(pd_daddr); 1659 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i)); 1660 *cs++ = lower_32_bits(pd_daddr); 1661 } 1662 *cs++ = MI_NOOP; 1663 1664 intel_ring_advance(rq, cs); 1665 1666 /* Be doubly sure the LRI have landed before proceeding */ 1667 err = engine->emit_flush(rq, EMIT_FLUSH); 1668 if (err) 1669 return err; 1670 1671 /* Re-invalidate the TLB for luck */ 1672 return engine->emit_flush(rq, EMIT_INVALIDATE); 1673 } 1674 1675 static int execlists_request_alloc(struct i915_request *request) 1676 { 1677 int ret; 1678 1679 GEM_BUG_ON(!intel_context_is_pinned(request->hw_context)); 1680 1681 /* 1682 * Flush enough space to reduce the likelihood of waiting after 1683 * we start building the request - in which case we will just 1684 * have to repeat work. 1685 */ 1686 request->reserved_space += EXECLISTS_REQUEST_SIZE; 1687 1688 /* 1689 * Note that after this point, we have committed to using 1690 * this request as it is being used to both track the 1691 * state of engine initialisation and liveness of the 1692 * golden renderstate above. Think twice before you try 1693 * to cancel/unwind this request now. 1694 */ 1695 1696 /* Unconditionally invalidate GPU caches and TLBs. */ 1697 if (i915_vm_is_4lvl(&request->gem_context->ppgtt->vm)) 1698 ret = request->engine->emit_flush(request, EMIT_INVALIDATE); 1699 else 1700 ret = emit_pdps(request); 1701 if (ret) 1702 return ret; 1703 1704 request->reserved_space -= EXECLISTS_REQUEST_SIZE; 1705 return 0; 1706 } 1707 1708 /* 1709 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after 1710 * PIPE_CONTROL instruction. This is required for the flush to happen correctly 1711 * but there is a slight complication as this is applied in WA batch where the 1712 * values are only initialized once so we cannot take register value at the 1713 * beginning and reuse it further; hence we save its value to memory, upload a 1714 * constant value with bit21 set and then we restore it back with the saved value. 1715 * To simplify the WA, a constant value is formed by using the default value 1716 * of this register. This shouldn't be a problem because we are only modifying 1717 * it for a short period and this batch in non-premptible. We can ofcourse 1718 * use additional instructions that read the actual value of the register 1719 * at that time and set our bit of interest but it makes the WA complicated. 1720 * 1721 * This WA is also required for Gen9 so extracting as a function avoids 1722 * code duplication. 1723 */ 1724 static u32 * 1725 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) 1726 { 1727 /* NB no one else is allowed to scribble over scratch + 256! */ 1728 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; 1729 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); 1730 *batch++ = i915_scratch_offset(engine->i915) + 256; 1731 *batch++ = 0; 1732 1733 *batch++ = MI_LOAD_REGISTER_IMM(1); 1734 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); 1735 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; 1736 1737 batch = gen8_emit_pipe_control(batch, 1738 PIPE_CONTROL_CS_STALL | 1739 PIPE_CONTROL_DC_FLUSH_ENABLE, 1740 0); 1741 1742 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; 1743 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); 1744 *batch++ = i915_scratch_offset(engine->i915) + 256; 1745 *batch++ = 0; 1746 1747 return batch; 1748 } 1749 1750 /* 1751 * Typically we only have one indirect_ctx and per_ctx batch buffer which are 1752 * initialized at the beginning and shared across all contexts but this field 1753 * helps us to have multiple batches at different offsets and select them based 1754 * on a criteria. At the moment this batch always start at the beginning of the page 1755 * and at this point we don't have multiple wa_ctx batch buffers. 1756 * 1757 * The number of WA applied are not known at the beginning; we use this field 1758 * to return the no of DWORDS written. 1759 * 1760 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END 1761 * so it adds NOOPs as padding to make it cacheline aligned. 1762 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together 1763 * makes a complete batch buffer. 1764 */ 1765 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) 1766 { 1767 /* WaDisableCtxRestoreArbitration:bdw,chv */ 1768 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 1769 1770 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ 1771 if (IS_BROADWELL(engine->i915)) 1772 batch = gen8_emit_flush_coherentl3_wa(engine, batch); 1773 1774 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ 1775 /* Actual scratch location is at 128 bytes offset */ 1776 batch = gen8_emit_pipe_control(batch, 1777 PIPE_CONTROL_FLUSH_L3 | 1778 PIPE_CONTROL_GLOBAL_GTT_IVB | 1779 PIPE_CONTROL_CS_STALL | 1780 PIPE_CONTROL_QW_WRITE, 1781 i915_scratch_offset(engine->i915) + 1782 2 * CACHELINE_BYTES); 1783 1784 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 1785 1786 /* Pad to end of cacheline */ 1787 while ((unsigned long)batch % CACHELINE_BYTES) 1788 *batch++ = MI_NOOP; 1789 1790 /* 1791 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because 1792 * execution depends on the length specified in terms of cache lines 1793 * in the register CTX_RCS_INDIRECT_CTX 1794 */ 1795 1796 return batch; 1797 } 1798 1799 struct lri { 1800 i915_reg_t reg; 1801 u32 value; 1802 }; 1803 1804 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count) 1805 { 1806 GEM_BUG_ON(!count || count > 63); 1807 1808 *batch++ = MI_LOAD_REGISTER_IMM(count); 1809 do { 1810 *batch++ = i915_mmio_reg_offset(lri->reg); 1811 *batch++ = lri->value; 1812 } while (lri++, --count); 1813 *batch++ = MI_NOOP; 1814 1815 return batch; 1816 } 1817 1818 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) 1819 { 1820 static const struct lri lri[] = { 1821 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ 1822 { 1823 COMMON_SLICE_CHICKEN2, 1824 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE, 1825 0), 1826 }, 1827 1828 /* BSpec: 11391 */ 1829 { 1830 FF_SLICE_CHICKEN, 1831 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX, 1832 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX), 1833 }, 1834 1835 /* BSpec: 11299 */ 1836 { 1837 _3D_CHICKEN3, 1838 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX, 1839 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX), 1840 } 1841 }; 1842 1843 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 1844 1845 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ 1846 batch = gen8_emit_flush_coherentl3_wa(engine, batch); 1847 1848 batch = emit_lri(batch, lri, ARRAY_SIZE(lri)); 1849 1850 /* WaMediaPoolStateCmdInWABB:bxt,glk */ 1851 if (HAS_POOLED_EU(engine->i915)) { 1852 /* 1853 * EU pool configuration is setup along with golden context 1854 * during context initialization. This value depends on 1855 * device type (2x6 or 3x6) and needs to be updated based 1856 * on which subslice is disabled especially for 2x6 1857 * devices, however it is safe to load default 1858 * configuration of 3x6 device instead of masking off 1859 * corresponding bits because HW ignores bits of a disabled 1860 * subslice and drops down to appropriate config. Please 1861 * see render_state_setup() in i915_gem_render_state.c for 1862 * possible configurations, to avoid duplication they are 1863 * not shown here again. 1864 */ 1865 *batch++ = GEN9_MEDIA_POOL_STATE; 1866 *batch++ = GEN9_MEDIA_POOL_ENABLE; 1867 *batch++ = 0x00777000; 1868 *batch++ = 0; 1869 *batch++ = 0; 1870 *batch++ = 0; 1871 } 1872 1873 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 1874 1875 /* Pad to end of cacheline */ 1876 while ((unsigned long)batch % CACHELINE_BYTES) 1877 *batch++ = MI_NOOP; 1878 1879 return batch; 1880 } 1881 1882 static u32 * 1883 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) 1884 { 1885 int i; 1886 1887 /* 1888 * WaPipeControlBefore3DStateSamplePattern: cnl 1889 * 1890 * Ensure the engine is idle prior to programming a 1891 * 3DSTATE_SAMPLE_PATTERN during a context restore. 1892 */ 1893 batch = gen8_emit_pipe_control(batch, 1894 PIPE_CONTROL_CS_STALL, 1895 0); 1896 /* 1897 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for 1898 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in 1899 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is 1900 * confusing. Since gen8_emit_pipe_control() already advances the 1901 * batch by 6 dwords, we advance the other 10 here, completing a 1902 * cacheline. It's not clear if the workaround requires this padding 1903 * before other commands, or if it's just the regular padding we would 1904 * already have for the workaround bb, so leave it here for now. 1905 */ 1906 for (i = 0; i < 10; i++) 1907 *batch++ = MI_NOOP; 1908 1909 /* Pad to end of cacheline */ 1910 while ((unsigned long)batch % CACHELINE_BYTES) 1911 *batch++ = MI_NOOP; 1912 1913 return batch; 1914 } 1915 1916 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE) 1917 1918 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) 1919 { 1920 struct drm_i915_gem_object *obj; 1921 struct i915_vma *vma; 1922 int err; 1923 1924 obj = i915_gem_object_create_shmem(engine->i915, CTX_WA_BB_OBJ_SIZE); 1925 if (IS_ERR(obj)) 1926 return PTR_ERR(obj); 1927 1928 vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL); 1929 if (IS_ERR(vma)) { 1930 err = PTR_ERR(vma); 1931 goto err; 1932 } 1933 1934 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); 1935 if (err) 1936 goto err; 1937 1938 engine->wa_ctx.vma = vma; 1939 return 0; 1940 1941 err: 1942 i915_gem_object_put(obj); 1943 return err; 1944 } 1945 1946 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine) 1947 { 1948 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); 1949 } 1950 1951 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch); 1952 1953 static int intel_init_workaround_bb(struct intel_engine_cs *engine) 1954 { 1955 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; 1956 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx, 1957 &wa_ctx->per_ctx }; 1958 wa_bb_func_t wa_bb_fn[2]; 1959 struct page *page; 1960 void *batch, *batch_ptr; 1961 unsigned int i; 1962 int ret; 1963 1964 if (engine->class != RENDER_CLASS) 1965 return 0; 1966 1967 switch (INTEL_GEN(engine->i915)) { 1968 case 11: 1969 return 0; 1970 case 10: 1971 wa_bb_fn[0] = gen10_init_indirectctx_bb; 1972 wa_bb_fn[1] = NULL; 1973 break; 1974 case 9: 1975 wa_bb_fn[0] = gen9_init_indirectctx_bb; 1976 wa_bb_fn[1] = NULL; 1977 break; 1978 case 8: 1979 wa_bb_fn[0] = gen8_init_indirectctx_bb; 1980 wa_bb_fn[1] = NULL; 1981 break; 1982 default: 1983 MISSING_CASE(INTEL_GEN(engine->i915)); 1984 return 0; 1985 } 1986 1987 ret = lrc_setup_wa_ctx(engine); 1988 if (ret) { 1989 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); 1990 return ret; 1991 } 1992 1993 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); 1994 batch = batch_ptr = kmap_atomic(page); 1995 1996 /* 1997 * Emit the two workaround batch buffers, recording the offset from the 1998 * start of the workaround batch buffer object for each and their 1999 * respective sizes. 2000 */ 2001 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) { 2002 wa_bb[i]->offset = batch_ptr - batch; 2003 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, 2004 CACHELINE_BYTES))) { 2005 ret = -EINVAL; 2006 break; 2007 } 2008 if (wa_bb_fn[i]) 2009 batch_ptr = wa_bb_fn[i](engine, batch_ptr); 2010 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset); 2011 } 2012 2013 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE); 2014 2015 kunmap_atomic(batch); 2016 if (ret) 2017 lrc_destroy_wa_ctx(engine); 2018 2019 return ret; 2020 } 2021 2022 static void enable_execlists(struct intel_engine_cs *engine) 2023 { 2024 intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */ 2025 2026 if (INTEL_GEN(engine->i915) >= 11) 2027 ENGINE_WRITE(engine, 2028 RING_MODE_GEN7, 2029 _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); 2030 else 2031 ENGINE_WRITE(engine, 2032 RING_MODE_GEN7, 2033 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); 2034 2035 ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 2036 2037 ENGINE_WRITE(engine, 2038 RING_HWS_PGA, 2039 i915_ggtt_offset(engine->status_page.vma)); 2040 ENGINE_POSTING_READ(engine, RING_HWS_PGA); 2041 } 2042 2043 static bool unexpected_starting_state(struct intel_engine_cs *engine) 2044 { 2045 bool unexpected = false; 2046 2047 if (ENGINE_READ(engine, RING_MI_MODE) & STOP_RING) { 2048 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n"); 2049 unexpected = true; 2050 } 2051 2052 return unexpected; 2053 } 2054 2055 static int execlists_resume(struct intel_engine_cs *engine) 2056 { 2057 intel_engine_apply_workarounds(engine); 2058 intel_engine_apply_whitelist(engine); 2059 2060 intel_mocs_init_engine(engine); 2061 2062 intel_engine_reset_breadcrumbs(engine); 2063 2064 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) { 2065 struct drm_printer p = drm_debug_printer(__func__); 2066 2067 intel_engine_dump(engine, &p, NULL); 2068 } 2069 2070 enable_execlists(engine); 2071 2072 return 0; 2073 } 2074 2075 static void execlists_reset_prepare(struct intel_engine_cs *engine) 2076 { 2077 struct intel_engine_execlists * const execlists = &engine->execlists; 2078 unsigned long flags; 2079 2080 GEM_TRACE("%s: depth<-%d\n", engine->name, 2081 atomic_read(&execlists->tasklet.count)); 2082 2083 /* 2084 * Prevent request submission to the hardware until we have 2085 * completed the reset in i915_gem_reset_finish(). If a request 2086 * is completed by one engine, it may then queue a request 2087 * to a second via its execlists->tasklet *just* as we are 2088 * calling engine->resume() and also writing the ELSP. 2089 * Turning off the execlists->tasklet until the reset is over 2090 * prevents the race. 2091 */ 2092 __tasklet_disable_sync_once(&execlists->tasklet); 2093 GEM_BUG_ON(!reset_in_progress(execlists)); 2094 2095 intel_engine_stop_cs(engine); 2096 2097 /* And flush any current direct submission. */ 2098 spin_lock_irqsave(&engine->timeline.lock, flags); 2099 spin_unlock_irqrestore(&engine->timeline.lock, flags); 2100 } 2101 2102 static bool lrc_regs_ok(const struct i915_request *rq) 2103 { 2104 const struct intel_ring *ring = rq->ring; 2105 const u32 *regs = rq->hw_context->lrc_reg_state; 2106 2107 /* Quick spot check for the common signs of context corruption */ 2108 2109 if (regs[CTX_RING_BUFFER_CONTROL + 1] != 2110 (RING_CTL_SIZE(ring->size) | RING_VALID)) 2111 return false; 2112 2113 if (regs[CTX_RING_BUFFER_START + 1] != i915_ggtt_offset(ring->vma)) 2114 return false; 2115 2116 return true; 2117 } 2118 2119 static void reset_csb_pointers(struct intel_engine_execlists *execlists) 2120 { 2121 const unsigned int reset_value = execlists->csb_size - 1; 2122 2123 /* 2124 * After a reset, the HW starts writing into CSB entry [0]. We 2125 * therefore have to set our HEAD pointer back one entry so that 2126 * the *first* entry we check is entry 0. To complicate this further, 2127 * as we don't wait for the first interrupt after reset, we have to 2128 * fake the HW write to point back to the last entry so that our 2129 * inline comparison of our cached head position against the last HW 2130 * write works even before the first interrupt. 2131 */ 2132 execlists->csb_head = reset_value; 2133 WRITE_ONCE(*execlists->csb_write, reset_value); 2134 wmb(); /* Make sure this is visible to HW (paranoia?) */ 2135 2136 invalidate_csb_entries(&execlists->csb_status[0], 2137 &execlists->csb_status[reset_value]); 2138 } 2139 2140 static struct i915_request *active_request(struct i915_request *rq) 2141 { 2142 const struct list_head * const list = &rq->engine->timeline.requests; 2143 const struct intel_context * const context = rq->hw_context; 2144 struct i915_request *active = NULL; 2145 2146 list_for_each_entry_from_reverse(rq, list, link) { 2147 if (i915_request_completed(rq)) 2148 break; 2149 2150 if (rq->hw_context != context) 2151 break; 2152 2153 active = rq; 2154 } 2155 2156 return active; 2157 } 2158 2159 static void __execlists_reset(struct intel_engine_cs *engine, bool stalled) 2160 { 2161 struct intel_engine_execlists * const execlists = &engine->execlists; 2162 struct intel_context *ce; 2163 struct i915_request *rq; 2164 u32 *regs; 2165 2166 process_csb(engine); /* drain preemption events */ 2167 2168 /* Following the reset, we need to reload the CSB read/write pointers */ 2169 reset_csb_pointers(&engine->execlists); 2170 2171 /* 2172 * Save the currently executing context, even if we completed 2173 * its request, it was still running at the time of the 2174 * reset and will have been clobbered. 2175 */ 2176 if (!port_isset(execlists->port)) 2177 goto out_clear; 2178 2179 rq = port_request(execlists->port); 2180 ce = rq->hw_context; 2181 2182 /* 2183 * Catch up with any missed context-switch interrupts. 2184 * 2185 * Ideally we would just read the remaining CSB entries now that we 2186 * know the gpu is idle. However, the CSB registers are sometimes^W 2187 * often trashed across a GPU reset! Instead we have to rely on 2188 * guessing the missed context-switch events by looking at what 2189 * requests were completed. 2190 */ 2191 execlists_cancel_port_requests(execlists); 2192 2193 rq = active_request(rq); 2194 if (!rq) 2195 goto out_replay; 2196 2197 /* 2198 * If this request hasn't started yet, e.g. it is waiting on a 2199 * semaphore, we need to avoid skipping the request or else we 2200 * break the signaling chain. However, if the context is corrupt 2201 * the request will not restart and we will be stuck with a wedged 2202 * device. It is quite often the case that if we issue a reset 2203 * while the GPU is loading the context image, that the context 2204 * image becomes corrupt. 2205 * 2206 * Otherwise, if we have not started yet, the request should replay 2207 * perfectly and we do not need to flag the result as being erroneous. 2208 */ 2209 if (!i915_request_started(rq) && lrc_regs_ok(rq)) 2210 goto out_replay; 2211 2212 /* 2213 * If the request was innocent, we leave the request in the ELSP 2214 * and will try to replay it on restarting. The context image may 2215 * have been corrupted by the reset, in which case we may have 2216 * to service a new GPU hang, but more likely we can continue on 2217 * without impact. 2218 * 2219 * If the request was guilty, we presume the context is corrupt 2220 * and have to at least restore the RING register in the context 2221 * image back to the expected values to skip over the guilty request. 2222 */ 2223 i915_reset_request(rq, stalled); 2224 if (!stalled && lrc_regs_ok(rq)) 2225 goto out_replay; 2226 2227 /* 2228 * We want a simple context + ring to execute the breadcrumb update. 2229 * We cannot rely on the context being intact across the GPU hang, 2230 * so clear it and rebuild just what we need for the breadcrumb. 2231 * All pending requests for this context will be zapped, and any 2232 * future request will be after userspace has had the opportunity 2233 * to recreate its own state. 2234 */ 2235 regs = ce->lrc_reg_state; 2236 if (engine->pinned_default_state) { 2237 memcpy(regs, /* skip restoring the vanilla PPHWSP */ 2238 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE, 2239 engine->context_size - PAGE_SIZE); 2240 } 2241 execlists_init_reg_state(regs, ce, engine, ce->ring); 2242 2243 out_replay: 2244 /* Rerun the request; its payload has been neutered (if guilty). */ 2245 ce->ring->head = 2246 rq ? intel_ring_wrap(ce->ring, rq->head) : ce->ring->tail; 2247 intel_ring_update_space(ce->ring); 2248 __execlists_update_reg_state(ce, engine); 2249 2250 /* Push back any incomplete requests for replay after the reset. */ 2251 __unwind_incomplete_requests(engine); 2252 2253 out_clear: 2254 execlists_clear_all_active(execlists); 2255 } 2256 2257 static void execlists_reset(struct intel_engine_cs *engine, bool stalled) 2258 { 2259 unsigned long flags; 2260 2261 GEM_TRACE("%s\n", engine->name); 2262 2263 spin_lock_irqsave(&engine->timeline.lock, flags); 2264 2265 __execlists_reset(engine, stalled); 2266 2267 spin_unlock_irqrestore(&engine->timeline.lock, flags); 2268 } 2269 2270 static void nop_submission_tasklet(unsigned long data) 2271 { 2272 /* The driver is wedged; don't process any more events. */ 2273 } 2274 2275 static void execlists_cancel_requests(struct intel_engine_cs *engine) 2276 { 2277 struct intel_engine_execlists * const execlists = &engine->execlists; 2278 struct i915_request *rq, *rn; 2279 struct rb_node *rb; 2280 unsigned long flags; 2281 2282 GEM_TRACE("%s\n", engine->name); 2283 2284 /* 2285 * Before we call engine->cancel_requests(), we should have exclusive 2286 * access to the submission state. This is arranged for us by the 2287 * caller disabling the interrupt generation, the tasklet and other 2288 * threads that may then access the same state, giving us a free hand 2289 * to reset state. However, we still need to let lockdep be aware that 2290 * we know this state may be accessed in hardirq context, so we 2291 * disable the irq around this manipulation and we want to keep 2292 * the spinlock focused on its duties and not accidentally conflate 2293 * coverage to the submission's irq state. (Similarly, although we 2294 * shouldn't need to disable irq around the manipulation of the 2295 * submission's irq state, we also wish to remind ourselves that 2296 * it is irq state.) 2297 */ 2298 spin_lock_irqsave(&engine->timeline.lock, flags); 2299 2300 __execlists_reset(engine, true); 2301 2302 /* Mark all executing requests as skipped. */ 2303 list_for_each_entry(rq, &engine->timeline.requests, link) { 2304 if (!i915_request_signaled(rq)) 2305 dma_fence_set_error(&rq->fence, -EIO); 2306 2307 i915_request_mark_complete(rq); 2308 } 2309 2310 /* Flush the queued requests to the timeline list (for retiring). */ 2311 while ((rb = rb_first_cached(&execlists->queue))) { 2312 struct i915_priolist *p = to_priolist(rb); 2313 int i; 2314 2315 priolist_for_each_request_consume(rq, rn, p, i) { 2316 list_del_init(&rq->sched.link); 2317 __i915_request_submit(rq); 2318 dma_fence_set_error(&rq->fence, -EIO); 2319 i915_request_mark_complete(rq); 2320 } 2321 2322 rb_erase_cached(&p->node, &execlists->queue); 2323 i915_priolist_free(p); 2324 } 2325 2326 /* Cancel all attached virtual engines */ 2327 while ((rb = rb_first_cached(&execlists->virtual))) { 2328 struct virtual_engine *ve = 2329 rb_entry(rb, typeof(*ve), nodes[engine->id].rb); 2330 2331 rb_erase_cached(rb, &execlists->virtual); 2332 RB_CLEAR_NODE(rb); 2333 2334 spin_lock(&ve->base.timeline.lock); 2335 if (ve->request) { 2336 ve->request->engine = engine; 2337 __i915_request_submit(ve->request); 2338 dma_fence_set_error(&ve->request->fence, -EIO); 2339 i915_request_mark_complete(ve->request); 2340 ve->base.execlists.queue_priority_hint = INT_MIN; 2341 ve->request = NULL; 2342 } 2343 spin_unlock(&ve->base.timeline.lock); 2344 } 2345 2346 /* Remaining _unready_ requests will be nop'ed when submitted */ 2347 2348 execlists->queue_priority_hint = INT_MIN; 2349 execlists->queue = RB_ROOT_CACHED; 2350 GEM_BUG_ON(port_isset(execlists->port)); 2351 2352 GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet)); 2353 execlists->tasklet.func = nop_submission_tasklet; 2354 2355 spin_unlock_irqrestore(&engine->timeline.lock, flags); 2356 } 2357 2358 static void execlists_reset_finish(struct intel_engine_cs *engine) 2359 { 2360 struct intel_engine_execlists * const execlists = &engine->execlists; 2361 2362 /* 2363 * After a GPU reset, we may have requests to replay. Do so now while 2364 * we still have the forcewake to be sure that the GPU is not allowed 2365 * to sleep before we restart and reload a context. 2366 */ 2367 GEM_BUG_ON(!reset_in_progress(execlists)); 2368 if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) 2369 execlists->tasklet.func(execlists->tasklet.data); 2370 2371 if (__tasklet_enable(&execlists->tasklet)) 2372 /* And kick in case we missed a new request submission. */ 2373 tasklet_hi_schedule(&execlists->tasklet); 2374 GEM_TRACE("%s: depth->%d\n", engine->name, 2375 atomic_read(&execlists->tasklet.count)); 2376 } 2377 2378 static int gen8_emit_bb_start(struct i915_request *rq, 2379 u64 offset, u32 len, 2380 const unsigned int flags) 2381 { 2382 u32 *cs; 2383 2384 cs = intel_ring_begin(rq, 4); 2385 if (IS_ERR(cs)) 2386 return PTR_ERR(cs); 2387 2388 /* 2389 * WaDisableCtxRestoreArbitration:bdw,chv 2390 * 2391 * We don't need to perform MI_ARB_ENABLE as often as we do (in 2392 * particular all the gen that do not need the w/a at all!), if we 2393 * took care to make sure that on every switch into this context 2394 * (both ordinary and for preemption) that arbitrartion was enabled 2395 * we would be fine. However, for gen8 there is another w/a that 2396 * requires us to not preempt inside GPGPU execution, so we keep 2397 * arbitration disabled for gen8 batches. Arbitration will be 2398 * re-enabled before we close the request 2399 * (engine->emit_fini_breadcrumb). 2400 */ 2401 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 2402 2403 /* FIXME(BDW+): Address space and security selectors. */ 2404 *cs++ = MI_BATCH_BUFFER_START_GEN8 | 2405 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); 2406 *cs++ = lower_32_bits(offset); 2407 *cs++ = upper_32_bits(offset); 2408 2409 intel_ring_advance(rq, cs); 2410 2411 return 0; 2412 } 2413 2414 static int gen9_emit_bb_start(struct i915_request *rq, 2415 u64 offset, u32 len, 2416 const unsigned int flags) 2417 { 2418 u32 *cs; 2419 2420 cs = intel_ring_begin(rq, 6); 2421 if (IS_ERR(cs)) 2422 return PTR_ERR(cs); 2423 2424 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 2425 2426 *cs++ = MI_BATCH_BUFFER_START_GEN8 | 2427 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); 2428 *cs++ = lower_32_bits(offset); 2429 *cs++ = upper_32_bits(offset); 2430 2431 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 2432 *cs++ = MI_NOOP; 2433 2434 intel_ring_advance(rq, cs); 2435 2436 return 0; 2437 } 2438 2439 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) 2440 { 2441 ENGINE_WRITE(engine, RING_IMR, 2442 ~(engine->irq_enable_mask | engine->irq_keep_mask)); 2443 ENGINE_POSTING_READ(engine, RING_IMR); 2444 } 2445 2446 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) 2447 { 2448 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); 2449 } 2450 2451 static int gen8_emit_flush(struct i915_request *request, u32 mode) 2452 { 2453 u32 cmd, *cs; 2454 2455 cs = intel_ring_begin(request, 4); 2456 if (IS_ERR(cs)) 2457 return PTR_ERR(cs); 2458 2459 cmd = MI_FLUSH_DW + 1; 2460 2461 /* We always require a command barrier so that subsequent 2462 * commands, such as breadcrumb interrupts, are strictly ordered 2463 * wrt the contents of the write cache being flushed to memory 2464 * (and thus being coherent from the CPU). 2465 */ 2466 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 2467 2468 if (mode & EMIT_INVALIDATE) { 2469 cmd |= MI_INVALIDATE_TLB; 2470 if (request->engine->class == VIDEO_DECODE_CLASS) 2471 cmd |= MI_INVALIDATE_BSD; 2472 } 2473 2474 *cs++ = cmd; 2475 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; 2476 *cs++ = 0; /* upper addr */ 2477 *cs++ = 0; /* value */ 2478 intel_ring_advance(request, cs); 2479 2480 return 0; 2481 } 2482 2483 static int gen8_emit_flush_render(struct i915_request *request, 2484 u32 mode) 2485 { 2486 struct intel_engine_cs *engine = request->engine; 2487 u32 scratch_addr = 2488 i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES; 2489 bool vf_flush_wa = false, dc_flush_wa = false; 2490 u32 *cs, flags = 0; 2491 int len; 2492 2493 flags |= PIPE_CONTROL_CS_STALL; 2494 2495 if (mode & EMIT_FLUSH) { 2496 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 2497 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 2498 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; 2499 flags |= PIPE_CONTROL_FLUSH_ENABLE; 2500 } 2501 2502 if (mode & EMIT_INVALIDATE) { 2503 flags |= PIPE_CONTROL_TLB_INVALIDATE; 2504 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 2505 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 2506 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 2507 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 2508 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 2509 flags |= PIPE_CONTROL_QW_WRITE; 2510 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; 2511 2512 /* 2513 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL 2514 * pipe control. 2515 */ 2516 if (IS_GEN(request->i915, 9)) 2517 vf_flush_wa = true; 2518 2519 /* WaForGAMHang:kbl */ 2520 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) 2521 dc_flush_wa = true; 2522 } 2523 2524 len = 6; 2525 2526 if (vf_flush_wa) 2527 len += 6; 2528 2529 if (dc_flush_wa) 2530 len += 12; 2531 2532 cs = intel_ring_begin(request, len); 2533 if (IS_ERR(cs)) 2534 return PTR_ERR(cs); 2535 2536 if (vf_flush_wa) 2537 cs = gen8_emit_pipe_control(cs, 0, 0); 2538 2539 if (dc_flush_wa) 2540 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, 2541 0); 2542 2543 cs = gen8_emit_pipe_control(cs, flags, scratch_addr); 2544 2545 if (dc_flush_wa) 2546 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); 2547 2548 intel_ring_advance(request, cs); 2549 2550 return 0; 2551 } 2552 2553 /* 2554 * Reserve space for 2 NOOPs at the end of each request to be 2555 * used as a workaround for not being allowed to do lite 2556 * restore with HEAD==TAIL (WaIdleLiteRestore). 2557 */ 2558 static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs) 2559 { 2560 /* Ensure there's always at least one preemption point per-request. */ 2561 *cs++ = MI_ARB_CHECK; 2562 *cs++ = MI_NOOP; 2563 request->wa_tail = intel_ring_offset(request, cs); 2564 2565 return cs; 2566 } 2567 2568 static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs) 2569 { 2570 cs = gen8_emit_ggtt_write(cs, 2571 request->fence.seqno, 2572 request->timeline->hwsp_offset, 2573 0); 2574 2575 *cs++ = MI_USER_INTERRUPT; 2576 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 2577 2578 request->tail = intel_ring_offset(request, cs); 2579 assert_ring_tail_valid(request->ring, request->tail); 2580 2581 return gen8_emit_wa_tail(request, cs); 2582 } 2583 2584 static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) 2585 { 2586 /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */ 2587 cs = gen8_emit_ggtt_write_rcs(cs, 2588 request->fence.seqno, 2589 request->timeline->hwsp_offset, 2590 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | 2591 PIPE_CONTROL_DEPTH_CACHE_FLUSH | 2592 PIPE_CONTROL_DC_FLUSH_ENABLE); 2593 cs = gen8_emit_pipe_control(cs, 2594 PIPE_CONTROL_FLUSH_ENABLE | 2595 PIPE_CONTROL_CS_STALL, 2596 0); 2597 2598 *cs++ = MI_USER_INTERRUPT; 2599 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 2600 2601 request->tail = intel_ring_offset(request, cs); 2602 assert_ring_tail_valid(request->ring, request->tail); 2603 2604 return gen8_emit_wa_tail(request, cs); 2605 } 2606 2607 static int gen8_init_rcs_context(struct i915_request *rq) 2608 { 2609 int ret; 2610 2611 ret = intel_engine_emit_ctx_wa(rq); 2612 if (ret) 2613 return ret; 2614 2615 ret = intel_rcs_context_init_mocs(rq); 2616 /* 2617 * Failing to program the MOCS is non-fatal.The system will not 2618 * run at peak performance. So generate an error and carry on. 2619 */ 2620 if (ret) 2621 DRM_ERROR("MOCS failed to program: expect performance issues.\n"); 2622 2623 return i915_gem_render_state_emit(rq); 2624 } 2625 2626 static void execlists_park(struct intel_engine_cs *engine) 2627 { 2628 intel_engine_park(engine); 2629 } 2630 2631 void intel_execlists_set_default_submission(struct intel_engine_cs *engine) 2632 { 2633 engine->submit_request = execlists_submit_request; 2634 engine->cancel_requests = execlists_cancel_requests; 2635 engine->schedule = i915_schedule; 2636 engine->execlists.tasklet.func = execlists_submission_tasklet; 2637 2638 engine->reset.prepare = execlists_reset_prepare; 2639 engine->reset.reset = execlists_reset; 2640 engine->reset.finish = execlists_reset_finish; 2641 2642 engine->park = execlists_park; 2643 engine->unpark = NULL; 2644 2645 engine->flags |= I915_ENGINE_SUPPORTS_STATS; 2646 if (!intel_vgpu_active(engine->i915)) 2647 engine->flags |= I915_ENGINE_HAS_SEMAPHORES; 2648 if (engine->preempt_context && 2649 HAS_LOGICAL_RING_PREEMPTION(engine->i915)) 2650 engine->flags |= I915_ENGINE_HAS_PREEMPTION; 2651 } 2652 2653 static void execlists_destroy(struct intel_engine_cs *engine) 2654 { 2655 intel_engine_cleanup_common(engine); 2656 lrc_destroy_wa_ctx(engine); 2657 kfree(engine); 2658 } 2659 2660 static void 2661 logical_ring_default_vfuncs(struct intel_engine_cs *engine) 2662 { 2663 /* Default vfuncs which can be overriden by each engine. */ 2664 2665 engine->destroy = execlists_destroy; 2666 engine->resume = execlists_resume; 2667 2668 engine->reset.prepare = execlists_reset_prepare; 2669 engine->reset.reset = execlists_reset; 2670 engine->reset.finish = execlists_reset_finish; 2671 2672 engine->cops = &execlists_context_ops; 2673 engine->request_alloc = execlists_request_alloc; 2674 2675 engine->emit_flush = gen8_emit_flush; 2676 engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb; 2677 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb; 2678 2679 engine->set_default_submission = intel_execlists_set_default_submission; 2680 2681 if (INTEL_GEN(engine->i915) < 11) { 2682 engine->irq_enable = gen8_logical_ring_enable_irq; 2683 engine->irq_disable = gen8_logical_ring_disable_irq; 2684 } else { 2685 /* 2686 * TODO: On Gen11 interrupt masks need to be clear 2687 * to allow C6 entry. Keep interrupts enabled at 2688 * and take the hit of generating extra interrupts 2689 * until a more refined solution exists. 2690 */ 2691 } 2692 if (IS_GEN(engine->i915, 8)) 2693 engine->emit_bb_start = gen8_emit_bb_start; 2694 else 2695 engine->emit_bb_start = gen9_emit_bb_start; 2696 } 2697 2698 static inline void 2699 logical_ring_default_irqs(struct intel_engine_cs *engine) 2700 { 2701 unsigned int shift = 0; 2702 2703 if (INTEL_GEN(engine->i915) < 11) { 2704 const u8 irq_shifts[] = { 2705 [RCS0] = GEN8_RCS_IRQ_SHIFT, 2706 [BCS0] = GEN8_BCS_IRQ_SHIFT, 2707 [VCS0] = GEN8_VCS0_IRQ_SHIFT, 2708 [VCS1] = GEN8_VCS1_IRQ_SHIFT, 2709 [VECS0] = GEN8_VECS_IRQ_SHIFT, 2710 }; 2711 2712 shift = irq_shifts[engine->id]; 2713 } 2714 2715 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; 2716 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; 2717 } 2718 2719 int intel_execlists_submission_setup(struct intel_engine_cs *engine) 2720 { 2721 /* Intentionally left blank. */ 2722 engine->buffer = NULL; 2723 2724 tasklet_init(&engine->execlists.tasklet, 2725 execlists_submission_tasklet, (unsigned long)engine); 2726 2727 logical_ring_default_vfuncs(engine); 2728 logical_ring_default_irqs(engine); 2729 2730 if (engine->class == RENDER_CLASS) { 2731 engine->init_context = gen8_init_rcs_context; 2732 engine->emit_flush = gen8_emit_flush_render; 2733 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs; 2734 } 2735 2736 return 0; 2737 } 2738 2739 int intel_execlists_submission_init(struct intel_engine_cs *engine) 2740 { 2741 struct drm_i915_private *i915 = engine->i915; 2742 struct intel_engine_execlists * const execlists = &engine->execlists; 2743 u32 base = engine->mmio_base; 2744 int ret; 2745 2746 ret = intel_engine_init_common(engine); 2747 if (ret) 2748 return ret; 2749 2750 intel_engine_init_workarounds(engine); 2751 intel_engine_init_whitelist(engine); 2752 2753 if (intel_init_workaround_bb(engine)) 2754 /* 2755 * We continue even if we fail to initialize WA batch 2756 * because we only expect rare glitches but nothing 2757 * critical to prevent us from using GPU 2758 */ 2759 DRM_ERROR("WA batch buffer initialization failed\n"); 2760 2761 if (HAS_LOGICAL_RING_ELSQ(i915)) { 2762 execlists->submit_reg = i915->uncore.regs + 2763 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base)); 2764 execlists->ctrl_reg = i915->uncore.regs + 2765 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base)); 2766 } else { 2767 execlists->submit_reg = i915->uncore.regs + 2768 i915_mmio_reg_offset(RING_ELSP(base)); 2769 } 2770 2771 execlists->preempt_complete_status = ~0u; 2772 if (engine->preempt_context) 2773 execlists->preempt_complete_status = 2774 upper_32_bits(engine->preempt_context->lrc_desc); 2775 2776 execlists->csb_status = 2777 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; 2778 2779 execlists->csb_write = 2780 &engine->status_page.addr[intel_hws_csb_write_index(i915)]; 2781 2782 if (INTEL_GEN(engine->i915) < 11) 2783 execlists->csb_size = GEN8_CSB_ENTRIES; 2784 else 2785 execlists->csb_size = GEN11_CSB_ENTRIES; 2786 2787 reset_csb_pointers(execlists); 2788 2789 return 0; 2790 } 2791 2792 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) 2793 { 2794 u32 indirect_ctx_offset; 2795 2796 switch (INTEL_GEN(engine->i915)) { 2797 default: 2798 MISSING_CASE(INTEL_GEN(engine->i915)); 2799 /* fall through */ 2800 case 11: 2801 indirect_ctx_offset = 2802 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2803 break; 2804 case 10: 2805 indirect_ctx_offset = 2806 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2807 break; 2808 case 9: 2809 indirect_ctx_offset = 2810 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2811 break; 2812 case 8: 2813 indirect_ctx_offset = 2814 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2815 break; 2816 } 2817 2818 return indirect_ctx_offset; 2819 } 2820 2821 static void execlists_init_reg_state(u32 *regs, 2822 struct intel_context *ce, 2823 struct intel_engine_cs *engine, 2824 struct intel_ring *ring) 2825 { 2826 struct i915_hw_ppgtt *ppgtt = ce->gem_context->ppgtt; 2827 bool rcs = engine->class == RENDER_CLASS; 2828 u32 base = engine->mmio_base; 2829 2830 /* 2831 * A context is actually a big batch buffer with several 2832 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The 2833 * values we are setting here are only for the first context restore: 2834 * on a subsequent save, the GPU will recreate this batchbuffer with new 2835 * values (including all the missing MI_LOAD_REGISTER_IMM commands that 2836 * we are not initializing here). 2837 * 2838 * Must keep consistent with virtual_update_register_offsets(). 2839 */ 2840 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | 2841 MI_LRI_FORCE_POSTED; 2842 2843 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base), 2844 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) | 2845 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH)); 2846 if (INTEL_GEN(engine->i915) < 11) { 2847 regs[CTX_CONTEXT_CONTROL + 1] |= 2848 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT | 2849 CTX_CTRL_RS_CTX_ENABLE); 2850 } 2851 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0); 2852 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0); 2853 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); 2854 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), 2855 RING_CTL_SIZE(ring->size) | RING_VALID); 2856 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0); 2857 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0); 2858 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT); 2859 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0); 2860 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0); 2861 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0); 2862 if (rcs) { 2863 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; 2864 2865 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0); 2866 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET, 2867 RING_INDIRECT_CTX_OFFSET(base), 0); 2868 if (wa_ctx->indirect_ctx.size) { 2869 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); 2870 2871 regs[CTX_RCS_INDIRECT_CTX + 1] = 2872 (ggtt_offset + wa_ctx->indirect_ctx.offset) | 2873 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); 2874 2875 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = 2876 intel_lr_indirect_ctx_offset(engine) << 6; 2877 } 2878 2879 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0); 2880 if (wa_ctx->per_ctx.size) { 2881 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); 2882 2883 regs[CTX_BB_PER_CTX_PTR + 1] = 2884 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; 2885 } 2886 } 2887 2888 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; 2889 2890 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); 2891 /* PDP values well be assigned later if needed */ 2892 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0); 2893 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0); 2894 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(base, 2), 0); 2895 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(base, 2), 0); 2896 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(base, 1), 0); 2897 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(base, 1), 0); 2898 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(base, 0), 0); 2899 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(base, 0), 0); 2900 2901 if (i915_vm_is_4lvl(&ppgtt->vm)) { 2902 /* 64b PPGTT (48bit canonical) 2903 * PDP0_DESCRIPTOR contains the base address to PML4 and 2904 * other PDP Descriptors are ignored. 2905 */ 2906 ASSIGN_CTX_PML4(ppgtt, regs); 2907 } else { 2908 ASSIGN_CTX_PDP(ppgtt, regs, 3); 2909 ASSIGN_CTX_PDP(ppgtt, regs, 2); 2910 ASSIGN_CTX_PDP(ppgtt, regs, 1); 2911 ASSIGN_CTX_PDP(ppgtt, regs, 0); 2912 } 2913 2914 if (rcs) { 2915 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); 2916 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0); 2917 2918 i915_oa_init_reg_state(engine, ce, regs); 2919 } 2920 2921 regs[CTX_END] = MI_BATCH_BUFFER_END; 2922 if (INTEL_GEN(engine->i915) >= 10) 2923 regs[CTX_END] |= BIT(0); 2924 } 2925 2926 static int 2927 populate_lr_context(struct intel_context *ce, 2928 struct drm_i915_gem_object *ctx_obj, 2929 struct intel_engine_cs *engine, 2930 struct intel_ring *ring) 2931 { 2932 void *vaddr; 2933 u32 *regs; 2934 int ret; 2935 2936 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); 2937 if (IS_ERR(vaddr)) { 2938 ret = PTR_ERR(vaddr); 2939 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); 2940 return ret; 2941 } 2942 2943 if (engine->default_state) { 2944 /* 2945 * We only want to copy over the template context state; 2946 * skipping over the headers reserved for GuC communication, 2947 * leaving those as zero. 2948 */ 2949 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE; 2950 void *defaults; 2951 2952 defaults = i915_gem_object_pin_map(engine->default_state, 2953 I915_MAP_WB); 2954 if (IS_ERR(defaults)) { 2955 ret = PTR_ERR(defaults); 2956 goto err_unpin_ctx; 2957 } 2958 2959 memcpy(vaddr + start, defaults + start, engine->context_size); 2960 i915_gem_object_unpin_map(engine->default_state); 2961 } 2962 2963 /* The second page of the context object contains some fields which must 2964 * be set up prior to the first execution. */ 2965 regs = vaddr + LRC_STATE_PN * PAGE_SIZE; 2966 execlists_init_reg_state(regs, ce, engine, ring); 2967 if (!engine->default_state) 2968 regs[CTX_CONTEXT_CONTROL + 1] |= 2969 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 2970 if (ce->gem_context == engine->i915->preempt_context && 2971 INTEL_GEN(engine->i915) < 11) 2972 regs[CTX_CONTEXT_CONTROL + 1] |= 2973 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | 2974 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT); 2975 2976 ret = 0; 2977 err_unpin_ctx: 2978 __i915_gem_object_flush_map(ctx_obj, 2979 LRC_HEADER_PAGES * PAGE_SIZE, 2980 engine->context_size); 2981 i915_gem_object_unpin_map(ctx_obj); 2982 return ret; 2983 } 2984 2985 static struct i915_timeline *get_timeline(struct i915_gem_context *ctx) 2986 { 2987 if (ctx->timeline) 2988 return i915_timeline_get(ctx->timeline); 2989 else 2990 return i915_timeline_create(ctx->i915, NULL); 2991 } 2992 2993 static int execlists_context_deferred_alloc(struct intel_context *ce, 2994 struct intel_engine_cs *engine) 2995 { 2996 struct drm_i915_gem_object *ctx_obj; 2997 struct i915_vma *vma; 2998 u32 context_size; 2999 struct intel_ring *ring; 3000 struct i915_timeline *timeline; 3001 int ret; 3002 3003 if (ce->state) 3004 return 0; 3005 3006 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); 3007 3008 /* 3009 * Before the actual start of the context image, we insert a few pages 3010 * for our own use and for sharing with the GuC. 3011 */ 3012 context_size += LRC_HEADER_PAGES * PAGE_SIZE; 3013 3014 ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size); 3015 if (IS_ERR(ctx_obj)) 3016 return PTR_ERR(ctx_obj); 3017 3018 vma = i915_vma_instance(ctx_obj, &engine->i915->ggtt.vm, NULL); 3019 if (IS_ERR(vma)) { 3020 ret = PTR_ERR(vma); 3021 goto error_deref_obj; 3022 } 3023 3024 timeline = get_timeline(ce->gem_context); 3025 if (IS_ERR(timeline)) { 3026 ret = PTR_ERR(timeline); 3027 goto error_deref_obj; 3028 } 3029 3030 ring = intel_engine_create_ring(engine, 3031 timeline, 3032 ce->gem_context->ring_size); 3033 i915_timeline_put(timeline); 3034 if (IS_ERR(ring)) { 3035 ret = PTR_ERR(ring); 3036 goto error_deref_obj; 3037 } 3038 3039 ret = populate_lr_context(ce, ctx_obj, engine, ring); 3040 if (ret) { 3041 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); 3042 goto error_ring_free; 3043 } 3044 3045 ce->ring = ring; 3046 ce->state = vma; 3047 3048 return 0; 3049 3050 error_ring_free: 3051 intel_ring_put(ring); 3052 error_deref_obj: 3053 i915_gem_object_put(ctx_obj); 3054 return ret; 3055 } 3056 3057 static void virtual_context_destroy(struct kref *kref) 3058 { 3059 struct virtual_engine *ve = 3060 container_of(kref, typeof(*ve), context.ref); 3061 unsigned int n; 3062 3063 GEM_BUG_ON(ve->request); 3064 GEM_BUG_ON(ve->context.inflight); 3065 3066 for (n = 0; n < ve->num_siblings; n++) { 3067 struct intel_engine_cs *sibling = ve->siblings[n]; 3068 struct rb_node *node = &ve->nodes[sibling->id].rb; 3069 3070 if (RB_EMPTY_NODE(node)) 3071 continue; 3072 3073 spin_lock_irq(&sibling->timeline.lock); 3074 3075 /* Detachment is lazily performed in the execlists tasklet */ 3076 if (!RB_EMPTY_NODE(node)) 3077 rb_erase_cached(node, &sibling->execlists.virtual); 3078 3079 spin_unlock_irq(&sibling->timeline.lock); 3080 } 3081 GEM_BUG_ON(__tasklet_is_scheduled(&ve->base.execlists.tasklet)); 3082 3083 if (ve->context.state) 3084 __execlists_context_fini(&ve->context); 3085 3086 kfree(ve->bonds); 3087 3088 i915_timeline_fini(&ve->base.timeline); 3089 kfree(ve); 3090 } 3091 3092 static void virtual_engine_initial_hint(struct virtual_engine *ve) 3093 { 3094 int swp; 3095 3096 /* 3097 * Pick a random sibling on starting to help spread the load around. 3098 * 3099 * New contexts are typically created with exactly the same order 3100 * of siblings, and often started in batches. Due to the way we iterate 3101 * the array of sibling when submitting requests, sibling[0] is 3102 * prioritised for dequeuing. If we make sure that sibling[0] is fairly 3103 * randomised across the system, we also help spread the load by the 3104 * first engine we inspect being different each time. 3105 * 3106 * NB This does not force us to execute on this engine, it will just 3107 * typically be the first we inspect for submission. 3108 */ 3109 swp = prandom_u32_max(ve->num_siblings); 3110 if (!swp) 3111 return; 3112 3113 swap(ve->siblings[swp], ve->siblings[0]); 3114 virtual_update_register_offsets(ve->context.lrc_reg_state, 3115 ve->siblings[0]); 3116 } 3117 3118 static int virtual_context_pin(struct intel_context *ce) 3119 { 3120 struct virtual_engine *ve = container_of(ce, typeof(*ve), context); 3121 int err; 3122 3123 /* Note: we must use a real engine class for setting up reg state */ 3124 err = __execlists_context_pin(ce, ve->siblings[0]); 3125 if (err) 3126 return err; 3127 3128 virtual_engine_initial_hint(ve); 3129 return 0; 3130 } 3131 3132 static void virtual_context_enter(struct intel_context *ce) 3133 { 3134 struct virtual_engine *ve = container_of(ce, typeof(*ve), context); 3135 unsigned int n; 3136 3137 for (n = 0; n < ve->num_siblings; n++) 3138 intel_engine_pm_get(ve->siblings[n]); 3139 } 3140 3141 static void virtual_context_exit(struct intel_context *ce) 3142 { 3143 struct virtual_engine *ve = container_of(ce, typeof(*ve), context); 3144 unsigned int n; 3145 3146 ce->saturated = 0; 3147 for (n = 0; n < ve->num_siblings; n++) 3148 intel_engine_pm_put(ve->siblings[n]); 3149 } 3150 3151 static const struct intel_context_ops virtual_context_ops = { 3152 .pin = virtual_context_pin, 3153 .unpin = execlists_context_unpin, 3154 3155 .enter = virtual_context_enter, 3156 .exit = virtual_context_exit, 3157 3158 .destroy = virtual_context_destroy, 3159 }; 3160 3161 static intel_engine_mask_t virtual_submission_mask(struct virtual_engine *ve) 3162 { 3163 struct i915_request *rq; 3164 intel_engine_mask_t mask; 3165 3166 rq = READ_ONCE(ve->request); 3167 if (!rq) 3168 return 0; 3169 3170 /* The rq is ready for submission; rq->execution_mask is now stable. */ 3171 mask = rq->execution_mask; 3172 if (unlikely(!mask)) { 3173 /* Invalid selection, submit to a random engine in error */ 3174 i915_request_skip(rq, -ENODEV); 3175 mask = ve->siblings[0]->mask; 3176 } 3177 3178 GEM_TRACE("%s: rq=%llx:%lld, mask=%x, prio=%d\n", 3179 ve->base.name, 3180 rq->fence.context, rq->fence.seqno, 3181 mask, ve->base.execlists.queue_priority_hint); 3182 3183 return mask; 3184 } 3185 3186 static void virtual_submission_tasklet(unsigned long data) 3187 { 3188 struct virtual_engine * const ve = (struct virtual_engine *)data; 3189 const int prio = ve->base.execlists.queue_priority_hint; 3190 intel_engine_mask_t mask; 3191 unsigned int n; 3192 3193 rcu_read_lock(); 3194 mask = virtual_submission_mask(ve); 3195 rcu_read_unlock(); 3196 if (unlikely(!mask)) 3197 return; 3198 3199 local_irq_disable(); 3200 for (n = 0; READ_ONCE(ve->request) && n < ve->num_siblings; n++) { 3201 struct intel_engine_cs *sibling = ve->siblings[n]; 3202 struct ve_node * const node = &ve->nodes[sibling->id]; 3203 struct rb_node **parent, *rb; 3204 bool first; 3205 3206 if (unlikely(!(mask & sibling->mask))) { 3207 if (!RB_EMPTY_NODE(&node->rb)) { 3208 spin_lock(&sibling->timeline.lock); 3209 rb_erase_cached(&node->rb, 3210 &sibling->execlists.virtual); 3211 RB_CLEAR_NODE(&node->rb); 3212 spin_unlock(&sibling->timeline.lock); 3213 } 3214 continue; 3215 } 3216 3217 spin_lock(&sibling->timeline.lock); 3218 3219 if (!RB_EMPTY_NODE(&node->rb)) { 3220 /* 3221 * Cheat and avoid rebalancing the tree if we can 3222 * reuse this node in situ. 3223 */ 3224 first = rb_first_cached(&sibling->execlists.virtual) == 3225 &node->rb; 3226 if (prio == node->prio || (prio > node->prio && first)) 3227 goto submit_engine; 3228 3229 rb_erase_cached(&node->rb, &sibling->execlists.virtual); 3230 } 3231 3232 rb = NULL; 3233 first = true; 3234 parent = &sibling->execlists.virtual.rb_root.rb_node; 3235 while (*parent) { 3236 struct ve_node *other; 3237 3238 rb = *parent; 3239 other = rb_entry(rb, typeof(*other), rb); 3240 if (prio > other->prio) { 3241 parent = &rb->rb_left; 3242 } else { 3243 parent = &rb->rb_right; 3244 first = false; 3245 } 3246 } 3247 3248 rb_link_node(&node->rb, rb, parent); 3249 rb_insert_color_cached(&node->rb, 3250 &sibling->execlists.virtual, 3251 first); 3252 3253 submit_engine: 3254 GEM_BUG_ON(RB_EMPTY_NODE(&node->rb)); 3255 node->prio = prio; 3256 if (first && prio > sibling->execlists.queue_priority_hint) { 3257 sibling->execlists.queue_priority_hint = prio; 3258 tasklet_hi_schedule(&sibling->execlists.tasklet); 3259 } 3260 3261 spin_unlock(&sibling->timeline.lock); 3262 } 3263 local_irq_enable(); 3264 } 3265 3266 static void virtual_submit_request(struct i915_request *rq) 3267 { 3268 struct virtual_engine *ve = to_virtual_engine(rq->engine); 3269 3270 GEM_TRACE("%s: rq=%llx:%lld\n", 3271 ve->base.name, 3272 rq->fence.context, 3273 rq->fence.seqno); 3274 3275 GEM_BUG_ON(ve->base.submit_request != virtual_submit_request); 3276 3277 GEM_BUG_ON(ve->request); 3278 ve->base.execlists.queue_priority_hint = rq_prio(rq); 3279 WRITE_ONCE(ve->request, rq); 3280 3281 tasklet_schedule(&ve->base.execlists.tasklet); 3282 } 3283 3284 static struct ve_bond * 3285 virtual_find_bond(struct virtual_engine *ve, 3286 const struct intel_engine_cs *master) 3287 { 3288 int i; 3289 3290 for (i = 0; i < ve->num_bonds; i++) { 3291 if (ve->bonds[i].master == master) 3292 return &ve->bonds[i]; 3293 } 3294 3295 return NULL; 3296 } 3297 3298 static void 3299 virtual_bond_execute(struct i915_request *rq, struct dma_fence *signal) 3300 { 3301 struct virtual_engine *ve = to_virtual_engine(rq->engine); 3302 struct ve_bond *bond; 3303 3304 bond = virtual_find_bond(ve, to_request(signal)->engine); 3305 if (bond) { 3306 intel_engine_mask_t old, new, cmp; 3307 3308 cmp = READ_ONCE(rq->execution_mask); 3309 do { 3310 old = cmp; 3311 new = cmp & bond->sibling_mask; 3312 } while ((cmp = cmpxchg(&rq->execution_mask, old, new)) != old); 3313 } 3314 } 3315 3316 struct intel_context * 3317 intel_execlists_create_virtual(struct i915_gem_context *ctx, 3318 struct intel_engine_cs **siblings, 3319 unsigned int count) 3320 { 3321 struct virtual_engine *ve; 3322 unsigned int n; 3323 int err; 3324 3325 if (count == 0) 3326 return ERR_PTR(-EINVAL); 3327 3328 if (count == 1) 3329 return intel_context_create(ctx, siblings[0]); 3330 3331 ve = kzalloc(struct_size(ve, siblings, count), GFP_KERNEL); 3332 if (!ve) 3333 return ERR_PTR(-ENOMEM); 3334 3335 ve->base.i915 = ctx->i915; 3336 ve->base.id = -1; 3337 ve->base.class = OTHER_CLASS; 3338 ve->base.uabi_class = I915_ENGINE_CLASS_INVALID; 3339 ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL; 3340 ve->base.flags = I915_ENGINE_IS_VIRTUAL; 3341 3342 snprintf(ve->base.name, sizeof(ve->base.name), "virtual"); 3343 3344 err = i915_timeline_init(ctx->i915, &ve->base.timeline, NULL); 3345 if (err) 3346 goto err_put; 3347 i915_timeline_set_subclass(&ve->base.timeline, TIMELINE_VIRTUAL); 3348 3349 intel_engine_init_execlists(&ve->base); 3350 3351 ve->base.cops = &virtual_context_ops; 3352 ve->base.request_alloc = execlists_request_alloc; 3353 3354 ve->base.schedule = i915_schedule; 3355 ve->base.submit_request = virtual_submit_request; 3356 ve->base.bond_execute = virtual_bond_execute; 3357 3358 ve->base.execlists.queue_priority_hint = INT_MIN; 3359 tasklet_init(&ve->base.execlists.tasklet, 3360 virtual_submission_tasklet, 3361 (unsigned long)ve); 3362 3363 intel_context_init(&ve->context, ctx, &ve->base); 3364 3365 for (n = 0; n < count; n++) { 3366 struct intel_engine_cs *sibling = siblings[n]; 3367 3368 GEM_BUG_ON(!is_power_of_2(sibling->mask)); 3369 if (sibling->mask & ve->base.mask) { 3370 DRM_DEBUG("duplicate %s entry in load balancer\n", 3371 sibling->name); 3372 err = -EINVAL; 3373 goto err_put; 3374 } 3375 3376 /* 3377 * The virtual engine implementation is tightly coupled to 3378 * the execlists backend -- we push out request directly 3379 * into a tree inside each physical engine. We could support 3380 * layering if we handle cloning of the requests and 3381 * submitting a copy into each backend. 3382 */ 3383 if (sibling->execlists.tasklet.func != 3384 execlists_submission_tasklet) { 3385 err = -ENODEV; 3386 goto err_put; 3387 } 3388 3389 GEM_BUG_ON(RB_EMPTY_NODE(&ve->nodes[sibling->id].rb)); 3390 RB_CLEAR_NODE(&ve->nodes[sibling->id].rb); 3391 3392 ve->siblings[ve->num_siblings++] = sibling; 3393 ve->base.mask |= sibling->mask; 3394 3395 /* 3396 * All physical engines must be compatible for their emission 3397 * functions (as we build the instructions during request 3398 * construction and do not alter them before submission 3399 * on the physical engine). We use the engine class as a guide 3400 * here, although that could be refined. 3401 */ 3402 if (ve->base.class != OTHER_CLASS) { 3403 if (ve->base.class != sibling->class) { 3404 DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n", 3405 sibling->class, ve->base.class); 3406 err = -EINVAL; 3407 goto err_put; 3408 } 3409 continue; 3410 } 3411 3412 ve->base.class = sibling->class; 3413 ve->base.uabi_class = sibling->uabi_class; 3414 snprintf(ve->base.name, sizeof(ve->base.name), 3415 "v%dx%d", ve->base.class, count); 3416 ve->base.context_size = sibling->context_size; 3417 3418 ve->base.emit_bb_start = sibling->emit_bb_start; 3419 ve->base.emit_flush = sibling->emit_flush; 3420 ve->base.emit_init_breadcrumb = sibling->emit_init_breadcrumb; 3421 ve->base.emit_fini_breadcrumb = sibling->emit_fini_breadcrumb; 3422 ve->base.emit_fini_breadcrumb_dw = 3423 sibling->emit_fini_breadcrumb_dw; 3424 } 3425 3426 return &ve->context; 3427 3428 err_put: 3429 intel_context_put(&ve->context); 3430 return ERR_PTR(err); 3431 } 3432 3433 struct intel_context * 3434 intel_execlists_clone_virtual(struct i915_gem_context *ctx, 3435 struct intel_engine_cs *src) 3436 { 3437 struct virtual_engine *se = to_virtual_engine(src); 3438 struct intel_context *dst; 3439 3440 dst = intel_execlists_create_virtual(ctx, 3441 se->siblings, 3442 se->num_siblings); 3443 if (IS_ERR(dst)) 3444 return dst; 3445 3446 if (se->num_bonds) { 3447 struct virtual_engine *de = to_virtual_engine(dst->engine); 3448 3449 de->bonds = kmemdup(se->bonds, 3450 sizeof(*se->bonds) * se->num_bonds, 3451 GFP_KERNEL); 3452 if (!de->bonds) { 3453 intel_context_put(dst); 3454 return ERR_PTR(-ENOMEM); 3455 } 3456 3457 de->num_bonds = se->num_bonds; 3458 } 3459 3460 return dst; 3461 } 3462 3463 int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine, 3464 const struct intel_engine_cs *master, 3465 const struct intel_engine_cs *sibling) 3466 { 3467 struct virtual_engine *ve = to_virtual_engine(engine); 3468 struct ve_bond *bond; 3469 int n; 3470 3471 /* Sanity check the sibling is part of the virtual engine */ 3472 for (n = 0; n < ve->num_siblings; n++) 3473 if (sibling == ve->siblings[n]) 3474 break; 3475 if (n == ve->num_siblings) 3476 return -EINVAL; 3477 3478 bond = virtual_find_bond(ve, master); 3479 if (bond) { 3480 bond->sibling_mask |= sibling->mask; 3481 return 0; 3482 } 3483 3484 bond = krealloc(ve->bonds, 3485 sizeof(*bond) * (ve->num_bonds + 1), 3486 GFP_KERNEL); 3487 if (!bond) 3488 return -ENOMEM; 3489 3490 bond[ve->num_bonds].master = master; 3491 bond[ve->num_bonds].sibling_mask = sibling->mask; 3492 3493 ve->bonds = bond; 3494 ve->num_bonds++; 3495 3496 return 0; 3497 } 3498 3499 void intel_execlists_show_requests(struct intel_engine_cs *engine, 3500 struct drm_printer *m, 3501 void (*show_request)(struct drm_printer *m, 3502 struct i915_request *rq, 3503 const char *prefix), 3504 unsigned int max) 3505 { 3506 const struct intel_engine_execlists *execlists = &engine->execlists; 3507 struct i915_request *rq, *last; 3508 unsigned long flags; 3509 unsigned int count; 3510 struct rb_node *rb; 3511 3512 spin_lock_irqsave(&engine->timeline.lock, flags); 3513 3514 last = NULL; 3515 count = 0; 3516 list_for_each_entry(rq, &engine->timeline.requests, link) { 3517 if (count++ < max - 1) 3518 show_request(m, rq, "\t\tE "); 3519 else 3520 last = rq; 3521 } 3522 if (last) { 3523 if (count > max) { 3524 drm_printf(m, 3525 "\t\t...skipping %d executing requests...\n", 3526 count - max); 3527 } 3528 show_request(m, last, "\t\tE "); 3529 } 3530 3531 last = NULL; 3532 count = 0; 3533 if (execlists->queue_priority_hint != INT_MIN) 3534 drm_printf(m, "\t\tQueue priority hint: %d\n", 3535 execlists->queue_priority_hint); 3536 for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) { 3537 struct i915_priolist *p = rb_entry(rb, typeof(*p), node); 3538 int i; 3539 3540 priolist_for_each_request(rq, p, i) { 3541 if (count++ < max - 1) 3542 show_request(m, rq, "\t\tQ "); 3543 else 3544 last = rq; 3545 } 3546 } 3547 if (last) { 3548 if (count > max) { 3549 drm_printf(m, 3550 "\t\t...skipping %d queued requests...\n", 3551 count - max); 3552 } 3553 show_request(m, last, "\t\tQ "); 3554 } 3555 3556 last = NULL; 3557 count = 0; 3558 for (rb = rb_first_cached(&execlists->virtual); rb; rb = rb_next(rb)) { 3559 struct virtual_engine *ve = 3560 rb_entry(rb, typeof(*ve), nodes[engine->id].rb); 3561 struct i915_request *rq = READ_ONCE(ve->request); 3562 3563 if (rq) { 3564 if (count++ < max - 1) 3565 show_request(m, rq, "\t\tV "); 3566 else 3567 last = rq; 3568 } 3569 } 3570 if (last) { 3571 if (count > max) { 3572 drm_printf(m, 3573 "\t\t...skipping %d virtual requests...\n", 3574 count - max); 3575 } 3576 show_request(m, last, "\t\tV "); 3577 } 3578 3579 spin_unlock_irqrestore(&engine->timeline.lock, flags); 3580 } 3581 3582 void intel_lr_context_reset(struct intel_engine_cs *engine, 3583 struct intel_context *ce, 3584 u32 head, 3585 bool scrub) 3586 { 3587 /* 3588 * We want a simple context + ring to execute the breadcrumb update. 3589 * We cannot rely on the context being intact across the GPU hang, 3590 * so clear it and rebuild just what we need for the breadcrumb. 3591 * All pending requests for this context will be zapped, and any 3592 * future request will be after userspace has had the opportunity 3593 * to recreate its own state. 3594 */ 3595 if (scrub) { 3596 u32 *regs = ce->lrc_reg_state; 3597 3598 if (engine->pinned_default_state) { 3599 memcpy(regs, /* skip restoring the vanilla PPHWSP */ 3600 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE, 3601 engine->context_size - PAGE_SIZE); 3602 } 3603 execlists_init_reg_state(regs, ce, engine, ce->ring); 3604 } 3605 3606 /* Rerun the request; its payload has been neutered (if guilty). */ 3607 ce->ring->head = head; 3608 intel_ring_update_space(ce->ring); 3609 3610 __execlists_update_reg_state(ce, engine); 3611 } 3612 3613 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 3614 #include "selftest_lrc.c" 3615 #endif 3616