1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * Michel Thierry <michel.thierry@intel.com> 26 * Thomas Daniel <thomas.daniel@intel.com> 27 * Oscar Mateo <oscar.mateo@intel.com> 28 * 29 */ 30 31 /** 32 * DOC: Logical Rings, Logical Ring Contexts and Execlists 33 * 34 * Motivation: 35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". 36 * These expanded contexts enable a number of new abilities, especially 37 * "Execlists" (also implemented in this file). 38 * 39 * One of the main differences with the legacy HW contexts is that logical 40 * ring contexts incorporate many more things to the context's state, like 41 * PDPs or ringbuffer control registers: 42 * 43 * The reason why PDPs are included in the context is straightforward: as 44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs 45 * contained there mean you don't need to do a ppgtt->switch_mm yourself, 46 * instead, the GPU will do it for you on the context switch. 47 * 48 * But, what about the ringbuffer control registers (head, tail, etc..)? 49 * shouldn't we just need a set of those per engine command streamer? This is 50 * where the name "Logical Rings" starts to make sense: by virtualizing the 51 * rings, the engine cs shifts to a new "ring buffer" with every context 52 * switch. When you want to submit a workload to the GPU you: A) choose your 53 * context, B) find its appropriate virtualized ring, C) write commands to it 54 * and then, finally, D) tell the GPU to switch to that context. 55 * 56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch 57 * to a contexts is via a context execution list, ergo "Execlists". 58 * 59 * LRC implementation: 60 * Regarding the creation of contexts, we have: 61 * 62 * - One global default context. 63 * - One local default context for each opened fd. 64 * - One local extra context for each context create ioctl call. 65 * 66 * Now that ringbuffers belong per-context (and not per-engine, like before) 67 * and that contexts are uniquely tied to a given engine (and not reusable, 68 * like before) we need: 69 * 70 * - One ringbuffer per-engine inside each context. 71 * - One backing object per-engine inside each context. 72 * 73 * The global default context starts its life with these new objects fully 74 * allocated and populated. The local default context for each opened fd is 75 * more complex, because we don't know at creation time which engine is going 76 * to use them. To handle this, we have implemented a deferred creation of LR 77 * contexts: 78 * 79 * The local context starts its life as a hollow or blank holder, that only 80 * gets populated for a given engine once we receive an execbuffer. If later 81 * on we receive another execbuffer ioctl for the same context but a different 82 * engine, we allocate/populate a new ringbuffer and context backing object and 83 * so on. 84 * 85 * Finally, regarding local contexts created using the ioctl call: as they are 86 * only allowed with the render ring, we can allocate & populate them right 87 * away (no need to defer anything, at least for now). 88 * 89 * Execlists implementation: 90 * Execlists are the new method by which, on gen8+ hardware, workloads are 91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method). 92 * This method works as follows: 93 * 94 * When a request is committed, its commands (the BB start and any leading or 95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer 96 * for the appropriate context. The tail pointer in the hardware context is not 97 * updated at this time, but instead, kept by the driver in the ringbuffer 98 * structure. A structure representing this request is added to a request queue 99 * for the appropriate engine: this structure contains a copy of the context's 100 * tail after the request was written to the ring buffer and a pointer to the 101 * context itself. 102 * 103 * If the engine's request queue was empty before the request was added, the 104 * queue is processed immediately. Otherwise the queue will be processed during 105 * a context switch interrupt. In any case, elements on the queue will get sent 106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a 107 * globally unique 20-bits submission ID. 108 * 109 * When execution of a request completes, the GPU updates the context status 110 * buffer with a context complete event and generates a context switch interrupt. 111 * During the interrupt handling, the driver examines the events in the buffer: 112 * for each context complete event, if the announced ID matches that on the head 113 * of the request queue, then that request is retired and removed from the queue. 114 * 115 * After processing, if any requests were retired and the queue is not empty 116 * then a new execution list can be submitted. The two requests at the front of 117 * the queue are next to be submitted but since a context may not occur twice in 118 * an execution list, if subsequent requests have the same ID as the first then 119 * the two requests must be combined. This is done simply by discarding requests 120 * at the head of the queue until either only one requests is left (in which case 121 * we use a NULL second context) or the first two requests have unique IDs. 122 * 123 * By always executing the first two requests in the queue the driver ensures 124 * that the GPU is kept as busy as possible. In the case where a single context 125 * completes but a second context is still executing, the request for this second 126 * context will be at the head of the queue when we remove the first one. This 127 * request will then be resubmitted along with a new request for a different context, 128 * which will cause the hardware to continue executing the second request and queue 129 * the new request (the GPU detects the condition of a context getting preempted 130 * with the same context and optimizes the context switch flow by not doing 131 * preemption, but just sampling the new tail pointer). 132 * 133 */ 134 #include <linux/interrupt.h> 135 136 #include "i915_drv.h" 137 #include "i915_gem_render_state.h" 138 #include "i915_vgpu.h" 139 #include "intel_engine_pm.h" 140 #include "intel_lrc_reg.h" 141 #include "intel_mocs.h" 142 #include "intel_reset.h" 143 #include "intel_workarounds.h" 144 145 #define RING_EXECLIST_QFULL (1 << 0x2) 146 #define RING_EXECLIST1_VALID (1 << 0x3) 147 #define RING_EXECLIST0_VALID (1 << 0x4) 148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) 149 #define RING_EXECLIST1_ACTIVE (1 << 0x11) 150 #define RING_EXECLIST0_ACTIVE (1 << 0x12) 151 152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) 153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) 154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) 155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) 156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4) 157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) 158 159 #define GEN8_CTX_STATUS_COMPLETED_MASK \ 160 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED) 161 162 /* Typical size of the average request (2 pipecontrols and a MI_BB) */ 163 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ 164 #define WA_TAIL_DWORDS 2 165 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS) 166 167 #define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT | I915_PRIORITY_NOSEMAPHORE) 168 169 static int execlists_context_deferred_alloc(struct intel_context *ce, 170 struct intel_engine_cs *engine); 171 static void execlists_init_reg_state(u32 *reg_state, 172 struct intel_context *ce, 173 struct intel_engine_cs *engine, 174 struct intel_ring *ring); 175 176 static inline struct i915_priolist *to_priolist(struct rb_node *rb) 177 { 178 return rb_entry(rb, struct i915_priolist, node); 179 } 180 181 static inline int rq_prio(const struct i915_request *rq) 182 { 183 return rq->sched.attr.priority; 184 } 185 186 static int effective_prio(const struct i915_request *rq) 187 { 188 int prio = rq_prio(rq); 189 190 /* 191 * On unwinding the active request, we give it a priority bump 192 * equivalent to a freshly submitted request. This protects it from 193 * being gazumped again, but it would be preferable if we didn't 194 * let it be gazumped in the first place! 195 * 196 * See __unwind_incomplete_requests() 197 */ 198 if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(rq)) { 199 /* 200 * After preemption, we insert the active request at the 201 * end of the new priority level. This means that we will be 202 * _lower_ priority than the preemptee all things equal (and 203 * so the preemption is valid), so adjust our comparison 204 * accordingly. 205 */ 206 prio |= ACTIVE_PRIORITY; 207 prio--; 208 } 209 210 /* Restrict mere WAIT boosts from triggering preemption */ 211 return prio | __NO_PREEMPTION; 212 } 213 214 static int queue_prio(const struct intel_engine_execlists *execlists) 215 { 216 struct i915_priolist *p; 217 struct rb_node *rb; 218 219 rb = rb_first_cached(&execlists->queue); 220 if (!rb) 221 return INT_MIN; 222 223 /* 224 * As the priolist[] are inverted, with the highest priority in [0], 225 * we have to flip the index value to become priority. 226 */ 227 p = to_priolist(rb); 228 return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used); 229 } 230 231 static inline bool need_preempt(const struct intel_engine_cs *engine, 232 const struct i915_request *rq) 233 { 234 int last_prio; 235 236 if (!engine->preempt_context) 237 return false; 238 239 if (i915_request_completed(rq)) 240 return false; 241 242 /* 243 * Check if the current priority hint merits a preemption attempt. 244 * 245 * We record the highest value priority we saw during rescheduling 246 * prior to this dequeue, therefore we know that if it is strictly 247 * less than the current tail of ESLP[0], we do not need to force 248 * a preempt-to-idle cycle. 249 * 250 * However, the priority hint is a mere hint that we may need to 251 * preempt. If that hint is stale or we may be trying to preempt 252 * ourselves, ignore the request. 253 */ 254 last_prio = effective_prio(rq); 255 if (!i915_scheduler_need_preempt(engine->execlists.queue_priority_hint, 256 last_prio)) 257 return false; 258 259 /* 260 * Check against the first request in ELSP[1], it will, thanks to the 261 * power of PI, be the highest priority of that context. 262 */ 263 if (!list_is_last(&rq->link, &engine->timeline.requests) && 264 rq_prio(list_next_entry(rq, link)) > last_prio) 265 return true; 266 267 /* 268 * If the inflight context did not trigger the preemption, then maybe 269 * it was the set of queued requests? Pick the highest priority in 270 * the queue (the first active priolist) and see if it deserves to be 271 * running instead of ELSP[0]. 272 * 273 * The highest priority request in the queue can not be either 274 * ELSP[0] or ELSP[1] as, thanks again to PI, if it was the same 275 * context, it's priority would not exceed ELSP[0] aka last_prio. 276 */ 277 return queue_prio(&engine->execlists) > last_prio; 278 } 279 280 __maybe_unused static inline bool 281 assert_priority_queue(const struct i915_request *prev, 282 const struct i915_request *next) 283 { 284 const struct intel_engine_execlists *execlists = 285 &prev->engine->execlists; 286 287 /* 288 * Without preemption, the prev may refer to the still active element 289 * which we refuse to let go. 290 * 291 * Even with preemption, there are times when we think it is better not 292 * to preempt and leave an ostensibly lower priority request in flight. 293 */ 294 if (port_request(execlists->port) == prev) 295 return true; 296 297 return rq_prio(prev) >= rq_prio(next); 298 } 299 300 /* 301 * The context descriptor encodes various attributes of a context, 302 * including its GTT address and some flags. Because it's fairly 303 * expensive to calculate, we'll just do it once and cache the result, 304 * which remains valid until the context is unpinned. 305 * 306 * This is what a descriptor looks like, from LSB to MSB:: 307 * 308 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template) 309 * bits 12-31: LRCA, GTT address of (the HWSP of) this context 310 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC) 311 * bits 53-54: mbz, reserved for use by hardware 312 * bits 55-63: group ID, currently unused and set to 0 313 * 314 * Starting from Gen11, the upper dword of the descriptor has a new format: 315 * 316 * bits 32-36: reserved 317 * bits 37-47: SW context ID 318 * bits 48:53: engine instance 319 * bit 54: mbz, reserved for use by hardware 320 * bits 55-60: SW counter 321 * bits 61-63: engine class 322 * 323 * engine info, SW context ID and SW counter need to form a unique number 324 * (Context ID) per lrc. 325 */ 326 static u64 327 lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine) 328 { 329 struct i915_gem_context *ctx = ce->gem_context; 330 u64 desc; 331 332 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH))); 333 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH))); 334 335 desc = ctx->desc_template; /* bits 0-11 */ 336 GEM_BUG_ON(desc & GENMASK_ULL(63, 12)); 337 338 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE; 339 /* bits 12-31 */ 340 GEM_BUG_ON(desc & GENMASK_ULL(63, 32)); 341 342 /* 343 * The following 32bits are copied into the OA reports (dword 2). 344 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing 345 * anything below. 346 */ 347 if (INTEL_GEN(engine->i915) >= 11) { 348 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH)); 349 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT; 350 /* bits 37-47 */ 351 352 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT; 353 /* bits 48-53 */ 354 355 /* TODO: decide what to do with SW counter (bits 55-60) */ 356 357 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT; 358 /* bits 61-63 */ 359 } else { 360 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH)); 361 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ 362 } 363 364 return desc; 365 } 366 367 static void unwind_wa_tail(struct i915_request *rq) 368 { 369 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES); 370 assert_ring_tail_valid(rq->ring, rq->tail); 371 } 372 373 static struct i915_request * 374 __unwind_incomplete_requests(struct intel_engine_cs *engine, int boost) 375 { 376 struct i915_request *rq, *rn, *active = NULL; 377 struct list_head *uninitialized_var(pl); 378 int prio = I915_PRIORITY_INVALID | boost; 379 380 lockdep_assert_held(&engine->timeline.lock); 381 382 list_for_each_entry_safe_reverse(rq, rn, 383 &engine->timeline.requests, 384 link) { 385 if (i915_request_completed(rq)) 386 break; 387 388 __i915_request_unsubmit(rq); 389 unwind_wa_tail(rq); 390 391 GEM_BUG_ON(rq->hw_context->active); 392 393 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); 394 if (rq_prio(rq) != prio) { 395 prio = rq_prio(rq); 396 pl = i915_sched_lookup_priolist(engine, prio); 397 } 398 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); 399 400 list_add(&rq->sched.link, pl); 401 402 active = rq; 403 } 404 405 /* 406 * The active request is now effectively the start of a new client 407 * stream, so give it the equivalent small priority bump to prevent 408 * it being gazumped a second time by another peer. 409 * 410 * Note we have to be careful not to apply a priority boost to a request 411 * still spinning on its semaphores. If the request hasn't started, that 412 * means it is still waiting for its dependencies to be signaled, and 413 * if we apply a priority boost to this request, we will boost it past 414 * its signalers and so break PI. 415 * 416 * One consequence of this preemption boost is that we may jump 417 * over lesser priorities (such as I915_PRIORITY_WAIT), effectively 418 * making those priorities non-preemptible. They will be moved forward 419 * in the priority queue, but they will not gain immediate access to 420 * the GPU. 421 */ 422 if (~prio & boost && __i915_request_has_started(active)) { 423 prio |= boost; 424 GEM_BUG_ON(active->sched.attr.priority >= prio); 425 active->sched.attr.priority = prio; 426 list_move_tail(&active->sched.link, 427 i915_sched_lookup_priolist(engine, prio)); 428 } 429 430 return active; 431 } 432 433 struct i915_request * 434 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists) 435 { 436 struct intel_engine_cs *engine = 437 container_of(execlists, typeof(*engine), execlists); 438 439 return __unwind_incomplete_requests(engine, 0); 440 } 441 442 static inline void 443 execlists_context_status_change(struct i915_request *rq, unsigned long status) 444 { 445 /* 446 * Only used when GVT-g is enabled now. When GVT-g is disabled, 447 * The compiler should eliminate this function as dead-code. 448 */ 449 if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) 450 return; 451 452 atomic_notifier_call_chain(&rq->engine->context_status_notifier, 453 status, rq); 454 } 455 456 inline void 457 execlists_user_begin(struct intel_engine_execlists *execlists, 458 const struct execlist_port *port) 459 { 460 execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER); 461 } 462 463 inline void 464 execlists_user_end(struct intel_engine_execlists *execlists) 465 { 466 execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER); 467 } 468 469 static inline void 470 execlists_context_schedule_in(struct i915_request *rq) 471 { 472 GEM_BUG_ON(rq->hw_context->active); 473 474 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); 475 intel_engine_context_in(rq->engine); 476 rq->hw_context->active = rq->engine; 477 } 478 479 static inline void 480 execlists_context_schedule_out(struct i915_request *rq, unsigned long status) 481 { 482 rq->hw_context->active = NULL; 483 intel_engine_context_out(rq->engine); 484 execlists_context_status_change(rq, status); 485 trace_i915_request_out(rq); 486 } 487 488 static u64 execlists_update_context(struct i915_request *rq) 489 { 490 struct intel_context *ce = rq->hw_context; 491 492 ce->lrc_reg_state[CTX_RING_TAIL + 1] = 493 intel_ring_set_tail(rq->ring, rq->tail); 494 495 /* 496 * Make sure the context image is complete before we submit it to HW. 497 * 498 * Ostensibly, writes (including the WCB) should be flushed prior to 499 * an uncached write such as our mmio register access, the empirical 500 * evidence (esp. on Braswell) suggests that the WC write into memory 501 * may not be visible to the HW prior to the completion of the UC 502 * register write and that we may begin execution from the context 503 * before its image is complete leading to invalid PD chasing. 504 * 505 * Furthermore, Braswell, at least, wants a full mb to be sure that 506 * the writes are coherent in memory (visible to the GPU) prior to 507 * execution, and not just visible to other CPUs (as is the result of 508 * wmb). 509 */ 510 mb(); 511 return ce->lrc_desc; 512 } 513 514 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port) 515 { 516 if (execlists->ctrl_reg) { 517 writel(lower_32_bits(desc), execlists->submit_reg + port * 2); 518 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1); 519 } else { 520 writel(upper_32_bits(desc), execlists->submit_reg); 521 writel(lower_32_bits(desc), execlists->submit_reg); 522 } 523 } 524 525 static void execlists_submit_ports(struct intel_engine_cs *engine) 526 { 527 struct intel_engine_execlists *execlists = &engine->execlists; 528 struct execlist_port *port = execlists->port; 529 unsigned int n; 530 531 /* 532 * We can skip acquiring intel_runtime_pm_get() here as it was taken 533 * on our behalf by the request (see i915_gem_mark_busy()) and it will 534 * not be relinquished until the device is idle (see 535 * i915_gem_idle_work_handler()). As a precaution, we make sure 536 * that all ELSP are drained i.e. we have processed the CSB, 537 * before allowing ourselves to idle and calling intel_runtime_pm_put(). 538 */ 539 GEM_BUG_ON(!intel_wakeref_active(&engine->wakeref)); 540 541 /* 542 * ELSQ note: the submit queue is not cleared after being submitted 543 * to the HW so we need to make sure we always clean it up. This is 544 * currently ensured by the fact that we always write the same number 545 * of elsq entries, keep this in mind before changing the loop below. 546 */ 547 for (n = execlists_num_ports(execlists); n--; ) { 548 struct i915_request *rq; 549 unsigned int count; 550 u64 desc; 551 552 rq = port_unpack(&port[n], &count); 553 if (rq) { 554 GEM_BUG_ON(count > !n); 555 if (!count++) 556 execlists_context_schedule_in(rq); 557 port_set(&port[n], port_pack(rq, count)); 558 desc = execlists_update_context(rq); 559 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); 560 561 GEM_TRACE("%s in[%d]: ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n", 562 engine->name, n, 563 port[n].context_id, count, 564 rq->fence.context, rq->fence.seqno, 565 hwsp_seqno(rq), 566 rq_prio(rq)); 567 } else { 568 GEM_BUG_ON(!n); 569 desc = 0; 570 } 571 572 write_desc(execlists, desc, n); 573 } 574 575 /* we need to manually load the submit queue */ 576 if (execlists->ctrl_reg) 577 writel(EL_CTRL_LOAD, execlists->ctrl_reg); 578 579 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); 580 } 581 582 static bool ctx_single_port_submission(const struct intel_context *ce) 583 { 584 return (IS_ENABLED(CONFIG_DRM_I915_GVT) && 585 i915_gem_context_force_single_submission(ce->gem_context)); 586 } 587 588 static bool can_merge_ctx(const struct intel_context *prev, 589 const struct intel_context *next) 590 { 591 if (prev != next) 592 return false; 593 594 if (ctx_single_port_submission(prev)) 595 return false; 596 597 return true; 598 } 599 600 static bool can_merge_rq(const struct i915_request *prev, 601 const struct i915_request *next) 602 { 603 GEM_BUG_ON(!assert_priority_queue(prev, next)); 604 605 if (!can_merge_ctx(prev->hw_context, next->hw_context)) 606 return false; 607 608 return true; 609 } 610 611 static void port_assign(struct execlist_port *port, struct i915_request *rq) 612 { 613 GEM_BUG_ON(rq == port_request(port)); 614 615 if (port_isset(port)) 616 i915_request_put(port_request(port)); 617 618 port_set(port, port_pack(i915_request_get(rq), port_count(port))); 619 } 620 621 static void inject_preempt_context(struct intel_engine_cs *engine) 622 { 623 struct intel_engine_execlists *execlists = &engine->execlists; 624 struct intel_context *ce = engine->preempt_context; 625 unsigned int n; 626 627 GEM_BUG_ON(execlists->preempt_complete_status != 628 upper_32_bits(ce->lrc_desc)); 629 630 /* 631 * Switch to our empty preempt context so 632 * the state of the GPU is known (idle). 633 */ 634 GEM_TRACE("%s\n", engine->name); 635 for (n = execlists_num_ports(execlists); --n; ) 636 write_desc(execlists, 0, n); 637 638 write_desc(execlists, ce->lrc_desc, n); 639 640 /* we need to manually load the submit queue */ 641 if (execlists->ctrl_reg) 642 writel(EL_CTRL_LOAD, execlists->ctrl_reg); 643 644 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); 645 execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT); 646 647 (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++); 648 } 649 650 static void complete_preempt_context(struct intel_engine_execlists *execlists) 651 { 652 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT)); 653 654 if (inject_preempt_hang(execlists)) 655 return; 656 657 execlists_cancel_port_requests(execlists); 658 __unwind_incomplete_requests(container_of(execlists, 659 struct intel_engine_cs, 660 execlists), 661 ACTIVE_PRIORITY); 662 } 663 664 static void execlists_dequeue(struct intel_engine_cs *engine) 665 { 666 struct intel_engine_execlists * const execlists = &engine->execlists; 667 struct execlist_port *port = execlists->port; 668 const struct execlist_port * const last_port = 669 &execlists->port[execlists->port_mask]; 670 struct i915_request *last = port_request(port); 671 struct rb_node *rb; 672 bool submit = false; 673 674 /* 675 * Hardware submission is through 2 ports. Conceptually each port 676 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is 677 * static for a context, and unique to each, so we only execute 678 * requests belonging to a single context from each ring. RING_HEAD 679 * is maintained by the CS in the context image, it marks the place 680 * where it got up to last time, and through RING_TAIL we tell the CS 681 * where we want to execute up to this time. 682 * 683 * In this list the requests are in order of execution. Consecutive 684 * requests from the same context are adjacent in the ringbuffer. We 685 * can combine these requests into a single RING_TAIL update: 686 * 687 * RING_HEAD...req1...req2 688 * ^- RING_TAIL 689 * since to execute req2 the CS must first execute req1. 690 * 691 * Our goal then is to point each port to the end of a consecutive 692 * sequence of requests as being the most optimal (fewest wake ups 693 * and context switches) submission. 694 */ 695 696 if (last) { 697 /* 698 * Don't resubmit or switch until all outstanding 699 * preemptions (lite-restore) are seen. Then we 700 * know the next preemption status we see corresponds 701 * to this ELSP update. 702 */ 703 GEM_BUG_ON(!execlists_is_active(execlists, 704 EXECLISTS_ACTIVE_USER)); 705 GEM_BUG_ON(!port_count(&port[0])); 706 707 /* 708 * If we write to ELSP a second time before the HW has had 709 * a chance to respond to the previous write, we can confuse 710 * the HW and hit "undefined behaviour". After writing to ELSP, 711 * we must then wait until we see a context-switch event from 712 * the HW to indicate that it has had a chance to respond. 713 */ 714 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK)) 715 return; 716 717 if (need_preempt(engine, last)) { 718 inject_preempt_context(engine); 719 return; 720 } 721 722 /* 723 * In theory, we could coalesce more requests onto 724 * the second port (the first port is active, with 725 * no preemptions pending). However, that means we 726 * then have to deal with the possible lite-restore 727 * of the second port (as we submit the ELSP, there 728 * may be a context-switch) but also we may complete 729 * the resubmission before the context-switch. Ergo, 730 * coalescing onto the second port will cause a 731 * preemption event, but we cannot predict whether 732 * that will affect port[0] or port[1]. 733 * 734 * If the second port is already active, we can wait 735 * until the next context-switch before contemplating 736 * new requests. The GPU will be busy and we should be 737 * able to resubmit the new ELSP before it idles, 738 * avoiding pipeline bubbles (momentary pauses where 739 * the driver is unable to keep up the supply of new 740 * work). However, we have to double check that the 741 * priorities of the ports haven't been switch. 742 */ 743 if (port_count(&port[1])) 744 return; 745 746 /* 747 * WaIdleLiteRestore:bdw,skl 748 * Apply the wa NOOPs to prevent 749 * ring:HEAD == rq:TAIL as we resubmit the 750 * request. See gen8_emit_fini_breadcrumb() for 751 * where we prepare the padding after the 752 * end of the request. 753 */ 754 last->tail = last->wa_tail; 755 } 756 757 while ((rb = rb_first_cached(&execlists->queue))) { 758 struct i915_priolist *p = to_priolist(rb); 759 struct i915_request *rq, *rn; 760 int i; 761 762 priolist_for_each_request_consume(rq, rn, p, i) { 763 /* 764 * Can we combine this request with the current port? 765 * It has to be the same context/ringbuffer and not 766 * have any exceptions (e.g. GVT saying never to 767 * combine contexts). 768 * 769 * If we can combine the requests, we can execute both 770 * by updating the RING_TAIL to point to the end of the 771 * second request, and so we never need to tell the 772 * hardware about the first. 773 */ 774 if (last && !can_merge_rq(last, rq)) { 775 /* 776 * If we are on the second port and cannot 777 * combine this request with the last, then we 778 * are done. 779 */ 780 if (port == last_port) 781 goto done; 782 783 /* 784 * We must not populate both ELSP[] with the 785 * same LRCA, i.e. we must submit 2 different 786 * contexts if we submit 2 ELSP. 787 */ 788 if (last->hw_context == rq->hw_context) 789 goto done; 790 791 /* 792 * If GVT overrides us we only ever submit 793 * port[0], leaving port[1] empty. Note that we 794 * also have to be careful that we don't queue 795 * the same context (even though a different 796 * request) to the second port. 797 */ 798 if (ctx_single_port_submission(last->hw_context) || 799 ctx_single_port_submission(rq->hw_context)) 800 goto done; 801 802 803 if (submit) 804 port_assign(port, last); 805 port++; 806 807 GEM_BUG_ON(port_isset(port)); 808 } 809 810 list_del_init(&rq->sched.link); 811 812 __i915_request_submit(rq); 813 trace_i915_request_in(rq, port_index(port, execlists)); 814 815 last = rq; 816 submit = true; 817 } 818 819 rb_erase_cached(&p->node, &execlists->queue); 820 i915_priolist_free(p); 821 } 822 823 done: 824 /* 825 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer. 826 * 827 * We choose the priority hint such that if we add a request of greater 828 * priority than this, we kick the submission tasklet to decide on 829 * the right order of submitting the requests to hardware. We must 830 * also be prepared to reorder requests as they are in-flight on the 831 * HW. We derive the priority hint then as the first "hole" in 832 * the HW submission ports and if there are no available slots, 833 * the priority of the lowest executing request, i.e. last. 834 * 835 * When we do receive a higher priority request ready to run from the 836 * user, see queue_request(), the priority hint is bumped to that 837 * request triggering preemption on the next dequeue (or subsequent 838 * interrupt for secondary ports). 839 */ 840 execlists->queue_priority_hint = queue_prio(execlists); 841 842 if (submit) { 843 port_assign(port, last); 844 execlists_submit_ports(engine); 845 } 846 847 /* We must always keep the beast fed if we have work piled up */ 848 GEM_BUG_ON(rb_first_cached(&execlists->queue) && 849 !port_isset(execlists->port)); 850 851 /* Re-evaluate the executing context setup after each preemptive kick */ 852 if (last) 853 execlists_user_begin(execlists, execlists->port); 854 855 /* If the engine is now idle, so should be the flag; and vice versa. */ 856 GEM_BUG_ON(execlists_is_active(&engine->execlists, 857 EXECLISTS_ACTIVE_USER) == 858 !port_isset(engine->execlists.port)); 859 } 860 861 void 862 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists) 863 { 864 struct execlist_port *port = execlists->port; 865 unsigned int num_ports = execlists_num_ports(execlists); 866 867 while (num_ports-- && port_isset(port)) { 868 struct i915_request *rq = port_request(port); 869 870 GEM_TRACE("%s:port%u fence %llx:%lld, (current %d)\n", 871 rq->engine->name, 872 (unsigned int)(port - execlists->port), 873 rq->fence.context, rq->fence.seqno, 874 hwsp_seqno(rq)); 875 876 GEM_BUG_ON(!execlists->active); 877 execlists_context_schedule_out(rq, 878 i915_request_completed(rq) ? 879 INTEL_CONTEXT_SCHEDULE_OUT : 880 INTEL_CONTEXT_SCHEDULE_PREEMPTED); 881 882 i915_request_put(rq); 883 884 memset(port, 0, sizeof(*port)); 885 port++; 886 } 887 888 execlists_clear_all_active(execlists); 889 } 890 891 static inline void 892 invalidate_csb_entries(const u32 *first, const u32 *last) 893 { 894 clflush((void *)first); 895 clflush((void *)last); 896 } 897 898 static inline bool 899 reset_in_progress(const struct intel_engine_execlists *execlists) 900 { 901 return unlikely(!__tasklet_is_enabled(&execlists->tasklet)); 902 } 903 904 static void process_csb(struct intel_engine_cs *engine) 905 { 906 struct intel_engine_execlists * const execlists = &engine->execlists; 907 struct execlist_port *port = execlists->port; 908 const u32 * const buf = execlists->csb_status; 909 const u8 num_entries = execlists->csb_size; 910 u8 head, tail; 911 912 lockdep_assert_held(&engine->timeline.lock); 913 914 /* 915 * Note that csb_write, csb_status may be either in HWSP or mmio. 916 * When reading from the csb_write mmio register, we have to be 917 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is 918 * the low 4bits. As it happens we know the next 4bits are always 919 * zero and so we can simply masked off the low u8 of the register 920 * and treat it identically to reading from the HWSP (without having 921 * to use explicit shifting and masking, and probably bifurcating 922 * the code to handle the legacy mmio read). 923 */ 924 head = execlists->csb_head; 925 tail = READ_ONCE(*execlists->csb_write); 926 GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail); 927 if (unlikely(head == tail)) 928 return; 929 930 /* 931 * Hopefully paired with a wmb() in HW! 932 * 933 * We must complete the read of the write pointer before any reads 934 * from the CSB, so that we do not see stale values. Without an rmb 935 * (lfence) the HW may speculatively perform the CSB[] reads *before* 936 * we perform the READ_ONCE(*csb_write). 937 */ 938 rmb(); 939 940 do { 941 struct i915_request *rq; 942 unsigned int status; 943 unsigned int count; 944 945 if (++head == num_entries) 946 head = 0; 947 948 /* 949 * We are flying near dragons again. 950 * 951 * We hold a reference to the request in execlist_port[] 952 * but no more than that. We are operating in softirq 953 * context and so cannot hold any mutex or sleep. That 954 * prevents us stopping the requests we are processing 955 * in port[] from being retired simultaneously (the 956 * breadcrumb will be complete before we see the 957 * context-switch). As we only hold the reference to the 958 * request, any pointer chasing underneath the request 959 * is subject to a potential use-after-free. Thus we 960 * store all of the bookkeeping within port[] as 961 * required, and avoid using unguarded pointers beneath 962 * request itself. The same applies to the atomic 963 * status notifier. 964 */ 965 966 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n", 967 engine->name, head, 968 buf[2 * head + 0], buf[2 * head + 1], 969 execlists->active); 970 971 status = buf[2 * head]; 972 if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE | 973 GEN8_CTX_STATUS_PREEMPTED)) 974 execlists_set_active(execlists, 975 EXECLISTS_ACTIVE_HWACK); 976 if (status & GEN8_CTX_STATUS_ACTIVE_IDLE) 977 execlists_clear_active(execlists, 978 EXECLISTS_ACTIVE_HWACK); 979 980 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) 981 continue; 982 983 /* We should never get a COMPLETED | IDLE_ACTIVE! */ 984 GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE); 985 986 if (status & GEN8_CTX_STATUS_COMPLETE && 987 buf[2*head + 1] == execlists->preempt_complete_status) { 988 GEM_TRACE("%s preempt-idle\n", engine->name); 989 complete_preempt_context(execlists); 990 continue; 991 } 992 993 if (status & GEN8_CTX_STATUS_PREEMPTED && 994 execlists_is_active(execlists, 995 EXECLISTS_ACTIVE_PREEMPT)) 996 continue; 997 998 GEM_BUG_ON(!execlists_is_active(execlists, 999 EXECLISTS_ACTIVE_USER)); 1000 1001 rq = port_unpack(port, &count); 1002 GEM_TRACE("%s out[0]: ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n", 1003 engine->name, 1004 port->context_id, count, 1005 rq ? rq->fence.context : 0, 1006 rq ? rq->fence.seqno : 0, 1007 rq ? hwsp_seqno(rq) : 0, 1008 rq ? rq_prio(rq) : 0); 1009 1010 /* Check the context/desc id for this event matches */ 1011 GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id); 1012 1013 GEM_BUG_ON(count == 0); 1014 if (--count == 0) { 1015 /* 1016 * On the final event corresponding to the 1017 * submission of this context, we expect either 1018 * an element-switch event or a completion 1019 * event (and on completion, the active-idle 1020 * marker). No more preemptions, lite-restore 1021 * or otherwise. 1022 */ 1023 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); 1024 GEM_BUG_ON(port_isset(&port[1]) && 1025 !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH)); 1026 GEM_BUG_ON(!port_isset(&port[1]) && 1027 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); 1028 1029 /* 1030 * We rely on the hardware being strongly 1031 * ordered, that the breadcrumb write is 1032 * coherent (visible from the CPU) before the 1033 * user interrupt and CSB is processed. 1034 */ 1035 GEM_BUG_ON(!i915_request_completed(rq)); 1036 1037 execlists_context_schedule_out(rq, 1038 INTEL_CONTEXT_SCHEDULE_OUT); 1039 i915_request_put(rq); 1040 1041 GEM_TRACE("%s completed ctx=%d\n", 1042 engine->name, port->context_id); 1043 1044 port = execlists_port_complete(execlists, port); 1045 if (port_isset(port)) 1046 execlists_user_begin(execlists, port); 1047 else 1048 execlists_user_end(execlists); 1049 } else { 1050 port_set(port, port_pack(rq, count)); 1051 } 1052 } while (head != tail); 1053 1054 execlists->csb_head = head; 1055 1056 /* 1057 * Gen11 has proven to fail wrt global observation point between 1058 * entry and tail update, failing on the ordering and thus 1059 * we see an old entry in the context status buffer. 1060 * 1061 * Forcibly evict out entries for the next gpu csb update, 1062 * to increase the odds that we get a fresh entries with non 1063 * working hardware. The cost for doing so comes out mostly with 1064 * the wash as hardware, working or not, will need to do the 1065 * invalidation before. 1066 */ 1067 invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); 1068 } 1069 1070 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) 1071 { 1072 lockdep_assert_held(&engine->timeline.lock); 1073 1074 process_csb(engine); 1075 if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT)) 1076 execlists_dequeue(engine); 1077 } 1078 1079 /* 1080 * Check the unread Context Status Buffers and manage the submission of new 1081 * contexts to the ELSP accordingly. 1082 */ 1083 static void execlists_submission_tasklet(unsigned long data) 1084 { 1085 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; 1086 unsigned long flags; 1087 1088 GEM_TRACE("%s awake?=%d, active=%x\n", 1089 engine->name, 1090 !!intel_wakeref_active(&engine->wakeref), 1091 engine->execlists.active); 1092 1093 spin_lock_irqsave(&engine->timeline.lock, flags); 1094 __execlists_submission_tasklet(engine); 1095 spin_unlock_irqrestore(&engine->timeline.lock, flags); 1096 } 1097 1098 static void queue_request(struct intel_engine_cs *engine, 1099 struct i915_sched_node *node, 1100 int prio) 1101 { 1102 list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio)); 1103 } 1104 1105 static void __submit_queue_imm(struct intel_engine_cs *engine) 1106 { 1107 struct intel_engine_execlists * const execlists = &engine->execlists; 1108 1109 if (reset_in_progress(execlists)) 1110 return; /* defer until we restart the engine following reset */ 1111 1112 if (execlists->tasklet.func == execlists_submission_tasklet) 1113 __execlists_submission_tasklet(engine); 1114 else 1115 tasklet_hi_schedule(&execlists->tasklet); 1116 } 1117 1118 static void submit_queue(struct intel_engine_cs *engine, int prio) 1119 { 1120 if (prio > engine->execlists.queue_priority_hint) { 1121 engine->execlists.queue_priority_hint = prio; 1122 __submit_queue_imm(engine); 1123 } 1124 } 1125 1126 static void execlists_submit_request(struct i915_request *request) 1127 { 1128 struct intel_engine_cs *engine = request->engine; 1129 unsigned long flags; 1130 1131 /* Will be called from irq-context when using foreign fences. */ 1132 spin_lock_irqsave(&engine->timeline.lock, flags); 1133 1134 queue_request(engine, &request->sched, rq_prio(request)); 1135 1136 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); 1137 GEM_BUG_ON(list_empty(&request->sched.link)); 1138 1139 submit_queue(engine, rq_prio(request)); 1140 1141 spin_unlock_irqrestore(&engine->timeline.lock, flags); 1142 } 1143 1144 static void __execlists_context_fini(struct intel_context *ce) 1145 { 1146 intel_ring_put(ce->ring); 1147 1148 GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj)); 1149 i915_gem_object_put(ce->state->obj); 1150 } 1151 1152 static void execlists_context_destroy(struct kref *kref) 1153 { 1154 struct intel_context *ce = container_of(kref, typeof(*ce), ref); 1155 1156 GEM_BUG_ON(intel_context_is_pinned(ce)); 1157 1158 if (ce->state) 1159 __execlists_context_fini(ce); 1160 1161 intel_context_free(ce); 1162 } 1163 1164 static int __context_pin(struct i915_vma *vma) 1165 { 1166 unsigned int flags; 1167 int err; 1168 1169 flags = PIN_GLOBAL | PIN_HIGH; 1170 flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); 1171 1172 err = i915_vma_pin(vma, 0, 0, flags); 1173 if (err) 1174 return err; 1175 1176 vma->obj->pin_global++; 1177 vma->obj->mm.dirty = true; 1178 1179 return 0; 1180 } 1181 1182 static void __context_unpin(struct i915_vma *vma) 1183 { 1184 vma->obj->pin_global--; 1185 __i915_vma_unpin(vma); 1186 } 1187 1188 static void execlists_context_unpin(struct intel_context *ce) 1189 { 1190 struct intel_engine_cs *engine; 1191 1192 /* 1193 * The tasklet may still be using a pointer to our state, via an 1194 * old request. However, since we know we only unpin the context 1195 * on retirement of the following request, we know that the last 1196 * request referencing us will have had a completion CS interrupt. 1197 * If we see that it is still active, it means that the tasklet hasn't 1198 * had the chance to run yet; let it run before we teardown the 1199 * reference it may use. 1200 */ 1201 engine = READ_ONCE(ce->active); 1202 if (unlikely(engine)) { 1203 unsigned long flags; 1204 1205 spin_lock_irqsave(&engine->timeline.lock, flags); 1206 process_csb(engine); 1207 spin_unlock_irqrestore(&engine->timeline.lock, flags); 1208 1209 GEM_BUG_ON(READ_ONCE(ce->active)); 1210 } 1211 1212 i915_gem_context_unpin_hw_id(ce->gem_context); 1213 1214 intel_ring_unpin(ce->ring); 1215 1216 i915_gem_object_unpin_map(ce->state->obj); 1217 __context_unpin(ce->state); 1218 } 1219 1220 static void 1221 __execlists_update_reg_state(struct intel_context *ce, 1222 struct intel_engine_cs *engine) 1223 { 1224 struct intel_ring *ring = ce->ring; 1225 u32 *regs = ce->lrc_reg_state; 1226 1227 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); 1228 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); 1229 1230 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma); 1231 regs[CTX_RING_HEAD + 1] = ring->head; 1232 regs[CTX_RING_TAIL + 1] = ring->tail; 1233 1234 /* RPCS */ 1235 if (engine->class == RENDER_CLASS) 1236 regs[CTX_R_PWR_CLK_STATE + 1] = 1237 intel_sseu_make_rpcs(engine->i915, &ce->sseu); 1238 } 1239 1240 static int 1241 __execlists_context_pin(struct intel_context *ce, 1242 struct intel_engine_cs *engine) 1243 { 1244 void *vaddr; 1245 int ret; 1246 1247 GEM_BUG_ON(!ce->gem_context->ppgtt); 1248 1249 ret = execlists_context_deferred_alloc(ce, engine); 1250 if (ret) 1251 goto err; 1252 GEM_BUG_ON(!ce->state); 1253 1254 ret = __context_pin(ce->state); 1255 if (ret) 1256 goto err; 1257 1258 vaddr = i915_gem_object_pin_map(ce->state->obj, 1259 i915_coherent_map_type(engine->i915) | 1260 I915_MAP_OVERRIDE); 1261 if (IS_ERR(vaddr)) { 1262 ret = PTR_ERR(vaddr); 1263 goto unpin_vma; 1264 } 1265 1266 ret = intel_ring_pin(ce->ring); 1267 if (ret) 1268 goto unpin_map; 1269 1270 ret = i915_gem_context_pin_hw_id(ce->gem_context); 1271 if (ret) 1272 goto unpin_ring; 1273 1274 ce->lrc_desc = lrc_descriptor(ce, engine); 1275 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; 1276 __execlists_update_reg_state(ce, engine); 1277 1278 return 0; 1279 1280 unpin_ring: 1281 intel_ring_unpin(ce->ring); 1282 unpin_map: 1283 i915_gem_object_unpin_map(ce->state->obj); 1284 unpin_vma: 1285 __context_unpin(ce->state); 1286 err: 1287 return ret; 1288 } 1289 1290 static int execlists_context_pin(struct intel_context *ce) 1291 { 1292 return __execlists_context_pin(ce, ce->engine); 1293 } 1294 1295 static void execlists_context_reset(struct intel_context *ce) 1296 { 1297 /* 1298 * Because we emit WA_TAIL_DWORDS there may be a disparity 1299 * between our bookkeeping in ce->ring->head and ce->ring->tail and 1300 * that stored in context. As we only write new commands from 1301 * ce->ring->tail onwards, everything before that is junk. If the GPU 1302 * starts reading from its RING_HEAD from the context, it may try to 1303 * execute that junk and die. 1304 * 1305 * The contexts that are stilled pinned on resume belong to the 1306 * kernel, and are local to each engine. All other contexts will 1307 * have their head/tail sanitized upon pinning before use, so they 1308 * will never see garbage, 1309 * 1310 * So to avoid that we reset the context images upon resume. For 1311 * simplicity, we just zero everything out. 1312 */ 1313 intel_ring_reset(ce->ring, 0); 1314 __execlists_update_reg_state(ce, ce->engine); 1315 } 1316 1317 static const struct intel_context_ops execlists_context_ops = { 1318 .pin = execlists_context_pin, 1319 .unpin = execlists_context_unpin, 1320 1321 .enter = intel_context_enter_engine, 1322 .exit = intel_context_exit_engine, 1323 1324 .reset = execlists_context_reset, 1325 .destroy = execlists_context_destroy, 1326 }; 1327 1328 static int gen8_emit_init_breadcrumb(struct i915_request *rq) 1329 { 1330 u32 *cs; 1331 1332 GEM_BUG_ON(!rq->timeline->has_initial_breadcrumb); 1333 1334 cs = intel_ring_begin(rq, 6); 1335 if (IS_ERR(cs)) 1336 return PTR_ERR(cs); 1337 1338 /* 1339 * Check if we have been preempted before we even get started. 1340 * 1341 * After this point i915_request_started() reports true, even if 1342 * we get preempted and so are no longer running. 1343 */ 1344 *cs++ = MI_ARB_CHECK; 1345 *cs++ = MI_NOOP; 1346 1347 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; 1348 *cs++ = rq->timeline->hwsp_offset; 1349 *cs++ = 0; 1350 *cs++ = rq->fence.seqno - 1; 1351 1352 intel_ring_advance(rq, cs); 1353 1354 /* Record the updated position of the request's payload */ 1355 rq->infix = intel_ring_offset(rq, cs); 1356 1357 return 0; 1358 } 1359 1360 static int emit_pdps(struct i915_request *rq) 1361 { 1362 const struct intel_engine_cs * const engine = rq->engine; 1363 struct i915_hw_ppgtt * const ppgtt = rq->gem_context->ppgtt; 1364 int err, i; 1365 u32 *cs; 1366 1367 GEM_BUG_ON(intel_vgpu_active(rq->i915)); 1368 1369 /* 1370 * Beware ye of the dragons, this sequence is magic! 1371 * 1372 * Small changes to this sequence can cause anything from 1373 * GPU hangs to forcewake errors and machine lockups! 1374 */ 1375 1376 /* Flush any residual operations from the context load */ 1377 err = engine->emit_flush(rq, EMIT_FLUSH); 1378 if (err) 1379 return err; 1380 1381 /* Magic required to prevent forcewake errors! */ 1382 err = engine->emit_flush(rq, EMIT_INVALIDATE); 1383 if (err) 1384 return err; 1385 1386 cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2); 1387 if (IS_ERR(cs)) 1388 return PTR_ERR(cs); 1389 1390 /* Ensure the LRI have landed before we invalidate & continue */ 1391 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED; 1392 for (i = GEN8_3LVL_PDPES; i--; ) { 1393 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); 1394 u32 base = engine->mmio_base; 1395 1396 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i)); 1397 *cs++ = upper_32_bits(pd_daddr); 1398 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i)); 1399 *cs++ = lower_32_bits(pd_daddr); 1400 } 1401 *cs++ = MI_NOOP; 1402 1403 intel_ring_advance(rq, cs); 1404 1405 /* Be doubly sure the LRI have landed before proceeding */ 1406 err = engine->emit_flush(rq, EMIT_FLUSH); 1407 if (err) 1408 return err; 1409 1410 /* Re-invalidate the TLB for luck */ 1411 return engine->emit_flush(rq, EMIT_INVALIDATE); 1412 } 1413 1414 static int execlists_request_alloc(struct i915_request *request) 1415 { 1416 int ret; 1417 1418 GEM_BUG_ON(!intel_context_is_pinned(request->hw_context)); 1419 1420 /* 1421 * Flush enough space to reduce the likelihood of waiting after 1422 * we start building the request - in which case we will just 1423 * have to repeat work. 1424 */ 1425 request->reserved_space += EXECLISTS_REQUEST_SIZE; 1426 1427 /* 1428 * Note that after this point, we have committed to using 1429 * this request as it is being used to both track the 1430 * state of engine initialisation and liveness of the 1431 * golden renderstate above. Think twice before you try 1432 * to cancel/unwind this request now. 1433 */ 1434 1435 /* Unconditionally invalidate GPU caches and TLBs. */ 1436 if (i915_vm_is_4lvl(&request->gem_context->ppgtt->vm)) 1437 ret = request->engine->emit_flush(request, EMIT_INVALIDATE); 1438 else 1439 ret = emit_pdps(request); 1440 if (ret) 1441 return ret; 1442 1443 request->reserved_space -= EXECLISTS_REQUEST_SIZE; 1444 return 0; 1445 } 1446 1447 /* 1448 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after 1449 * PIPE_CONTROL instruction. This is required for the flush to happen correctly 1450 * but there is a slight complication as this is applied in WA batch where the 1451 * values are only initialized once so we cannot take register value at the 1452 * beginning and reuse it further; hence we save its value to memory, upload a 1453 * constant value with bit21 set and then we restore it back with the saved value. 1454 * To simplify the WA, a constant value is formed by using the default value 1455 * of this register. This shouldn't be a problem because we are only modifying 1456 * it for a short period and this batch in non-premptible. We can ofcourse 1457 * use additional instructions that read the actual value of the register 1458 * at that time and set our bit of interest but it makes the WA complicated. 1459 * 1460 * This WA is also required for Gen9 so extracting as a function avoids 1461 * code duplication. 1462 */ 1463 static u32 * 1464 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) 1465 { 1466 /* NB no one else is allowed to scribble over scratch + 256! */ 1467 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; 1468 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); 1469 *batch++ = i915_scratch_offset(engine->i915) + 256; 1470 *batch++ = 0; 1471 1472 *batch++ = MI_LOAD_REGISTER_IMM(1); 1473 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); 1474 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; 1475 1476 batch = gen8_emit_pipe_control(batch, 1477 PIPE_CONTROL_CS_STALL | 1478 PIPE_CONTROL_DC_FLUSH_ENABLE, 1479 0); 1480 1481 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; 1482 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); 1483 *batch++ = i915_scratch_offset(engine->i915) + 256; 1484 *batch++ = 0; 1485 1486 return batch; 1487 } 1488 1489 /* 1490 * Typically we only have one indirect_ctx and per_ctx batch buffer which are 1491 * initialized at the beginning and shared across all contexts but this field 1492 * helps us to have multiple batches at different offsets and select them based 1493 * on a criteria. At the moment this batch always start at the beginning of the page 1494 * and at this point we don't have multiple wa_ctx batch buffers. 1495 * 1496 * The number of WA applied are not known at the beginning; we use this field 1497 * to return the no of DWORDS written. 1498 * 1499 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END 1500 * so it adds NOOPs as padding to make it cacheline aligned. 1501 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together 1502 * makes a complete batch buffer. 1503 */ 1504 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) 1505 { 1506 /* WaDisableCtxRestoreArbitration:bdw,chv */ 1507 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 1508 1509 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ 1510 if (IS_BROADWELL(engine->i915)) 1511 batch = gen8_emit_flush_coherentl3_wa(engine, batch); 1512 1513 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ 1514 /* Actual scratch location is at 128 bytes offset */ 1515 batch = gen8_emit_pipe_control(batch, 1516 PIPE_CONTROL_FLUSH_L3 | 1517 PIPE_CONTROL_GLOBAL_GTT_IVB | 1518 PIPE_CONTROL_CS_STALL | 1519 PIPE_CONTROL_QW_WRITE, 1520 i915_scratch_offset(engine->i915) + 1521 2 * CACHELINE_BYTES); 1522 1523 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 1524 1525 /* Pad to end of cacheline */ 1526 while ((unsigned long)batch % CACHELINE_BYTES) 1527 *batch++ = MI_NOOP; 1528 1529 /* 1530 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because 1531 * execution depends on the length specified in terms of cache lines 1532 * in the register CTX_RCS_INDIRECT_CTX 1533 */ 1534 1535 return batch; 1536 } 1537 1538 struct lri { 1539 i915_reg_t reg; 1540 u32 value; 1541 }; 1542 1543 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count) 1544 { 1545 GEM_BUG_ON(!count || count > 63); 1546 1547 *batch++ = MI_LOAD_REGISTER_IMM(count); 1548 do { 1549 *batch++ = i915_mmio_reg_offset(lri->reg); 1550 *batch++ = lri->value; 1551 } while (lri++, --count); 1552 *batch++ = MI_NOOP; 1553 1554 return batch; 1555 } 1556 1557 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) 1558 { 1559 static const struct lri lri[] = { 1560 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ 1561 { 1562 COMMON_SLICE_CHICKEN2, 1563 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE, 1564 0), 1565 }, 1566 1567 /* BSpec: 11391 */ 1568 { 1569 FF_SLICE_CHICKEN, 1570 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX, 1571 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX), 1572 }, 1573 1574 /* BSpec: 11299 */ 1575 { 1576 _3D_CHICKEN3, 1577 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX, 1578 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX), 1579 } 1580 }; 1581 1582 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 1583 1584 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ 1585 batch = gen8_emit_flush_coherentl3_wa(engine, batch); 1586 1587 batch = emit_lri(batch, lri, ARRAY_SIZE(lri)); 1588 1589 /* WaMediaPoolStateCmdInWABB:bxt,glk */ 1590 if (HAS_POOLED_EU(engine->i915)) { 1591 /* 1592 * EU pool configuration is setup along with golden context 1593 * during context initialization. This value depends on 1594 * device type (2x6 or 3x6) and needs to be updated based 1595 * on which subslice is disabled especially for 2x6 1596 * devices, however it is safe to load default 1597 * configuration of 3x6 device instead of masking off 1598 * corresponding bits because HW ignores bits of a disabled 1599 * subslice and drops down to appropriate config. Please 1600 * see render_state_setup() in i915_gem_render_state.c for 1601 * possible configurations, to avoid duplication they are 1602 * not shown here again. 1603 */ 1604 *batch++ = GEN9_MEDIA_POOL_STATE; 1605 *batch++ = GEN9_MEDIA_POOL_ENABLE; 1606 *batch++ = 0x00777000; 1607 *batch++ = 0; 1608 *batch++ = 0; 1609 *batch++ = 0; 1610 } 1611 1612 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 1613 1614 /* Pad to end of cacheline */ 1615 while ((unsigned long)batch % CACHELINE_BYTES) 1616 *batch++ = MI_NOOP; 1617 1618 return batch; 1619 } 1620 1621 static u32 * 1622 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) 1623 { 1624 int i; 1625 1626 /* 1627 * WaPipeControlBefore3DStateSamplePattern: cnl 1628 * 1629 * Ensure the engine is idle prior to programming a 1630 * 3DSTATE_SAMPLE_PATTERN during a context restore. 1631 */ 1632 batch = gen8_emit_pipe_control(batch, 1633 PIPE_CONTROL_CS_STALL, 1634 0); 1635 /* 1636 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for 1637 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in 1638 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is 1639 * confusing. Since gen8_emit_pipe_control() already advances the 1640 * batch by 6 dwords, we advance the other 10 here, completing a 1641 * cacheline. It's not clear if the workaround requires this padding 1642 * before other commands, or if it's just the regular padding we would 1643 * already have for the workaround bb, so leave it here for now. 1644 */ 1645 for (i = 0; i < 10; i++) 1646 *batch++ = MI_NOOP; 1647 1648 /* Pad to end of cacheline */ 1649 while ((unsigned long)batch % CACHELINE_BYTES) 1650 *batch++ = MI_NOOP; 1651 1652 return batch; 1653 } 1654 1655 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE) 1656 1657 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) 1658 { 1659 struct drm_i915_gem_object *obj; 1660 struct i915_vma *vma; 1661 int err; 1662 1663 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE); 1664 if (IS_ERR(obj)) 1665 return PTR_ERR(obj); 1666 1667 vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL); 1668 if (IS_ERR(vma)) { 1669 err = PTR_ERR(vma); 1670 goto err; 1671 } 1672 1673 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); 1674 if (err) 1675 goto err; 1676 1677 engine->wa_ctx.vma = vma; 1678 return 0; 1679 1680 err: 1681 i915_gem_object_put(obj); 1682 return err; 1683 } 1684 1685 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine) 1686 { 1687 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); 1688 } 1689 1690 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch); 1691 1692 static int intel_init_workaround_bb(struct intel_engine_cs *engine) 1693 { 1694 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; 1695 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx, 1696 &wa_ctx->per_ctx }; 1697 wa_bb_func_t wa_bb_fn[2]; 1698 struct page *page; 1699 void *batch, *batch_ptr; 1700 unsigned int i; 1701 int ret; 1702 1703 if (engine->class != RENDER_CLASS) 1704 return 0; 1705 1706 switch (INTEL_GEN(engine->i915)) { 1707 case 11: 1708 return 0; 1709 case 10: 1710 wa_bb_fn[0] = gen10_init_indirectctx_bb; 1711 wa_bb_fn[1] = NULL; 1712 break; 1713 case 9: 1714 wa_bb_fn[0] = gen9_init_indirectctx_bb; 1715 wa_bb_fn[1] = NULL; 1716 break; 1717 case 8: 1718 wa_bb_fn[0] = gen8_init_indirectctx_bb; 1719 wa_bb_fn[1] = NULL; 1720 break; 1721 default: 1722 MISSING_CASE(INTEL_GEN(engine->i915)); 1723 return 0; 1724 } 1725 1726 ret = lrc_setup_wa_ctx(engine); 1727 if (ret) { 1728 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); 1729 return ret; 1730 } 1731 1732 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); 1733 batch = batch_ptr = kmap_atomic(page); 1734 1735 /* 1736 * Emit the two workaround batch buffers, recording the offset from the 1737 * start of the workaround batch buffer object for each and their 1738 * respective sizes. 1739 */ 1740 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) { 1741 wa_bb[i]->offset = batch_ptr - batch; 1742 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, 1743 CACHELINE_BYTES))) { 1744 ret = -EINVAL; 1745 break; 1746 } 1747 if (wa_bb_fn[i]) 1748 batch_ptr = wa_bb_fn[i](engine, batch_ptr); 1749 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset); 1750 } 1751 1752 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE); 1753 1754 kunmap_atomic(batch); 1755 if (ret) 1756 lrc_destroy_wa_ctx(engine); 1757 1758 return ret; 1759 } 1760 1761 static void enable_execlists(struct intel_engine_cs *engine) 1762 { 1763 struct drm_i915_private *dev_priv = engine->i915; 1764 1765 intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */ 1766 1767 if (INTEL_GEN(dev_priv) >= 11) 1768 I915_WRITE(RING_MODE_GEN7(engine), 1769 _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); 1770 else 1771 I915_WRITE(RING_MODE_GEN7(engine), 1772 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); 1773 1774 I915_WRITE(RING_MI_MODE(engine->mmio_base), 1775 _MASKED_BIT_DISABLE(STOP_RING)); 1776 1777 I915_WRITE(RING_HWS_PGA(engine->mmio_base), 1778 i915_ggtt_offset(engine->status_page.vma)); 1779 POSTING_READ(RING_HWS_PGA(engine->mmio_base)); 1780 } 1781 1782 static bool unexpected_starting_state(struct intel_engine_cs *engine) 1783 { 1784 struct drm_i915_private *dev_priv = engine->i915; 1785 bool unexpected = false; 1786 1787 if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) { 1788 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n"); 1789 unexpected = true; 1790 } 1791 1792 return unexpected; 1793 } 1794 1795 static int execlists_resume(struct intel_engine_cs *engine) 1796 { 1797 intel_engine_apply_workarounds(engine); 1798 intel_engine_apply_whitelist(engine); 1799 1800 intel_mocs_init_engine(engine); 1801 1802 intel_engine_reset_breadcrumbs(engine); 1803 1804 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) { 1805 struct drm_printer p = drm_debug_printer(__func__); 1806 1807 intel_engine_dump(engine, &p, NULL); 1808 } 1809 1810 enable_execlists(engine); 1811 1812 return 0; 1813 } 1814 1815 static void execlists_reset_prepare(struct intel_engine_cs *engine) 1816 { 1817 struct intel_engine_execlists * const execlists = &engine->execlists; 1818 unsigned long flags; 1819 1820 GEM_TRACE("%s: depth<-%d\n", engine->name, 1821 atomic_read(&execlists->tasklet.count)); 1822 1823 /* 1824 * Prevent request submission to the hardware until we have 1825 * completed the reset in i915_gem_reset_finish(). If a request 1826 * is completed by one engine, it may then queue a request 1827 * to a second via its execlists->tasklet *just* as we are 1828 * calling engine->resume() and also writing the ELSP. 1829 * Turning off the execlists->tasklet until the reset is over 1830 * prevents the race. 1831 */ 1832 __tasklet_disable_sync_once(&execlists->tasklet); 1833 GEM_BUG_ON(!reset_in_progress(execlists)); 1834 1835 intel_engine_stop_cs(engine); 1836 1837 /* And flush any current direct submission. */ 1838 spin_lock_irqsave(&engine->timeline.lock, flags); 1839 spin_unlock_irqrestore(&engine->timeline.lock, flags); 1840 } 1841 1842 static bool lrc_regs_ok(const struct i915_request *rq) 1843 { 1844 const struct intel_ring *ring = rq->ring; 1845 const u32 *regs = rq->hw_context->lrc_reg_state; 1846 1847 /* Quick spot check for the common signs of context corruption */ 1848 1849 if (regs[CTX_RING_BUFFER_CONTROL + 1] != 1850 (RING_CTL_SIZE(ring->size) | RING_VALID)) 1851 return false; 1852 1853 if (regs[CTX_RING_BUFFER_START + 1] != i915_ggtt_offset(ring->vma)) 1854 return false; 1855 1856 return true; 1857 } 1858 1859 static void reset_csb_pointers(struct intel_engine_execlists *execlists) 1860 { 1861 const unsigned int reset_value = execlists->csb_size - 1; 1862 1863 /* 1864 * After a reset, the HW starts writing into CSB entry [0]. We 1865 * therefore have to set our HEAD pointer back one entry so that 1866 * the *first* entry we check is entry 0. To complicate this further, 1867 * as we don't wait for the first interrupt after reset, we have to 1868 * fake the HW write to point back to the last entry so that our 1869 * inline comparison of our cached head position against the last HW 1870 * write works even before the first interrupt. 1871 */ 1872 execlists->csb_head = reset_value; 1873 WRITE_ONCE(*execlists->csb_write, reset_value); 1874 wmb(); /* Make sure this is visible to HW (paranoia?) */ 1875 1876 invalidate_csb_entries(&execlists->csb_status[0], 1877 &execlists->csb_status[reset_value]); 1878 } 1879 1880 static void __execlists_reset(struct intel_engine_cs *engine, bool stalled) 1881 { 1882 struct intel_engine_execlists * const execlists = &engine->execlists; 1883 struct intel_context *ce; 1884 struct i915_request *rq; 1885 u32 *regs; 1886 1887 process_csb(engine); /* drain preemption events */ 1888 1889 /* Following the reset, we need to reload the CSB read/write pointers */ 1890 reset_csb_pointers(&engine->execlists); 1891 1892 /* 1893 * Save the currently executing context, even if we completed 1894 * its request, it was still running at the time of the 1895 * reset and will have been clobbered. 1896 */ 1897 if (!port_isset(execlists->port)) 1898 goto out_clear; 1899 1900 ce = port_request(execlists->port)->hw_context; 1901 1902 /* 1903 * Catch up with any missed context-switch interrupts. 1904 * 1905 * Ideally we would just read the remaining CSB entries now that we 1906 * know the gpu is idle. However, the CSB registers are sometimes^W 1907 * often trashed across a GPU reset! Instead we have to rely on 1908 * guessing the missed context-switch events by looking at what 1909 * requests were completed. 1910 */ 1911 execlists_cancel_port_requests(execlists); 1912 1913 /* Push back any incomplete requests for replay after the reset. */ 1914 rq = __unwind_incomplete_requests(engine, 0); 1915 if (!rq) 1916 goto out_replay; 1917 1918 if (rq->hw_context != ce) { /* caught just before a CS event */ 1919 rq = NULL; 1920 goto out_replay; 1921 } 1922 1923 /* 1924 * If this request hasn't started yet, e.g. it is waiting on a 1925 * semaphore, we need to avoid skipping the request or else we 1926 * break the signaling chain. However, if the context is corrupt 1927 * the request will not restart and we will be stuck with a wedged 1928 * device. It is quite often the case that if we issue a reset 1929 * while the GPU is loading the context image, that the context 1930 * image becomes corrupt. 1931 * 1932 * Otherwise, if we have not started yet, the request should replay 1933 * perfectly and we do not need to flag the result as being erroneous. 1934 */ 1935 if (!i915_request_started(rq) && lrc_regs_ok(rq)) 1936 goto out_replay; 1937 1938 /* 1939 * If the request was innocent, we leave the request in the ELSP 1940 * and will try to replay it on restarting. The context image may 1941 * have been corrupted by the reset, in which case we may have 1942 * to service a new GPU hang, but more likely we can continue on 1943 * without impact. 1944 * 1945 * If the request was guilty, we presume the context is corrupt 1946 * and have to at least restore the RING register in the context 1947 * image back to the expected values to skip over the guilty request. 1948 */ 1949 i915_reset_request(rq, stalled); 1950 if (!stalled && lrc_regs_ok(rq)) 1951 goto out_replay; 1952 1953 /* 1954 * We want a simple context + ring to execute the breadcrumb update. 1955 * We cannot rely on the context being intact across the GPU hang, 1956 * so clear it and rebuild just what we need for the breadcrumb. 1957 * All pending requests for this context will be zapped, and any 1958 * future request will be after userspace has had the opportunity 1959 * to recreate its own state. 1960 */ 1961 regs = ce->lrc_reg_state; 1962 if (engine->pinned_default_state) { 1963 memcpy(regs, /* skip restoring the vanilla PPHWSP */ 1964 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE, 1965 engine->context_size - PAGE_SIZE); 1966 } 1967 execlists_init_reg_state(regs, ce, engine, ce->ring); 1968 1969 /* Rerun the request; its payload has been neutered (if guilty). */ 1970 out_replay: 1971 ce->ring->head = 1972 rq ? intel_ring_wrap(ce->ring, rq->head) : ce->ring->tail; 1973 intel_ring_update_space(ce->ring); 1974 __execlists_update_reg_state(ce, engine); 1975 1976 out_clear: 1977 execlists_clear_all_active(execlists); 1978 } 1979 1980 static void execlists_reset(struct intel_engine_cs *engine, bool stalled) 1981 { 1982 unsigned long flags; 1983 1984 GEM_TRACE("%s\n", engine->name); 1985 1986 spin_lock_irqsave(&engine->timeline.lock, flags); 1987 1988 __execlists_reset(engine, stalled); 1989 1990 spin_unlock_irqrestore(&engine->timeline.lock, flags); 1991 } 1992 1993 static void nop_submission_tasklet(unsigned long data) 1994 { 1995 /* The driver is wedged; don't process any more events. */ 1996 } 1997 1998 static void execlists_cancel_requests(struct intel_engine_cs *engine) 1999 { 2000 struct intel_engine_execlists * const execlists = &engine->execlists; 2001 struct i915_request *rq, *rn; 2002 struct rb_node *rb; 2003 unsigned long flags; 2004 2005 GEM_TRACE("%s\n", engine->name); 2006 2007 /* 2008 * Before we call engine->cancel_requests(), we should have exclusive 2009 * access to the submission state. This is arranged for us by the 2010 * caller disabling the interrupt generation, the tasklet and other 2011 * threads that may then access the same state, giving us a free hand 2012 * to reset state. However, we still need to let lockdep be aware that 2013 * we know this state may be accessed in hardirq context, so we 2014 * disable the irq around this manipulation and we want to keep 2015 * the spinlock focused on its duties and not accidentally conflate 2016 * coverage to the submission's irq state. (Similarly, although we 2017 * shouldn't need to disable irq around the manipulation of the 2018 * submission's irq state, we also wish to remind ourselves that 2019 * it is irq state.) 2020 */ 2021 spin_lock_irqsave(&engine->timeline.lock, flags); 2022 2023 __execlists_reset(engine, true); 2024 2025 /* Mark all executing requests as skipped. */ 2026 list_for_each_entry(rq, &engine->timeline.requests, link) { 2027 if (!i915_request_signaled(rq)) 2028 dma_fence_set_error(&rq->fence, -EIO); 2029 2030 i915_request_mark_complete(rq); 2031 } 2032 2033 /* Flush the queued requests to the timeline list (for retiring). */ 2034 while ((rb = rb_first_cached(&execlists->queue))) { 2035 struct i915_priolist *p = to_priolist(rb); 2036 int i; 2037 2038 priolist_for_each_request_consume(rq, rn, p, i) { 2039 list_del_init(&rq->sched.link); 2040 __i915_request_submit(rq); 2041 dma_fence_set_error(&rq->fence, -EIO); 2042 i915_request_mark_complete(rq); 2043 } 2044 2045 rb_erase_cached(&p->node, &execlists->queue); 2046 i915_priolist_free(p); 2047 } 2048 2049 /* Remaining _unready_ requests will be nop'ed when submitted */ 2050 2051 execlists->queue_priority_hint = INT_MIN; 2052 execlists->queue = RB_ROOT_CACHED; 2053 GEM_BUG_ON(port_isset(execlists->port)); 2054 2055 GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet)); 2056 execlists->tasklet.func = nop_submission_tasklet; 2057 2058 spin_unlock_irqrestore(&engine->timeline.lock, flags); 2059 } 2060 2061 static void execlists_reset_finish(struct intel_engine_cs *engine) 2062 { 2063 struct intel_engine_execlists * const execlists = &engine->execlists; 2064 2065 /* 2066 * After a GPU reset, we may have requests to replay. Do so now while 2067 * we still have the forcewake to be sure that the GPU is not allowed 2068 * to sleep before we restart and reload a context. 2069 */ 2070 GEM_BUG_ON(!reset_in_progress(execlists)); 2071 if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) 2072 execlists->tasklet.func(execlists->tasklet.data); 2073 2074 if (__tasklet_enable(&execlists->tasklet)) 2075 /* And kick in case we missed a new request submission. */ 2076 tasklet_hi_schedule(&execlists->tasklet); 2077 GEM_TRACE("%s: depth->%d\n", engine->name, 2078 atomic_read(&execlists->tasklet.count)); 2079 } 2080 2081 static int gen8_emit_bb_start(struct i915_request *rq, 2082 u64 offset, u32 len, 2083 const unsigned int flags) 2084 { 2085 u32 *cs; 2086 2087 cs = intel_ring_begin(rq, 4); 2088 if (IS_ERR(cs)) 2089 return PTR_ERR(cs); 2090 2091 /* 2092 * WaDisableCtxRestoreArbitration:bdw,chv 2093 * 2094 * We don't need to perform MI_ARB_ENABLE as often as we do (in 2095 * particular all the gen that do not need the w/a at all!), if we 2096 * took care to make sure that on every switch into this context 2097 * (both ordinary and for preemption) that arbitrartion was enabled 2098 * we would be fine. However, for gen8 there is another w/a that 2099 * requires us to not preempt inside GPGPU execution, so we keep 2100 * arbitration disabled for gen8 batches. Arbitration will be 2101 * re-enabled before we close the request 2102 * (engine->emit_fini_breadcrumb). 2103 */ 2104 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 2105 2106 /* FIXME(BDW+): Address space and security selectors. */ 2107 *cs++ = MI_BATCH_BUFFER_START_GEN8 | 2108 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); 2109 *cs++ = lower_32_bits(offset); 2110 *cs++ = upper_32_bits(offset); 2111 2112 intel_ring_advance(rq, cs); 2113 2114 return 0; 2115 } 2116 2117 static int gen9_emit_bb_start(struct i915_request *rq, 2118 u64 offset, u32 len, 2119 const unsigned int flags) 2120 { 2121 u32 *cs; 2122 2123 cs = intel_ring_begin(rq, 6); 2124 if (IS_ERR(cs)) 2125 return PTR_ERR(cs); 2126 2127 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 2128 2129 *cs++ = MI_BATCH_BUFFER_START_GEN8 | 2130 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); 2131 *cs++ = lower_32_bits(offset); 2132 *cs++ = upper_32_bits(offset); 2133 2134 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 2135 *cs++ = MI_NOOP; 2136 2137 intel_ring_advance(rq, cs); 2138 2139 return 0; 2140 } 2141 2142 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) 2143 { 2144 ENGINE_WRITE(engine, RING_IMR, 2145 ~(engine->irq_enable_mask | engine->irq_keep_mask)); 2146 ENGINE_POSTING_READ(engine, RING_IMR); 2147 } 2148 2149 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) 2150 { 2151 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); 2152 } 2153 2154 static int gen8_emit_flush(struct i915_request *request, u32 mode) 2155 { 2156 u32 cmd, *cs; 2157 2158 cs = intel_ring_begin(request, 4); 2159 if (IS_ERR(cs)) 2160 return PTR_ERR(cs); 2161 2162 cmd = MI_FLUSH_DW + 1; 2163 2164 /* We always require a command barrier so that subsequent 2165 * commands, such as breadcrumb interrupts, are strictly ordered 2166 * wrt the contents of the write cache being flushed to memory 2167 * (and thus being coherent from the CPU). 2168 */ 2169 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 2170 2171 if (mode & EMIT_INVALIDATE) { 2172 cmd |= MI_INVALIDATE_TLB; 2173 if (request->engine->class == VIDEO_DECODE_CLASS) 2174 cmd |= MI_INVALIDATE_BSD; 2175 } 2176 2177 *cs++ = cmd; 2178 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; 2179 *cs++ = 0; /* upper addr */ 2180 *cs++ = 0; /* value */ 2181 intel_ring_advance(request, cs); 2182 2183 return 0; 2184 } 2185 2186 static int gen8_emit_flush_render(struct i915_request *request, 2187 u32 mode) 2188 { 2189 struct intel_engine_cs *engine = request->engine; 2190 u32 scratch_addr = 2191 i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES; 2192 bool vf_flush_wa = false, dc_flush_wa = false; 2193 u32 *cs, flags = 0; 2194 int len; 2195 2196 flags |= PIPE_CONTROL_CS_STALL; 2197 2198 if (mode & EMIT_FLUSH) { 2199 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 2200 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 2201 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; 2202 flags |= PIPE_CONTROL_FLUSH_ENABLE; 2203 } 2204 2205 if (mode & EMIT_INVALIDATE) { 2206 flags |= PIPE_CONTROL_TLB_INVALIDATE; 2207 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 2208 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 2209 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 2210 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 2211 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 2212 flags |= PIPE_CONTROL_QW_WRITE; 2213 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; 2214 2215 /* 2216 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL 2217 * pipe control. 2218 */ 2219 if (IS_GEN(request->i915, 9)) 2220 vf_flush_wa = true; 2221 2222 /* WaForGAMHang:kbl */ 2223 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) 2224 dc_flush_wa = true; 2225 } 2226 2227 len = 6; 2228 2229 if (vf_flush_wa) 2230 len += 6; 2231 2232 if (dc_flush_wa) 2233 len += 12; 2234 2235 cs = intel_ring_begin(request, len); 2236 if (IS_ERR(cs)) 2237 return PTR_ERR(cs); 2238 2239 if (vf_flush_wa) 2240 cs = gen8_emit_pipe_control(cs, 0, 0); 2241 2242 if (dc_flush_wa) 2243 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, 2244 0); 2245 2246 cs = gen8_emit_pipe_control(cs, flags, scratch_addr); 2247 2248 if (dc_flush_wa) 2249 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); 2250 2251 intel_ring_advance(request, cs); 2252 2253 return 0; 2254 } 2255 2256 /* 2257 * Reserve space for 2 NOOPs at the end of each request to be 2258 * used as a workaround for not being allowed to do lite 2259 * restore with HEAD==TAIL (WaIdleLiteRestore). 2260 */ 2261 static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs) 2262 { 2263 /* Ensure there's always at least one preemption point per-request. */ 2264 *cs++ = MI_ARB_CHECK; 2265 *cs++ = MI_NOOP; 2266 request->wa_tail = intel_ring_offset(request, cs); 2267 2268 return cs; 2269 } 2270 2271 static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs) 2272 { 2273 cs = gen8_emit_ggtt_write(cs, 2274 request->fence.seqno, 2275 request->timeline->hwsp_offset, 2276 0); 2277 2278 cs = gen8_emit_ggtt_write(cs, 2279 intel_engine_next_hangcheck_seqno(request->engine), 2280 I915_GEM_HWS_HANGCHECK_ADDR, 2281 MI_FLUSH_DW_STORE_INDEX); 2282 2283 2284 *cs++ = MI_USER_INTERRUPT; 2285 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 2286 2287 request->tail = intel_ring_offset(request, cs); 2288 assert_ring_tail_valid(request->ring, request->tail); 2289 2290 return gen8_emit_wa_tail(request, cs); 2291 } 2292 2293 static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) 2294 { 2295 cs = gen8_emit_ggtt_write_rcs(cs, 2296 request->fence.seqno, 2297 request->timeline->hwsp_offset, 2298 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | 2299 PIPE_CONTROL_DEPTH_CACHE_FLUSH | 2300 PIPE_CONTROL_DC_FLUSH_ENABLE | 2301 PIPE_CONTROL_FLUSH_ENABLE | 2302 PIPE_CONTROL_CS_STALL); 2303 2304 cs = gen8_emit_ggtt_write_rcs(cs, 2305 intel_engine_next_hangcheck_seqno(request->engine), 2306 I915_GEM_HWS_HANGCHECK_ADDR, 2307 PIPE_CONTROL_STORE_DATA_INDEX); 2308 2309 *cs++ = MI_USER_INTERRUPT; 2310 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 2311 2312 request->tail = intel_ring_offset(request, cs); 2313 assert_ring_tail_valid(request->ring, request->tail); 2314 2315 return gen8_emit_wa_tail(request, cs); 2316 } 2317 2318 static int gen8_init_rcs_context(struct i915_request *rq) 2319 { 2320 int ret; 2321 2322 ret = intel_engine_emit_ctx_wa(rq); 2323 if (ret) 2324 return ret; 2325 2326 ret = intel_rcs_context_init_mocs(rq); 2327 /* 2328 * Failing to program the MOCS is non-fatal.The system will not 2329 * run at peak performance. So generate an error and carry on. 2330 */ 2331 if (ret) 2332 DRM_ERROR("MOCS failed to program: expect performance issues.\n"); 2333 2334 return i915_gem_render_state_emit(rq); 2335 } 2336 2337 static void execlists_park(struct intel_engine_cs *engine) 2338 { 2339 intel_engine_park(engine); 2340 } 2341 2342 void intel_execlists_set_default_submission(struct intel_engine_cs *engine) 2343 { 2344 engine->submit_request = execlists_submit_request; 2345 engine->cancel_requests = execlists_cancel_requests; 2346 engine->schedule = i915_schedule; 2347 engine->execlists.tasklet.func = execlists_submission_tasklet; 2348 2349 engine->reset.prepare = execlists_reset_prepare; 2350 engine->reset.reset = execlists_reset; 2351 engine->reset.finish = execlists_reset_finish; 2352 2353 engine->park = execlists_park; 2354 engine->unpark = NULL; 2355 2356 engine->flags |= I915_ENGINE_SUPPORTS_STATS; 2357 if (!intel_vgpu_active(engine->i915)) 2358 engine->flags |= I915_ENGINE_HAS_SEMAPHORES; 2359 if (engine->preempt_context && 2360 HAS_LOGICAL_RING_PREEMPTION(engine->i915)) 2361 engine->flags |= I915_ENGINE_HAS_PREEMPTION; 2362 } 2363 2364 static void execlists_destroy(struct intel_engine_cs *engine) 2365 { 2366 intel_engine_cleanup_common(engine); 2367 lrc_destroy_wa_ctx(engine); 2368 kfree(engine); 2369 } 2370 2371 static void 2372 logical_ring_default_vfuncs(struct intel_engine_cs *engine) 2373 { 2374 /* Default vfuncs which can be overriden by each engine. */ 2375 2376 engine->destroy = execlists_destroy; 2377 engine->resume = execlists_resume; 2378 2379 engine->reset.prepare = execlists_reset_prepare; 2380 engine->reset.reset = execlists_reset; 2381 engine->reset.finish = execlists_reset_finish; 2382 2383 engine->cops = &execlists_context_ops; 2384 engine->request_alloc = execlists_request_alloc; 2385 2386 engine->emit_flush = gen8_emit_flush; 2387 engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb; 2388 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb; 2389 2390 engine->set_default_submission = intel_execlists_set_default_submission; 2391 2392 if (INTEL_GEN(engine->i915) < 11) { 2393 engine->irq_enable = gen8_logical_ring_enable_irq; 2394 engine->irq_disable = gen8_logical_ring_disable_irq; 2395 } else { 2396 /* 2397 * TODO: On Gen11 interrupt masks need to be clear 2398 * to allow C6 entry. Keep interrupts enabled at 2399 * and take the hit of generating extra interrupts 2400 * until a more refined solution exists. 2401 */ 2402 } 2403 if (IS_GEN(engine->i915, 8)) 2404 engine->emit_bb_start = gen8_emit_bb_start; 2405 else 2406 engine->emit_bb_start = gen9_emit_bb_start; 2407 } 2408 2409 static inline void 2410 logical_ring_default_irqs(struct intel_engine_cs *engine) 2411 { 2412 unsigned int shift = 0; 2413 2414 if (INTEL_GEN(engine->i915) < 11) { 2415 const u8 irq_shifts[] = { 2416 [RCS0] = GEN8_RCS_IRQ_SHIFT, 2417 [BCS0] = GEN8_BCS_IRQ_SHIFT, 2418 [VCS0] = GEN8_VCS0_IRQ_SHIFT, 2419 [VCS1] = GEN8_VCS1_IRQ_SHIFT, 2420 [VECS0] = GEN8_VECS_IRQ_SHIFT, 2421 }; 2422 2423 shift = irq_shifts[engine->id]; 2424 } 2425 2426 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; 2427 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; 2428 } 2429 2430 int intel_execlists_submission_setup(struct intel_engine_cs *engine) 2431 { 2432 /* Intentionally left blank. */ 2433 engine->buffer = NULL; 2434 2435 tasklet_init(&engine->execlists.tasklet, 2436 execlists_submission_tasklet, (unsigned long)engine); 2437 2438 logical_ring_default_vfuncs(engine); 2439 logical_ring_default_irqs(engine); 2440 2441 if (engine->class == RENDER_CLASS) { 2442 engine->init_context = gen8_init_rcs_context; 2443 engine->emit_flush = gen8_emit_flush_render; 2444 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs; 2445 } 2446 2447 return 0; 2448 } 2449 2450 int intel_execlists_submission_init(struct intel_engine_cs *engine) 2451 { 2452 struct drm_i915_private *i915 = engine->i915; 2453 struct intel_engine_execlists * const execlists = &engine->execlists; 2454 u32 base = engine->mmio_base; 2455 int ret; 2456 2457 ret = intel_engine_init_common(engine); 2458 if (ret) 2459 return ret; 2460 2461 intel_engine_init_workarounds(engine); 2462 intel_engine_init_whitelist(engine); 2463 2464 if (intel_init_workaround_bb(engine)) 2465 /* 2466 * We continue even if we fail to initialize WA batch 2467 * because we only expect rare glitches but nothing 2468 * critical to prevent us from using GPU 2469 */ 2470 DRM_ERROR("WA batch buffer initialization failed\n"); 2471 2472 if (HAS_LOGICAL_RING_ELSQ(i915)) { 2473 execlists->submit_reg = i915->uncore.regs + 2474 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base)); 2475 execlists->ctrl_reg = i915->uncore.regs + 2476 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base)); 2477 } else { 2478 execlists->submit_reg = i915->uncore.regs + 2479 i915_mmio_reg_offset(RING_ELSP(base)); 2480 } 2481 2482 execlists->preempt_complete_status = ~0u; 2483 if (engine->preempt_context) 2484 execlists->preempt_complete_status = 2485 upper_32_bits(engine->preempt_context->lrc_desc); 2486 2487 execlists->csb_status = 2488 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; 2489 2490 execlists->csb_write = 2491 &engine->status_page.addr[intel_hws_csb_write_index(i915)]; 2492 2493 if (INTEL_GEN(engine->i915) < 11) 2494 execlists->csb_size = GEN8_CSB_ENTRIES; 2495 else 2496 execlists->csb_size = GEN11_CSB_ENTRIES; 2497 2498 reset_csb_pointers(execlists); 2499 2500 return 0; 2501 } 2502 2503 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) 2504 { 2505 u32 indirect_ctx_offset; 2506 2507 switch (INTEL_GEN(engine->i915)) { 2508 default: 2509 MISSING_CASE(INTEL_GEN(engine->i915)); 2510 /* fall through */ 2511 case 11: 2512 indirect_ctx_offset = 2513 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2514 break; 2515 case 10: 2516 indirect_ctx_offset = 2517 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2518 break; 2519 case 9: 2520 indirect_ctx_offset = 2521 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2522 break; 2523 case 8: 2524 indirect_ctx_offset = 2525 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2526 break; 2527 } 2528 2529 return indirect_ctx_offset; 2530 } 2531 2532 static void execlists_init_reg_state(u32 *regs, 2533 struct intel_context *ce, 2534 struct intel_engine_cs *engine, 2535 struct intel_ring *ring) 2536 { 2537 struct i915_hw_ppgtt *ppgtt = ce->gem_context->ppgtt; 2538 bool rcs = engine->class == RENDER_CLASS; 2539 u32 base = engine->mmio_base; 2540 2541 /* A context is actually a big batch buffer with several 2542 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The 2543 * values we are setting here are only for the first context restore: 2544 * on a subsequent save, the GPU will recreate this batchbuffer with new 2545 * values (including all the missing MI_LOAD_REGISTER_IMM commands that 2546 * we are not initializing here). 2547 */ 2548 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | 2549 MI_LRI_FORCE_POSTED; 2550 2551 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base), 2552 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) | 2553 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH)); 2554 if (INTEL_GEN(engine->i915) < 11) { 2555 regs[CTX_CONTEXT_CONTROL + 1] |= 2556 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT | 2557 CTX_CTRL_RS_CTX_ENABLE); 2558 } 2559 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0); 2560 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0); 2561 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); 2562 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), 2563 RING_CTL_SIZE(ring->size) | RING_VALID); 2564 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0); 2565 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0); 2566 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT); 2567 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0); 2568 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0); 2569 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0); 2570 if (rcs) { 2571 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; 2572 2573 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0); 2574 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET, 2575 RING_INDIRECT_CTX_OFFSET(base), 0); 2576 if (wa_ctx->indirect_ctx.size) { 2577 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); 2578 2579 regs[CTX_RCS_INDIRECT_CTX + 1] = 2580 (ggtt_offset + wa_ctx->indirect_ctx.offset) | 2581 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); 2582 2583 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = 2584 intel_lr_indirect_ctx_offset(engine) << 6; 2585 } 2586 2587 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0); 2588 if (wa_ctx->per_ctx.size) { 2589 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); 2590 2591 regs[CTX_BB_PER_CTX_PTR + 1] = 2592 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; 2593 } 2594 } 2595 2596 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; 2597 2598 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); 2599 /* PDP values well be assigned later if needed */ 2600 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0); 2601 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0); 2602 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(base, 2), 0); 2603 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(base, 2), 0); 2604 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(base, 1), 0); 2605 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(base, 1), 0); 2606 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(base, 0), 0); 2607 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(base, 0), 0); 2608 2609 if (i915_vm_is_4lvl(&ppgtt->vm)) { 2610 /* 64b PPGTT (48bit canonical) 2611 * PDP0_DESCRIPTOR contains the base address to PML4 and 2612 * other PDP Descriptors are ignored. 2613 */ 2614 ASSIGN_CTX_PML4(ppgtt, regs); 2615 } else { 2616 ASSIGN_CTX_PDP(ppgtt, regs, 3); 2617 ASSIGN_CTX_PDP(ppgtt, regs, 2); 2618 ASSIGN_CTX_PDP(ppgtt, regs, 1); 2619 ASSIGN_CTX_PDP(ppgtt, regs, 0); 2620 } 2621 2622 if (rcs) { 2623 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); 2624 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0); 2625 2626 i915_oa_init_reg_state(engine, ce, regs); 2627 } 2628 2629 regs[CTX_END] = MI_BATCH_BUFFER_END; 2630 if (INTEL_GEN(engine->i915) >= 10) 2631 regs[CTX_END] |= BIT(0); 2632 } 2633 2634 static int 2635 populate_lr_context(struct intel_context *ce, 2636 struct drm_i915_gem_object *ctx_obj, 2637 struct intel_engine_cs *engine, 2638 struct intel_ring *ring) 2639 { 2640 void *vaddr; 2641 u32 *regs; 2642 int ret; 2643 2644 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); 2645 if (IS_ERR(vaddr)) { 2646 ret = PTR_ERR(vaddr); 2647 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); 2648 return ret; 2649 } 2650 2651 if (engine->default_state) { 2652 /* 2653 * We only want to copy over the template context state; 2654 * skipping over the headers reserved for GuC communication, 2655 * leaving those as zero. 2656 */ 2657 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE; 2658 void *defaults; 2659 2660 defaults = i915_gem_object_pin_map(engine->default_state, 2661 I915_MAP_WB); 2662 if (IS_ERR(defaults)) { 2663 ret = PTR_ERR(defaults); 2664 goto err_unpin_ctx; 2665 } 2666 2667 memcpy(vaddr + start, defaults + start, engine->context_size); 2668 i915_gem_object_unpin_map(engine->default_state); 2669 } 2670 2671 /* The second page of the context object contains some fields which must 2672 * be set up prior to the first execution. */ 2673 regs = vaddr + LRC_STATE_PN * PAGE_SIZE; 2674 execlists_init_reg_state(regs, ce, engine, ring); 2675 if (!engine->default_state) 2676 regs[CTX_CONTEXT_CONTROL + 1] |= 2677 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 2678 if (ce->gem_context == engine->i915->preempt_context && 2679 INTEL_GEN(engine->i915) < 11) 2680 regs[CTX_CONTEXT_CONTROL + 1] |= 2681 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | 2682 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT); 2683 2684 ret = 0; 2685 err_unpin_ctx: 2686 __i915_gem_object_flush_map(ctx_obj, 2687 LRC_HEADER_PAGES * PAGE_SIZE, 2688 engine->context_size); 2689 i915_gem_object_unpin_map(ctx_obj); 2690 return ret; 2691 } 2692 2693 static struct i915_timeline *get_timeline(struct i915_gem_context *ctx) 2694 { 2695 if (ctx->timeline) 2696 return i915_timeline_get(ctx->timeline); 2697 else 2698 return i915_timeline_create(ctx->i915, NULL); 2699 } 2700 2701 static int execlists_context_deferred_alloc(struct intel_context *ce, 2702 struct intel_engine_cs *engine) 2703 { 2704 struct drm_i915_gem_object *ctx_obj; 2705 struct i915_vma *vma; 2706 u32 context_size; 2707 struct intel_ring *ring; 2708 struct i915_timeline *timeline; 2709 int ret; 2710 2711 if (ce->state) 2712 return 0; 2713 2714 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); 2715 2716 /* 2717 * Before the actual start of the context image, we insert a few pages 2718 * for our own use and for sharing with the GuC. 2719 */ 2720 context_size += LRC_HEADER_PAGES * PAGE_SIZE; 2721 2722 ctx_obj = i915_gem_object_create(engine->i915, context_size); 2723 if (IS_ERR(ctx_obj)) 2724 return PTR_ERR(ctx_obj); 2725 2726 vma = i915_vma_instance(ctx_obj, &engine->i915->ggtt.vm, NULL); 2727 if (IS_ERR(vma)) { 2728 ret = PTR_ERR(vma); 2729 goto error_deref_obj; 2730 } 2731 2732 timeline = get_timeline(ce->gem_context); 2733 if (IS_ERR(timeline)) { 2734 ret = PTR_ERR(timeline); 2735 goto error_deref_obj; 2736 } 2737 2738 ring = intel_engine_create_ring(engine, 2739 timeline, 2740 ce->gem_context->ring_size); 2741 i915_timeline_put(timeline); 2742 if (IS_ERR(ring)) { 2743 ret = PTR_ERR(ring); 2744 goto error_deref_obj; 2745 } 2746 2747 ret = populate_lr_context(ce, ctx_obj, engine, ring); 2748 if (ret) { 2749 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); 2750 goto error_ring_free; 2751 } 2752 2753 ce->ring = ring; 2754 ce->state = vma; 2755 2756 return 0; 2757 2758 error_ring_free: 2759 intel_ring_put(ring); 2760 error_deref_obj: 2761 i915_gem_object_put(ctx_obj); 2762 return ret; 2763 } 2764 2765 void intel_execlists_show_requests(struct intel_engine_cs *engine, 2766 struct drm_printer *m, 2767 void (*show_request)(struct drm_printer *m, 2768 struct i915_request *rq, 2769 const char *prefix), 2770 unsigned int max) 2771 { 2772 const struct intel_engine_execlists *execlists = &engine->execlists; 2773 struct i915_request *rq, *last; 2774 unsigned long flags; 2775 unsigned int count; 2776 struct rb_node *rb; 2777 2778 spin_lock_irqsave(&engine->timeline.lock, flags); 2779 2780 last = NULL; 2781 count = 0; 2782 list_for_each_entry(rq, &engine->timeline.requests, link) { 2783 if (count++ < max - 1) 2784 show_request(m, rq, "\t\tE "); 2785 else 2786 last = rq; 2787 } 2788 if (last) { 2789 if (count > max) { 2790 drm_printf(m, 2791 "\t\t...skipping %d executing requests...\n", 2792 count - max); 2793 } 2794 show_request(m, last, "\t\tE "); 2795 } 2796 2797 last = NULL; 2798 count = 0; 2799 if (execlists->queue_priority_hint != INT_MIN) 2800 drm_printf(m, "\t\tQueue priority hint: %d\n", 2801 execlists->queue_priority_hint); 2802 for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) { 2803 struct i915_priolist *p = rb_entry(rb, typeof(*p), node); 2804 int i; 2805 2806 priolist_for_each_request(rq, p, i) { 2807 if (count++ < max - 1) 2808 show_request(m, rq, "\t\tQ "); 2809 else 2810 last = rq; 2811 } 2812 } 2813 if (last) { 2814 if (count > max) { 2815 drm_printf(m, 2816 "\t\t...skipping %d queued requests...\n", 2817 count - max); 2818 } 2819 show_request(m, last, "\t\tQ "); 2820 } 2821 2822 spin_unlock_irqrestore(&engine->timeline.lock, flags); 2823 } 2824 2825 void intel_lr_context_reset(struct intel_engine_cs *engine, 2826 struct intel_context *ce, 2827 u32 head, 2828 bool scrub) 2829 { 2830 /* 2831 * We want a simple context + ring to execute the breadcrumb update. 2832 * We cannot rely on the context being intact across the GPU hang, 2833 * so clear it and rebuild just what we need for the breadcrumb. 2834 * All pending requests for this context will be zapped, and any 2835 * future request will be after userspace has had the opportunity 2836 * to recreate its own state. 2837 */ 2838 if (scrub) { 2839 u32 *regs = ce->lrc_reg_state; 2840 2841 if (engine->pinned_default_state) { 2842 memcpy(regs, /* skip restoring the vanilla PPHWSP */ 2843 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE, 2844 engine->context_size - PAGE_SIZE); 2845 } 2846 execlists_init_reg_state(regs, ce, engine, ce->ring); 2847 } 2848 2849 /* Rerun the request; its payload has been neutered (if guilty). */ 2850 ce->ring->head = head; 2851 intel_ring_update_space(ce->ring); 2852 2853 __execlists_update_reg_state(ce, engine); 2854 } 2855 2856 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2857 #include "selftest_lrc.c" 2858 #endif 2859