1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * Michel Thierry <michel.thierry@intel.com> 26 * Thomas Daniel <thomas.daniel@intel.com> 27 * Oscar Mateo <oscar.mateo@intel.com> 28 * 29 */ 30 31 /** 32 * DOC: Logical Rings, Logical Ring Contexts and Execlists 33 * 34 * Motivation: 35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". 36 * These expanded contexts enable a number of new abilities, especially 37 * "Execlists" (also implemented in this file). 38 * 39 * One of the main differences with the legacy HW contexts is that logical 40 * ring contexts incorporate many more things to the context's state, like 41 * PDPs or ringbuffer control registers: 42 * 43 * The reason why PDPs are included in the context is straightforward: as 44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs 45 * contained there mean you don't need to do a ppgtt->switch_mm yourself, 46 * instead, the GPU will do it for you on the context switch. 47 * 48 * But, what about the ringbuffer control registers (head, tail, etc..)? 49 * shouldn't we just need a set of those per engine command streamer? This is 50 * where the name "Logical Rings" starts to make sense: by virtualizing the 51 * rings, the engine cs shifts to a new "ring buffer" with every context 52 * switch. When you want to submit a workload to the GPU you: A) choose your 53 * context, B) find its appropriate virtualized ring, C) write commands to it 54 * and then, finally, D) tell the GPU to switch to that context. 55 * 56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch 57 * to a contexts is via a context execution list, ergo "Execlists". 58 * 59 * LRC implementation: 60 * Regarding the creation of contexts, we have: 61 * 62 * - One global default context. 63 * - One local default context for each opened fd. 64 * - One local extra context for each context create ioctl call. 65 * 66 * Now that ringbuffers belong per-context (and not per-engine, like before) 67 * and that contexts are uniquely tied to a given engine (and not reusable, 68 * like before) we need: 69 * 70 * - One ringbuffer per-engine inside each context. 71 * - One backing object per-engine inside each context. 72 * 73 * The global default context starts its life with these new objects fully 74 * allocated and populated. The local default context for each opened fd is 75 * more complex, because we don't know at creation time which engine is going 76 * to use them. To handle this, we have implemented a deferred creation of LR 77 * contexts: 78 * 79 * The local context starts its life as a hollow or blank holder, that only 80 * gets populated for a given engine once we receive an execbuffer. If later 81 * on we receive another execbuffer ioctl for the same context but a different 82 * engine, we allocate/populate a new ringbuffer and context backing object and 83 * so on. 84 * 85 * Finally, regarding local contexts created using the ioctl call: as they are 86 * only allowed with the render ring, we can allocate & populate them right 87 * away (no need to defer anything, at least for now). 88 * 89 * Execlists implementation: 90 * Execlists are the new method by which, on gen8+ hardware, workloads are 91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method). 92 * This method works as follows: 93 * 94 * When a request is committed, its commands (the BB start and any leading or 95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer 96 * for the appropriate context. The tail pointer in the hardware context is not 97 * updated at this time, but instead, kept by the driver in the ringbuffer 98 * structure. A structure representing this request is added to a request queue 99 * for the appropriate engine: this structure contains a copy of the context's 100 * tail after the request was written to the ring buffer and a pointer to the 101 * context itself. 102 * 103 * If the engine's request queue was empty before the request was added, the 104 * queue is processed immediately. Otherwise the queue will be processed during 105 * a context switch interrupt. In any case, elements on the queue will get sent 106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a 107 * globally unique 20-bits submission ID. 108 * 109 * When execution of a request completes, the GPU updates the context status 110 * buffer with a context complete event and generates a context switch interrupt. 111 * During the interrupt handling, the driver examines the events in the buffer: 112 * for each context complete event, if the announced ID matches that on the head 113 * of the request queue, then that request is retired and removed from the queue. 114 * 115 * After processing, if any requests were retired and the queue is not empty 116 * then a new execution list can be submitted. The two requests at the front of 117 * the queue are next to be submitted but since a context may not occur twice in 118 * an execution list, if subsequent requests have the same ID as the first then 119 * the two requests must be combined. This is done simply by discarding requests 120 * at the head of the queue until either only one requests is left (in which case 121 * we use a NULL second context) or the first two requests have unique IDs. 122 * 123 * By always executing the first two requests in the queue the driver ensures 124 * that the GPU is kept as busy as possible. In the case where a single context 125 * completes but a second context is still executing, the request for this second 126 * context will be at the head of the queue when we remove the first one. This 127 * request will then be resubmitted along with a new request for a different context, 128 * which will cause the hardware to continue executing the second request and queue 129 * the new request (the GPU detects the condition of a context getting preempted 130 * with the same context and optimizes the context switch flow by not doing 131 * preemption, but just sampling the new tail pointer). 132 * 133 */ 134 #include <linux/interrupt.h> 135 136 #include "gem/i915_gem_context.h" 137 138 #include "i915_drv.h" 139 #include "i915_gem_render_state.h" 140 #include "i915_vgpu.h" 141 #include "intel_engine_pm.h" 142 #include "intel_lrc_reg.h" 143 #include "intel_mocs.h" 144 #include "intel_reset.h" 145 #include "intel_workarounds.h" 146 147 #define RING_EXECLIST_QFULL (1 << 0x2) 148 #define RING_EXECLIST1_VALID (1 << 0x3) 149 #define RING_EXECLIST0_VALID (1 << 0x4) 150 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) 151 #define RING_EXECLIST1_ACTIVE (1 << 0x11) 152 #define RING_EXECLIST0_ACTIVE (1 << 0x12) 153 154 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) 155 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) 156 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) 157 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) 158 #define GEN8_CTX_STATUS_COMPLETE (1 << 4) 159 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) 160 161 #define GEN8_CTX_STATUS_COMPLETED_MASK \ 162 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED) 163 164 /* Typical size of the average request (2 pipecontrols and a MI_BB) */ 165 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ 166 #define WA_TAIL_DWORDS 2 167 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS) 168 169 struct virtual_engine { 170 struct intel_engine_cs base; 171 struct intel_context context; 172 173 /* 174 * We allow only a single request through the virtual engine at a time 175 * (each request in the timeline waits for the completion fence of 176 * the previous before being submitted). By restricting ourselves to 177 * only submitting a single request, each request is placed on to a 178 * physical to maximise load spreading (by virtue of the late greedy 179 * scheduling -- each real engine takes the next available request 180 * upon idling). 181 */ 182 struct i915_request *request; 183 184 /* 185 * We keep a rbtree of available virtual engines inside each physical 186 * engine, sorted by priority. Here we preallocate the nodes we need 187 * for the virtual engine, indexed by physical_engine->id. 188 */ 189 struct ve_node { 190 struct rb_node rb; 191 int prio; 192 } nodes[I915_NUM_ENGINES]; 193 194 /* 195 * Keep track of bonded pairs -- restrictions upon on our selection 196 * of physical engines any particular request may be submitted to. 197 * If we receive a submit-fence from a master engine, we will only 198 * use one of sibling_mask physical engines. 199 */ 200 struct ve_bond { 201 const struct intel_engine_cs *master; 202 intel_engine_mask_t sibling_mask; 203 } *bonds; 204 unsigned int num_bonds; 205 206 /* And finally, which physical engines this virtual engine maps onto. */ 207 unsigned int num_siblings; 208 struct intel_engine_cs *siblings[0]; 209 }; 210 211 static struct virtual_engine *to_virtual_engine(struct intel_engine_cs *engine) 212 { 213 GEM_BUG_ON(!intel_engine_is_virtual(engine)); 214 return container_of(engine, struct virtual_engine, base); 215 } 216 217 static int execlists_context_deferred_alloc(struct intel_context *ce, 218 struct intel_engine_cs *engine); 219 static void execlists_init_reg_state(u32 *reg_state, 220 struct intel_context *ce, 221 struct intel_engine_cs *engine, 222 struct intel_ring *ring); 223 224 static inline struct i915_priolist *to_priolist(struct rb_node *rb) 225 { 226 return rb_entry(rb, struct i915_priolist, node); 227 } 228 229 static inline int rq_prio(const struct i915_request *rq) 230 { 231 return rq->sched.attr.priority; 232 } 233 234 static int effective_prio(const struct i915_request *rq) 235 { 236 int prio = rq_prio(rq); 237 238 /* 239 * On unwinding the active request, we give it a priority bump 240 * if it has completed waiting on any semaphore. If we know that 241 * the request has already started, we can prevent an unwanted 242 * preempt-to-idle cycle by taking that into account now. 243 */ 244 if (__i915_request_has_started(rq)) 245 prio |= I915_PRIORITY_NOSEMAPHORE; 246 247 /* Restrict mere WAIT boosts from triggering preemption */ 248 return prio | __NO_PREEMPTION; 249 } 250 251 static int queue_prio(const struct intel_engine_execlists *execlists) 252 { 253 struct i915_priolist *p; 254 struct rb_node *rb; 255 256 rb = rb_first_cached(&execlists->queue); 257 if (!rb) 258 return INT_MIN; 259 260 /* 261 * As the priolist[] are inverted, with the highest priority in [0], 262 * we have to flip the index value to become priority. 263 */ 264 p = to_priolist(rb); 265 return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used); 266 } 267 268 static inline bool need_preempt(const struct intel_engine_cs *engine, 269 const struct i915_request *rq, 270 struct rb_node *rb) 271 { 272 int last_prio; 273 274 if (!engine->preempt_context) 275 return false; 276 277 if (i915_request_completed(rq)) 278 return false; 279 280 /* 281 * Check if the current priority hint merits a preemption attempt. 282 * 283 * We record the highest value priority we saw during rescheduling 284 * prior to this dequeue, therefore we know that if it is strictly 285 * less than the current tail of ESLP[0], we do not need to force 286 * a preempt-to-idle cycle. 287 * 288 * However, the priority hint is a mere hint that we may need to 289 * preempt. If that hint is stale or we may be trying to preempt 290 * ourselves, ignore the request. 291 */ 292 last_prio = effective_prio(rq); 293 if (!i915_scheduler_need_preempt(engine->execlists.queue_priority_hint, 294 last_prio)) 295 return false; 296 297 /* 298 * Check against the first request in ELSP[1], it will, thanks to the 299 * power of PI, be the highest priority of that context. 300 */ 301 if (!list_is_last(&rq->sched.link, &engine->active.requests) && 302 rq_prio(list_next_entry(rq, sched.link)) > last_prio) 303 return true; 304 305 if (rb) { 306 struct virtual_engine *ve = 307 rb_entry(rb, typeof(*ve), nodes[engine->id].rb); 308 bool preempt = false; 309 310 if (engine == ve->siblings[0]) { /* only preempt one sibling */ 311 struct i915_request *next; 312 313 rcu_read_lock(); 314 next = READ_ONCE(ve->request); 315 if (next) 316 preempt = rq_prio(next) > last_prio; 317 rcu_read_unlock(); 318 } 319 320 if (preempt) 321 return preempt; 322 } 323 324 /* 325 * If the inflight context did not trigger the preemption, then maybe 326 * it was the set of queued requests? Pick the highest priority in 327 * the queue (the first active priolist) and see if it deserves to be 328 * running instead of ELSP[0]. 329 * 330 * The highest priority request in the queue can not be either 331 * ELSP[0] or ELSP[1] as, thanks again to PI, if it was the same 332 * context, it's priority would not exceed ELSP[0] aka last_prio. 333 */ 334 return queue_prio(&engine->execlists) > last_prio; 335 } 336 337 __maybe_unused static inline bool 338 assert_priority_queue(const struct i915_request *prev, 339 const struct i915_request *next) 340 { 341 const struct intel_engine_execlists *execlists = 342 &prev->engine->execlists; 343 344 /* 345 * Without preemption, the prev may refer to the still active element 346 * which we refuse to let go. 347 * 348 * Even with preemption, there are times when we think it is better not 349 * to preempt and leave an ostensibly lower priority request in flight. 350 */ 351 if (port_request(execlists->port) == prev) 352 return true; 353 354 return rq_prio(prev) >= rq_prio(next); 355 } 356 357 /* 358 * The context descriptor encodes various attributes of a context, 359 * including its GTT address and some flags. Because it's fairly 360 * expensive to calculate, we'll just do it once and cache the result, 361 * which remains valid until the context is unpinned. 362 * 363 * This is what a descriptor looks like, from LSB to MSB:: 364 * 365 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template) 366 * bits 12-31: LRCA, GTT address of (the HWSP of) this context 367 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC) 368 * bits 53-54: mbz, reserved for use by hardware 369 * bits 55-63: group ID, currently unused and set to 0 370 * 371 * Starting from Gen11, the upper dword of the descriptor has a new format: 372 * 373 * bits 32-36: reserved 374 * bits 37-47: SW context ID 375 * bits 48:53: engine instance 376 * bit 54: mbz, reserved for use by hardware 377 * bits 55-60: SW counter 378 * bits 61-63: engine class 379 * 380 * engine info, SW context ID and SW counter need to form a unique number 381 * (Context ID) per lrc. 382 */ 383 static u64 384 lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine) 385 { 386 struct i915_gem_context *ctx = ce->gem_context; 387 u64 desc; 388 389 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH))); 390 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH))); 391 392 desc = ctx->desc_template; /* bits 0-11 */ 393 GEM_BUG_ON(desc & GENMASK_ULL(63, 12)); 394 395 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE; 396 /* bits 12-31 */ 397 GEM_BUG_ON(desc & GENMASK_ULL(63, 32)); 398 399 /* 400 * The following 32bits are copied into the OA reports (dword 2). 401 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing 402 * anything below. 403 */ 404 if (INTEL_GEN(engine->i915) >= 11) { 405 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH)); 406 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT; 407 /* bits 37-47 */ 408 409 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT; 410 /* bits 48-53 */ 411 412 /* TODO: decide what to do with SW counter (bits 55-60) */ 413 414 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT; 415 /* bits 61-63 */ 416 } else { 417 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH)); 418 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ 419 } 420 421 return desc; 422 } 423 424 static void unwind_wa_tail(struct i915_request *rq) 425 { 426 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES); 427 assert_ring_tail_valid(rq->ring, rq->tail); 428 } 429 430 static struct i915_request * 431 __unwind_incomplete_requests(struct intel_engine_cs *engine) 432 { 433 struct i915_request *rq, *rn, *active = NULL; 434 struct list_head *uninitialized_var(pl); 435 int prio = I915_PRIORITY_INVALID; 436 437 lockdep_assert_held(&engine->active.lock); 438 439 list_for_each_entry_safe_reverse(rq, rn, 440 &engine->active.requests, 441 sched.link) { 442 struct intel_engine_cs *owner; 443 444 if (i915_request_completed(rq)) 445 break; 446 447 __i915_request_unsubmit(rq); 448 unwind_wa_tail(rq); 449 450 GEM_BUG_ON(rq->hw_context->inflight); 451 452 /* 453 * Push the request back into the queue for later resubmission. 454 * If this request is not native to this physical engine (i.e. 455 * it came from a virtual source), push it back onto the virtual 456 * engine so that it can be moved across onto another physical 457 * engine as load dictates. 458 */ 459 owner = rq->hw_context->engine; 460 if (likely(owner == engine)) { 461 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); 462 if (rq_prio(rq) != prio) { 463 prio = rq_prio(rq); 464 pl = i915_sched_lookup_priolist(engine, prio); 465 } 466 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); 467 468 list_move(&rq->sched.link, pl); 469 active = rq; 470 } else { 471 rq->engine = owner; 472 owner->submit_request(rq); 473 active = NULL; 474 } 475 } 476 477 return active; 478 } 479 480 struct i915_request * 481 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists) 482 { 483 struct intel_engine_cs *engine = 484 container_of(execlists, typeof(*engine), execlists); 485 486 return __unwind_incomplete_requests(engine); 487 } 488 489 static inline void 490 execlists_context_status_change(struct i915_request *rq, unsigned long status) 491 { 492 /* 493 * Only used when GVT-g is enabled now. When GVT-g is disabled, 494 * The compiler should eliminate this function as dead-code. 495 */ 496 if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) 497 return; 498 499 atomic_notifier_call_chain(&rq->engine->context_status_notifier, 500 status, rq); 501 } 502 503 inline void 504 execlists_user_begin(struct intel_engine_execlists *execlists, 505 const struct execlist_port *port) 506 { 507 execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER); 508 } 509 510 inline void 511 execlists_user_end(struct intel_engine_execlists *execlists) 512 { 513 execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER); 514 } 515 516 static inline void 517 execlists_context_schedule_in(struct i915_request *rq) 518 { 519 GEM_BUG_ON(rq->hw_context->inflight); 520 521 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); 522 intel_engine_context_in(rq->engine); 523 rq->hw_context->inflight = rq->engine; 524 } 525 526 static void kick_siblings(struct i915_request *rq) 527 { 528 struct virtual_engine *ve = to_virtual_engine(rq->hw_context->engine); 529 struct i915_request *next = READ_ONCE(ve->request); 530 531 if (next && next->execution_mask & ~rq->execution_mask) 532 tasklet_schedule(&ve->base.execlists.tasklet); 533 } 534 535 static inline void 536 execlists_context_schedule_out(struct i915_request *rq, unsigned long status) 537 { 538 rq->hw_context->inflight = NULL; 539 intel_engine_context_out(rq->engine); 540 execlists_context_status_change(rq, status); 541 trace_i915_request_out(rq); 542 543 /* 544 * If this is part of a virtual engine, its next request may have 545 * been blocked waiting for access to the active context. We have 546 * to kick all the siblings again in case we need to switch (e.g. 547 * the next request is not runnable on this engine). Hopefully, 548 * we will already have submitted the next request before the 549 * tasklet runs and do not need to rebuild each virtual tree 550 * and kick everyone again. 551 */ 552 if (rq->engine != rq->hw_context->engine) 553 kick_siblings(rq); 554 } 555 556 static u64 execlists_update_context(struct i915_request *rq) 557 { 558 struct intel_context *ce = rq->hw_context; 559 560 ce->lrc_reg_state[CTX_RING_TAIL + 1] = 561 intel_ring_set_tail(rq->ring, rq->tail); 562 563 /* 564 * Make sure the context image is complete before we submit it to HW. 565 * 566 * Ostensibly, writes (including the WCB) should be flushed prior to 567 * an uncached write such as our mmio register access, the empirical 568 * evidence (esp. on Braswell) suggests that the WC write into memory 569 * may not be visible to the HW prior to the completion of the UC 570 * register write and that we may begin execution from the context 571 * before its image is complete leading to invalid PD chasing. 572 * 573 * Furthermore, Braswell, at least, wants a full mb to be sure that 574 * the writes are coherent in memory (visible to the GPU) prior to 575 * execution, and not just visible to other CPUs (as is the result of 576 * wmb). 577 */ 578 mb(); 579 return ce->lrc_desc; 580 } 581 582 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port) 583 { 584 if (execlists->ctrl_reg) { 585 writel(lower_32_bits(desc), execlists->submit_reg + port * 2); 586 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1); 587 } else { 588 writel(upper_32_bits(desc), execlists->submit_reg); 589 writel(lower_32_bits(desc), execlists->submit_reg); 590 } 591 } 592 593 static void execlists_submit_ports(struct intel_engine_cs *engine) 594 { 595 struct intel_engine_execlists *execlists = &engine->execlists; 596 struct execlist_port *port = execlists->port; 597 unsigned int n; 598 599 /* 600 * We can skip acquiring intel_runtime_pm_get() here as it was taken 601 * on our behalf by the request (see i915_gem_mark_busy()) and it will 602 * not be relinquished until the device is idle (see 603 * i915_gem_idle_work_handler()). As a precaution, we make sure 604 * that all ELSP are drained i.e. we have processed the CSB, 605 * before allowing ourselves to idle and calling intel_runtime_pm_put(). 606 */ 607 GEM_BUG_ON(!intel_wakeref_active(&engine->wakeref)); 608 609 /* 610 * ELSQ note: the submit queue is not cleared after being submitted 611 * to the HW so we need to make sure we always clean it up. This is 612 * currently ensured by the fact that we always write the same number 613 * of elsq entries, keep this in mind before changing the loop below. 614 */ 615 for (n = execlists_num_ports(execlists); n--; ) { 616 struct i915_request *rq; 617 unsigned int count; 618 u64 desc; 619 620 rq = port_unpack(&port[n], &count); 621 if (rq) { 622 GEM_BUG_ON(count > !n); 623 if (!count++) 624 execlists_context_schedule_in(rq); 625 port_set(&port[n], port_pack(rq, count)); 626 desc = execlists_update_context(rq); 627 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); 628 629 GEM_TRACE("%s in[%d]: ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n", 630 engine->name, n, 631 port[n].context_id, count, 632 rq->fence.context, rq->fence.seqno, 633 hwsp_seqno(rq), 634 rq_prio(rq)); 635 } else { 636 GEM_BUG_ON(!n); 637 desc = 0; 638 } 639 640 write_desc(execlists, desc, n); 641 } 642 643 /* we need to manually load the submit queue */ 644 if (execlists->ctrl_reg) 645 writel(EL_CTRL_LOAD, execlists->ctrl_reg); 646 647 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); 648 } 649 650 static bool ctx_single_port_submission(const struct intel_context *ce) 651 { 652 return (IS_ENABLED(CONFIG_DRM_I915_GVT) && 653 i915_gem_context_force_single_submission(ce->gem_context)); 654 } 655 656 static bool can_merge_ctx(const struct intel_context *prev, 657 const struct intel_context *next) 658 { 659 if (prev != next) 660 return false; 661 662 if (ctx_single_port_submission(prev)) 663 return false; 664 665 return true; 666 } 667 668 static bool can_merge_rq(const struct i915_request *prev, 669 const struct i915_request *next) 670 { 671 GEM_BUG_ON(!assert_priority_queue(prev, next)); 672 673 if (!can_merge_ctx(prev->hw_context, next->hw_context)) 674 return false; 675 676 return true; 677 } 678 679 static void port_assign(struct execlist_port *port, struct i915_request *rq) 680 { 681 GEM_BUG_ON(rq == port_request(port)); 682 683 if (port_isset(port)) 684 i915_request_put(port_request(port)); 685 686 port_set(port, port_pack(i915_request_get(rq), port_count(port))); 687 } 688 689 static void inject_preempt_context(struct intel_engine_cs *engine) 690 { 691 struct intel_engine_execlists *execlists = &engine->execlists; 692 struct intel_context *ce = engine->preempt_context; 693 unsigned int n; 694 695 GEM_BUG_ON(execlists->preempt_complete_status != 696 upper_32_bits(ce->lrc_desc)); 697 698 /* 699 * Switch to our empty preempt context so 700 * the state of the GPU is known (idle). 701 */ 702 GEM_TRACE("%s\n", engine->name); 703 for (n = execlists_num_ports(execlists); --n; ) 704 write_desc(execlists, 0, n); 705 706 write_desc(execlists, ce->lrc_desc, n); 707 708 /* we need to manually load the submit queue */ 709 if (execlists->ctrl_reg) 710 writel(EL_CTRL_LOAD, execlists->ctrl_reg); 711 712 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); 713 execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT); 714 715 (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++); 716 } 717 718 static void complete_preempt_context(struct intel_engine_execlists *execlists) 719 { 720 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT)); 721 722 if (inject_preempt_hang(execlists)) 723 return; 724 725 execlists_cancel_port_requests(execlists); 726 __unwind_incomplete_requests(container_of(execlists, 727 struct intel_engine_cs, 728 execlists)); 729 } 730 731 static void virtual_update_register_offsets(u32 *regs, 732 struct intel_engine_cs *engine) 733 { 734 u32 base = engine->mmio_base; 735 736 /* Must match execlists_init_reg_state()! */ 737 738 regs[CTX_CONTEXT_CONTROL] = 739 i915_mmio_reg_offset(RING_CONTEXT_CONTROL(base)); 740 regs[CTX_RING_HEAD] = i915_mmio_reg_offset(RING_HEAD(base)); 741 regs[CTX_RING_TAIL] = i915_mmio_reg_offset(RING_TAIL(base)); 742 regs[CTX_RING_BUFFER_START] = i915_mmio_reg_offset(RING_START(base)); 743 regs[CTX_RING_BUFFER_CONTROL] = i915_mmio_reg_offset(RING_CTL(base)); 744 745 regs[CTX_BB_HEAD_U] = i915_mmio_reg_offset(RING_BBADDR_UDW(base)); 746 regs[CTX_BB_HEAD_L] = i915_mmio_reg_offset(RING_BBADDR(base)); 747 regs[CTX_BB_STATE] = i915_mmio_reg_offset(RING_BBSTATE(base)); 748 regs[CTX_SECOND_BB_HEAD_U] = 749 i915_mmio_reg_offset(RING_SBBADDR_UDW(base)); 750 regs[CTX_SECOND_BB_HEAD_L] = i915_mmio_reg_offset(RING_SBBADDR(base)); 751 regs[CTX_SECOND_BB_STATE] = i915_mmio_reg_offset(RING_SBBSTATE(base)); 752 753 regs[CTX_CTX_TIMESTAMP] = 754 i915_mmio_reg_offset(RING_CTX_TIMESTAMP(base)); 755 regs[CTX_PDP3_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 3)); 756 regs[CTX_PDP3_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 3)); 757 regs[CTX_PDP2_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 2)); 758 regs[CTX_PDP2_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 2)); 759 regs[CTX_PDP1_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 1)); 760 regs[CTX_PDP1_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 1)); 761 regs[CTX_PDP0_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0)); 762 regs[CTX_PDP0_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0)); 763 764 if (engine->class == RENDER_CLASS) { 765 regs[CTX_RCS_INDIRECT_CTX] = 766 i915_mmio_reg_offset(RING_INDIRECT_CTX(base)); 767 regs[CTX_RCS_INDIRECT_CTX_OFFSET] = 768 i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(base)); 769 regs[CTX_BB_PER_CTX_PTR] = 770 i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(base)); 771 772 regs[CTX_R_PWR_CLK_STATE] = 773 i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE); 774 } 775 } 776 777 static bool virtual_matches(const struct virtual_engine *ve, 778 const struct i915_request *rq, 779 const struct intel_engine_cs *engine) 780 { 781 const struct intel_engine_cs *inflight; 782 783 if (!(rq->execution_mask & engine->mask)) /* We peeked too soon! */ 784 return false; 785 786 /* 787 * We track when the HW has completed saving the context image 788 * (i.e. when we have seen the final CS event switching out of 789 * the context) and must not overwrite the context image before 790 * then. This restricts us to only using the active engine 791 * while the previous virtualized request is inflight (so 792 * we reuse the register offsets). This is a very small 793 * hystersis on the greedy seelction algorithm. 794 */ 795 inflight = READ_ONCE(ve->context.inflight); 796 if (inflight && inflight != engine) 797 return false; 798 799 return true; 800 } 801 802 static void virtual_xfer_breadcrumbs(struct virtual_engine *ve, 803 struct intel_engine_cs *engine) 804 { 805 struct intel_engine_cs *old = ve->siblings[0]; 806 807 /* All unattached (rq->engine == old) must already be completed */ 808 809 spin_lock(&old->breadcrumbs.irq_lock); 810 if (!list_empty(&ve->context.signal_link)) { 811 list_move_tail(&ve->context.signal_link, 812 &engine->breadcrumbs.signalers); 813 intel_engine_queue_breadcrumbs(engine); 814 } 815 spin_unlock(&old->breadcrumbs.irq_lock); 816 } 817 818 static void execlists_dequeue(struct intel_engine_cs *engine) 819 { 820 struct intel_engine_execlists * const execlists = &engine->execlists; 821 struct execlist_port *port = execlists->port; 822 const struct execlist_port * const last_port = 823 &execlists->port[execlists->port_mask]; 824 struct i915_request *last = port_request(port); 825 struct rb_node *rb; 826 bool submit = false; 827 828 /* 829 * Hardware submission is through 2 ports. Conceptually each port 830 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is 831 * static for a context, and unique to each, so we only execute 832 * requests belonging to a single context from each ring. RING_HEAD 833 * is maintained by the CS in the context image, it marks the place 834 * where it got up to last time, and through RING_TAIL we tell the CS 835 * where we want to execute up to this time. 836 * 837 * In this list the requests are in order of execution. Consecutive 838 * requests from the same context are adjacent in the ringbuffer. We 839 * can combine these requests into a single RING_TAIL update: 840 * 841 * RING_HEAD...req1...req2 842 * ^- RING_TAIL 843 * since to execute req2 the CS must first execute req1. 844 * 845 * Our goal then is to point each port to the end of a consecutive 846 * sequence of requests as being the most optimal (fewest wake ups 847 * and context switches) submission. 848 */ 849 850 for (rb = rb_first_cached(&execlists->virtual); rb; ) { 851 struct virtual_engine *ve = 852 rb_entry(rb, typeof(*ve), nodes[engine->id].rb); 853 struct i915_request *rq = READ_ONCE(ve->request); 854 855 if (!rq) { /* lazily cleanup after another engine handled rq */ 856 rb_erase_cached(rb, &execlists->virtual); 857 RB_CLEAR_NODE(rb); 858 rb = rb_first_cached(&execlists->virtual); 859 continue; 860 } 861 862 if (!virtual_matches(ve, rq, engine)) { 863 rb = rb_next(rb); 864 continue; 865 } 866 867 break; 868 } 869 870 if (last) { 871 /* 872 * Don't resubmit or switch until all outstanding 873 * preemptions (lite-restore) are seen. Then we 874 * know the next preemption status we see corresponds 875 * to this ELSP update. 876 */ 877 GEM_BUG_ON(!execlists_is_active(execlists, 878 EXECLISTS_ACTIVE_USER)); 879 GEM_BUG_ON(!port_count(&port[0])); 880 881 /* 882 * If we write to ELSP a second time before the HW has had 883 * a chance to respond to the previous write, we can confuse 884 * the HW and hit "undefined behaviour". After writing to ELSP, 885 * we must then wait until we see a context-switch event from 886 * the HW to indicate that it has had a chance to respond. 887 */ 888 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK)) 889 return; 890 891 if (need_preempt(engine, last, rb)) { 892 inject_preempt_context(engine); 893 return; 894 } 895 896 /* 897 * In theory, we could coalesce more requests onto 898 * the second port (the first port is active, with 899 * no preemptions pending). However, that means we 900 * then have to deal with the possible lite-restore 901 * of the second port (as we submit the ELSP, there 902 * may be a context-switch) but also we may complete 903 * the resubmission before the context-switch. Ergo, 904 * coalescing onto the second port will cause a 905 * preemption event, but we cannot predict whether 906 * that will affect port[0] or port[1]. 907 * 908 * If the second port is already active, we can wait 909 * until the next context-switch before contemplating 910 * new requests. The GPU will be busy and we should be 911 * able to resubmit the new ELSP before it idles, 912 * avoiding pipeline bubbles (momentary pauses where 913 * the driver is unable to keep up the supply of new 914 * work). However, we have to double check that the 915 * priorities of the ports haven't been switch. 916 */ 917 if (port_count(&port[1])) 918 return; 919 920 /* 921 * WaIdleLiteRestore:bdw,skl 922 * Apply the wa NOOPs to prevent 923 * ring:HEAD == rq:TAIL as we resubmit the 924 * request. See gen8_emit_fini_breadcrumb() for 925 * where we prepare the padding after the 926 * end of the request. 927 */ 928 last->tail = last->wa_tail; 929 } 930 931 while (rb) { /* XXX virtual is always taking precedence */ 932 struct virtual_engine *ve = 933 rb_entry(rb, typeof(*ve), nodes[engine->id].rb); 934 struct i915_request *rq; 935 936 spin_lock(&ve->base.active.lock); 937 938 rq = ve->request; 939 if (unlikely(!rq)) { /* lost the race to a sibling */ 940 spin_unlock(&ve->base.active.lock); 941 rb_erase_cached(rb, &execlists->virtual); 942 RB_CLEAR_NODE(rb); 943 rb = rb_first_cached(&execlists->virtual); 944 continue; 945 } 946 947 GEM_BUG_ON(rq != ve->request); 948 GEM_BUG_ON(rq->engine != &ve->base); 949 GEM_BUG_ON(rq->hw_context != &ve->context); 950 951 if (rq_prio(rq) >= queue_prio(execlists)) { 952 if (!virtual_matches(ve, rq, engine)) { 953 spin_unlock(&ve->base.active.lock); 954 rb = rb_next(rb); 955 continue; 956 } 957 958 if (last && !can_merge_rq(last, rq)) { 959 spin_unlock(&ve->base.active.lock); 960 return; /* leave this rq for another engine */ 961 } 962 963 GEM_TRACE("%s: virtual rq=%llx:%lld%s, new engine? %s\n", 964 engine->name, 965 rq->fence.context, 966 rq->fence.seqno, 967 i915_request_completed(rq) ? "!" : 968 i915_request_started(rq) ? "*" : 969 "", 970 yesno(engine != ve->siblings[0])); 971 972 ve->request = NULL; 973 ve->base.execlists.queue_priority_hint = INT_MIN; 974 rb_erase_cached(rb, &execlists->virtual); 975 RB_CLEAR_NODE(rb); 976 977 GEM_BUG_ON(!(rq->execution_mask & engine->mask)); 978 rq->engine = engine; 979 980 if (engine != ve->siblings[0]) { 981 u32 *regs = ve->context.lrc_reg_state; 982 unsigned int n; 983 984 GEM_BUG_ON(READ_ONCE(ve->context.inflight)); 985 virtual_update_register_offsets(regs, engine); 986 987 if (!list_empty(&ve->context.signals)) 988 virtual_xfer_breadcrumbs(ve, engine); 989 990 /* 991 * Move the bound engine to the top of the list 992 * for future execution. We then kick this 993 * tasklet first before checking others, so that 994 * we preferentially reuse this set of bound 995 * registers. 996 */ 997 for (n = 1; n < ve->num_siblings; n++) { 998 if (ve->siblings[n] == engine) { 999 swap(ve->siblings[n], 1000 ve->siblings[0]); 1001 break; 1002 } 1003 } 1004 1005 GEM_BUG_ON(ve->siblings[0] != engine); 1006 } 1007 1008 __i915_request_submit(rq); 1009 trace_i915_request_in(rq, port_index(port, execlists)); 1010 submit = true; 1011 last = rq; 1012 } 1013 1014 spin_unlock(&ve->base.active.lock); 1015 break; 1016 } 1017 1018 while ((rb = rb_first_cached(&execlists->queue))) { 1019 struct i915_priolist *p = to_priolist(rb); 1020 struct i915_request *rq, *rn; 1021 int i; 1022 1023 priolist_for_each_request_consume(rq, rn, p, i) { 1024 /* 1025 * Can we combine this request with the current port? 1026 * It has to be the same context/ringbuffer and not 1027 * have any exceptions (e.g. GVT saying never to 1028 * combine contexts). 1029 * 1030 * If we can combine the requests, we can execute both 1031 * by updating the RING_TAIL to point to the end of the 1032 * second request, and so we never need to tell the 1033 * hardware about the first. 1034 */ 1035 if (last && !can_merge_rq(last, rq)) { 1036 /* 1037 * If we are on the second port and cannot 1038 * combine this request with the last, then we 1039 * are done. 1040 */ 1041 if (port == last_port) 1042 goto done; 1043 1044 /* 1045 * We must not populate both ELSP[] with the 1046 * same LRCA, i.e. we must submit 2 different 1047 * contexts if we submit 2 ELSP. 1048 */ 1049 if (last->hw_context == rq->hw_context) 1050 goto done; 1051 1052 /* 1053 * If GVT overrides us we only ever submit 1054 * port[0], leaving port[1] empty. Note that we 1055 * also have to be careful that we don't queue 1056 * the same context (even though a different 1057 * request) to the second port. 1058 */ 1059 if (ctx_single_port_submission(last->hw_context) || 1060 ctx_single_port_submission(rq->hw_context)) 1061 goto done; 1062 1063 1064 if (submit) 1065 port_assign(port, last); 1066 port++; 1067 1068 GEM_BUG_ON(port_isset(port)); 1069 } 1070 1071 __i915_request_submit(rq); 1072 trace_i915_request_in(rq, port_index(port, execlists)); 1073 1074 last = rq; 1075 submit = true; 1076 } 1077 1078 rb_erase_cached(&p->node, &execlists->queue); 1079 i915_priolist_free(p); 1080 } 1081 1082 done: 1083 /* 1084 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer. 1085 * 1086 * We choose the priority hint such that if we add a request of greater 1087 * priority than this, we kick the submission tasklet to decide on 1088 * the right order of submitting the requests to hardware. We must 1089 * also be prepared to reorder requests as they are in-flight on the 1090 * HW. We derive the priority hint then as the first "hole" in 1091 * the HW submission ports and if there are no available slots, 1092 * the priority of the lowest executing request, i.e. last. 1093 * 1094 * When we do receive a higher priority request ready to run from the 1095 * user, see queue_request(), the priority hint is bumped to that 1096 * request triggering preemption on the next dequeue (or subsequent 1097 * interrupt for secondary ports). 1098 */ 1099 execlists->queue_priority_hint = queue_prio(execlists); 1100 1101 if (submit) { 1102 port_assign(port, last); 1103 execlists_submit_ports(engine); 1104 } 1105 1106 /* We must always keep the beast fed if we have work piled up */ 1107 GEM_BUG_ON(rb_first_cached(&execlists->queue) && 1108 !port_isset(execlists->port)); 1109 1110 /* Re-evaluate the executing context setup after each preemptive kick */ 1111 if (last) 1112 execlists_user_begin(execlists, execlists->port); 1113 1114 /* If the engine is now idle, so should be the flag; and vice versa. */ 1115 GEM_BUG_ON(execlists_is_active(&engine->execlists, 1116 EXECLISTS_ACTIVE_USER) == 1117 !port_isset(engine->execlists.port)); 1118 } 1119 1120 void 1121 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists) 1122 { 1123 struct execlist_port *port = execlists->port; 1124 unsigned int num_ports = execlists_num_ports(execlists); 1125 1126 while (num_ports-- && port_isset(port)) { 1127 struct i915_request *rq = port_request(port); 1128 1129 GEM_TRACE("%s:port%u fence %llx:%lld, (current %d)\n", 1130 rq->engine->name, 1131 (unsigned int)(port - execlists->port), 1132 rq->fence.context, rq->fence.seqno, 1133 hwsp_seqno(rq)); 1134 1135 GEM_BUG_ON(!execlists->active); 1136 execlists_context_schedule_out(rq, 1137 i915_request_completed(rq) ? 1138 INTEL_CONTEXT_SCHEDULE_OUT : 1139 INTEL_CONTEXT_SCHEDULE_PREEMPTED); 1140 1141 i915_request_put(rq); 1142 1143 memset(port, 0, sizeof(*port)); 1144 port++; 1145 } 1146 1147 execlists_clear_all_active(execlists); 1148 } 1149 1150 static inline void 1151 invalidate_csb_entries(const u32 *first, const u32 *last) 1152 { 1153 clflush((void *)first); 1154 clflush((void *)last); 1155 } 1156 1157 static inline bool 1158 reset_in_progress(const struct intel_engine_execlists *execlists) 1159 { 1160 return unlikely(!__tasklet_is_enabled(&execlists->tasklet)); 1161 } 1162 1163 static void process_csb(struct intel_engine_cs *engine) 1164 { 1165 struct intel_engine_execlists * const execlists = &engine->execlists; 1166 struct execlist_port *port = execlists->port; 1167 const u32 * const buf = execlists->csb_status; 1168 const u8 num_entries = execlists->csb_size; 1169 u8 head, tail; 1170 1171 lockdep_assert_held(&engine->active.lock); 1172 1173 /* 1174 * Note that csb_write, csb_status may be either in HWSP or mmio. 1175 * When reading from the csb_write mmio register, we have to be 1176 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is 1177 * the low 4bits. As it happens we know the next 4bits are always 1178 * zero and so we can simply masked off the low u8 of the register 1179 * and treat it identically to reading from the HWSP (without having 1180 * to use explicit shifting and masking, and probably bifurcating 1181 * the code to handle the legacy mmio read). 1182 */ 1183 head = execlists->csb_head; 1184 tail = READ_ONCE(*execlists->csb_write); 1185 GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail); 1186 if (unlikely(head == tail)) 1187 return; 1188 1189 /* 1190 * Hopefully paired with a wmb() in HW! 1191 * 1192 * We must complete the read of the write pointer before any reads 1193 * from the CSB, so that we do not see stale values. Without an rmb 1194 * (lfence) the HW may speculatively perform the CSB[] reads *before* 1195 * we perform the READ_ONCE(*csb_write). 1196 */ 1197 rmb(); 1198 1199 do { 1200 struct i915_request *rq; 1201 unsigned int status; 1202 unsigned int count; 1203 1204 if (++head == num_entries) 1205 head = 0; 1206 1207 /* 1208 * We are flying near dragons again. 1209 * 1210 * We hold a reference to the request in execlist_port[] 1211 * but no more than that. We are operating in softirq 1212 * context and so cannot hold any mutex or sleep. That 1213 * prevents us stopping the requests we are processing 1214 * in port[] from being retired simultaneously (the 1215 * breadcrumb will be complete before we see the 1216 * context-switch). As we only hold the reference to the 1217 * request, any pointer chasing underneath the request 1218 * is subject to a potential use-after-free. Thus we 1219 * store all of the bookkeeping within port[] as 1220 * required, and avoid using unguarded pointers beneath 1221 * request itself. The same applies to the atomic 1222 * status notifier. 1223 */ 1224 1225 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n", 1226 engine->name, head, 1227 buf[2 * head + 0], buf[2 * head + 1], 1228 execlists->active); 1229 1230 status = buf[2 * head]; 1231 if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE | 1232 GEN8_CTX_STATUS_PREEMPTED)) 1233 execlists_set_active(execlists, 1234 EXECLISTS_ACTIVE_HWACK); 1235 if (status & GEN8_CTX_STATUS_ACTIVE_IDLE) 1236 execlists_clear_active(execlists, 1237 EXECLISTS_ACTIVE_HWACK); 1238 1239 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) 1240 continue; 1241 1242 /* We should never get a COMPLETED | IDLE_ACTIVE! */ 1243 GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE); 1244 1245 if (status & GEN8_CTX_STATUS_COMPLETE && 1246 buf[2*head + 1] == execlists->preempt_complete_status) { 1247 GEM_TRACE("%s preempt-idle\n", engine->name); 1248 complete_preempt_context(execlists); 1249 continue; 1250 } 1251 1252 if (status & GEN8_CTX_STATUS_PREEMPTED && 1253 execlists_is_active(execlists, 1254 EXECLISTS_ACTIVE_PREEMPT)) 1255 continue; 1256 1257 GEM_BUG_ON(!execlists_is_active(execlists, 1258 EXECLISTS_ACTIVE_USER)); 1259 1260 rq = port_unpack(port, &count); 1261 GEM_TRACE("%s out[0]: ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n", 1262 engine->name, 1263 port->context_id, count, 1264 rq ? rq->fence.context : 0, 1265 rq ? rq->fence.seqno : 0, 1266 rq ? hwsp_seqno(rq) : 0, 1267 rq ? rq_prio(rq) : 0); 1268 1269 /* Check the context/desc id for this event matches */ 1270 GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id); 1271 1272 GEM_BUG_ON(count == 0); 1273 if (--count == 0) { 1274 /* 1275 * On the final event corresponding to the 1276 * submission of this context, we expect either 1277 * an element-switch event or a completion 1278 * event (and on completion, the active-idle 1279 * marker). No more preemptions, lite-restore 1280 * or otherwise. 1281 */ 1282 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); 1283 GEM_BUG_ON(port_isset(&port[1]) && 1284 !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH)); 1285 GEM_BUG_ON(!port_isset(&port[1]) && 1286 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); 1287 1288 /* 1289 * We rely on the hardware being strongly 1290 * ordered, that the breadcrumb write is 1291 * coherent (visible from the CPU) before the 1292 * user interrupt and CSB is processed. 1293 */ 1294 GEM_BUG_ON(!i915_request_completed(rq)); 1295 1296 execlists_context_schedule_out(rq, 1297 INTEL_CONTEXT_SCHEDULE_OUT); 1298 i915_request_put(rq); 1299 1300 GEM_TRACE("%s completed ctx=%d\n", 1301 engine->name, port->context_id); 1302 1303 port = execlists_port_complete(execlists, port); 1304 if (port_isset(port)) 1305 execlists_user_begin(execlists, port); 1306 else 1307 execlists_user_end(execlists); 1308 } else { 1309 port_set(port, port_pack(rq, count)); 1310 } 1311 } while (head != tail); 1312 1313 execlists->csb_head = head; 1314 1315 /* 1316 * Gen11 has proven to fail wrt global observation point between 1317 * entry and tail update, failing on the ordering and thus 1318 * we see an old entry in the context status buffer. 1319 * 1320 * Forcibly evict out entries for the next gpu csb update, 1321 * to increase the odds that we get a fresh entries with non 1322 * working hardware. The cost for doing so comes out mostly with 1323 * the wash as hardware, working or not, will need to do the 1324 * invalidation before. 1325 */ 1326 invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); 1327 } 1328 1329 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) 1330 { 1331 lockdep_assert_held(&engine->active.lock); 1332 1333 process_csb(engine); 1334 if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT)) 1335 execlists_dequeue(engine); 1336 } 1337 1338 /* 1339 * Check the unread Context Status Buffers and manage the submission of new 1340 * contexts to the ELSP accordingly. 1341 */ 1342 static void execlists_submission_tasklet(unsigned long data) 1343 { 1344 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; 1345 unsigned long flags; 1346 1347 GEM_TRACE("%s awake?=%d, active=%x\n", 1348 engine->name, 1349 !!intel_wakeref_active(&engine->wakeref), 1350 engine->execlists.active); 1351 1352 spin_lock_irqsave(&engine->active.lock, flags); 1353 __execlists_submission_tasklet(engine); 1354 spin_unlock_irqrestore(&engine->active.lock, flags); 1355 } 1356 1357 static void queue_request(struct intel_engine_cs *engine, 1358 struct i915_sched_node *node, 1359 int prio) 1360 { 1361 GEM_BUG_ON(!list_empty(&node->link)); 1362 list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio)); 1363 } 1364 1365 static void __submit_queue_imm(struct intel_engine_cs *engine) 1366 { 1367 struct intel_engine_execlists * const execlists = &engine->execlists; 1368 1369 if (reset_in_progress(execlists)) 1370 return; /* defer until we restart the engine following reset */ 1371 1372 if (execlists->tasklet.func == execlists_submission_tasklet) 1373 __execlists_submission_tasklet(engine); 1374 else 1375 tasklet_hi_schedule(&execlists->tasklet); 1376 } 1377 1378 static void submit_queue(struct intel_engine_cs *engine, int prio) 1379 { 1380 if (prio > engine->execlists.queue_priority_hint) { 1381 engine->execlists.queue_priority_hint = prio; 1382 __submit_queue_imm(engine); 1383 } 1384 } 1385 1386 static void execlists_submit_request(struct i915_request *request) 1387 { 1388 struct intel_engine_cs *engine = request->engine; 1389 unsigned long flags; 1390 1391 /* Will be called from irq-context when using foreign fences. */ 1392 spin_lock_irqsave(&engine->active.lock, flags); 1393 1394 queue_request(engine, &request->sched, rq_prio(request)); 1395 1396 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); 1397 GEM_BUG_ON(list_empty(&request->sched.link)); 1398 1399 submit_queue(engine, rq_prio(request)); 1400 1401 spin_unlock_irqrestore(&engine->active.lock, flags); 1402 } 1403 1404 static void __execlists_context_fini(struct intel_context *ce) 1405 { 1406 intel_ring_put(ce->ring); 1407 1408 GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj)); 1409 i915_gem_object_put(ce->state->obj); 1410 } 1411 1412 static void execlists_context_destroy(struct kref *kref) 1413 { 1414 struct intel_context *ce = container_of(kref, typeof(*ce), ref); 1415 1416 GEM_BUG_ON(intel_context_is_pinned(ce)); 1417 1418 if (ce->state) 1419 __execlists_context_fini(ce); 1420 1421 intel_context_free(ce); 1422 } 1423 1424 static void execlists_context_unpin(struct intel_context *ce) 1425 { 1426 i915_gem_context_unpin_hw_id(ce->gem_context); 1427 i915_gem_object_unpin_map(ce->state->obj); 1428 intel_ring_unpin(ce->ring); 1429 } 1430 1431 static void 1432 __execlists_update_reg_state(struct intel_context *ce, 1433 struct intel_engine_cs *engine) 1434 { 1435 struct intel_ring *ring = ce->ring; 1436 u32 *regs = ce->lrc_reg_state; 1437 1438 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); 1439 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); 1440 1441 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma); 1442 regs[CTX_RING_HEAD + 1] = ring->head; 1443 regs[CTX_RING_TAIL + 1] = ring->tail; 1444 1445 /* RPCS */ 1446 if (engine->class == RENDER_CLASS) 1447 regs[CTX_R_PWR_CLK_STATE + 1] = 1448 intel_sseu_make_rpcs(engine->i915, &ce->sseu); 1449 } 1450 1451 static int 1452 __execlists_context_pin(struct intel_context *ce, 1453 struct intel_engine_cs *engine) 1454 { 1455 void *vaddr; 1456 int ret; 1457 1458 GEM_BUG_ON(!ce->gem_context->vm); 1459 1460 ret = execlists_context_deferred_alloc(ce, engine); 1461 if (ret) 1462 goto err; 1463 GEM_BUG_ON(!ce->state); 1464 1465 ret = intel_context_active_acquire(ce, 1466 engine->i915->ggtt.pin_bias | 1467 PIN_OFFSET_BIAS | 1468 PIN_HIGH); 1469 if (ret) 1470 goto err; 1471 1472 vaddr = i915_gem_object_pin_map(ce->state->obj, 1473 i915_coherent_map_type(engine->i915) | 1474 I915_MAP_OVERRIDE); 1475 if (IS_ERR(vaddr)) { 1476 ret = PTR_ERR(vaddr); 1477 goto unpin_active; 1478 } 1479 1480 ret = intel_ring_pin(ce->ring); 1481 if (ret) 1482 goto unpin_map; 1483 1484 ret = i915_gem_context_pin_hw_id(ce->gem_context); 1485 if (ret) 1486 goto unpin_ring; 1487 1488 ce->lrc_desc = lrc_descriptor(ce, engine); 1489 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; 1490 __execlists_update_reg_state(ce, engine); 1491 1492 return 0; 1493 1494 unpin_ring: 1495 intel_ring_unpin(ce->ring); 1496 unpin_map: 1497 i915_gem_object_unpin_map(ce->state->obj); 1498 unpin_active: 1499 intel_context_active_release(ce); 1500 err: 1501 return ret; 1502 } 1503 1504 static int execlists_context_pin(struct intel_context *ce) 1505 { 1506 return __execlists_context_pin(ce, ce->engine); 1507 } 1508 1509 static void execlists_context_reset(struct intel_context *ce) 1510 { 1511 /* 1512 * Because we emit WA_TAIL_DWORDS there may be a disparity 1513 * between our bookkeeping in ce->ring->head and ce->ring->tail and 1514 * that stored in context. As we only write new commands from 1515 * ce->ring->tail onwards, everything before that is junk. If the GPU 1516 * starts reading from its RING_HEAD from the context, it may try to 1517 * execute that junk and die. 1518 * 1519 * The contexts that are stilled pinned on resume belong to the 1520 * kernel, and are local to each engine. All other contexts will 1521 * have their head/tail sanitized upon pinning before use, so they 1522 * will never see garbage, 1523 * 1524 * So to avoid that we reset the context images upon resume. For 1525 * simplicity, we just zero everything out. 1526 */ 1527 intel_ring_reset(ce->ring, 0); 1528 __execlists_update_reg_state(ce, ce->engine); 1529 } 1530 1531 static const struct intel_context_ops execlists_context_ops = { 1532 .pin = execlists_context_pin, 1533 .unpin = execlists_context_unpin, 1534 1535 .enter = intel_context_enter_engine, 1536 .exit = intel_context_exit_engine, 1537 1538 .reset = execlists_context_reset, 1539 .destroy = execlists_context_destroy, 1540 }; 1541 1542 static int gen8_emit_init_breadcrumb(struct i915_request *rq) 1543 { 1544 u32 *cs; 1545 1546 GEM_BUG_ON(!rq->timeline->has_initial_breadcrumb); 1547 1548 cs = intel_ring_begin(rq, 6); 1549 if (IS_ERR(cs)) 1550 return PTR_ERR(cs); 1551 1552 /* 1553 * Check if we have been preempted before we even get started. 1554 * 1555 * After this point i915_request_started() reports true, even if 1556 * we get preempted and so are no longer running. 1557 */ 1558 *cs++ = MI_ARB_CHECK; 1559 *cs++ = MI_NOOP; 1560 1561 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; 1562 *cs++ = rq->timeline->hwsp_offset; 1563 *cs++ = 0; 1564 *cs++ = rq->fence.seqno - 1; 1565 1566 intel_ring_advance(rq, cs); 1567 1568 /* Record the updated position of the request's payload */ 1569 rq->infix = intel_ring_offset(rq, cs); 1570 1571 return 0; 1572 } 1573 1574 static int emit_pdps(struct i915_request *rq) 1575 { 1576 const struct intel_engine_cs * const engine = rq->engine; 1577 struct i915_ppgtt * const ppgtt = 1578 i915_vm_to_ppgtt(rq->gem_context->vm); 1579 int err, i; 1580 u32 *cs; 1581 1582 GEM_BUG_ON(intel_vgpu_active(rq->i915)); 1583 1584 /* 1585 * Beware ye of the dragons, this sequence is magic! 1586 * 1587 * Small changes to this sequence can cause anything from 1588 * GPU hangs to forcewake errors and machine lockups! 1589 */ 1590 1591 /* Flush any residual operations from the context load */ 1592 err = engine->emit_flush(rq, EMIT_FLUSH); 1593 if (err) 1594 return err; 1595 1596 /* Magic required to prevent forcewake errors! */ 1597 err = engine->emit_flush(rq, EMIT_INVALIDATE); 1598 if (err) 1599 return err; 1600 1601 cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2); 1602 if (IS_ERR(cs)) 1603 return PTR_ERR(cs); 1604 1605 /* Ensure the LRI have landed before we invalidate & continue */ 1606 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED; 1607 for (i = GEN8_3LVL_PDPES; i--; ) { 1608 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); 1609 u32 base = engine->mmio_base; 1610 1611 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i)); 1612 *cs++ = upper_32_bits(pd_daddr); 1613 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i)); 1614 *cs++ = lower_32_bits(pd_daddr); 1615 } 1616 *cs++ = MI_NOOP; 1617 1618 intel_ring_advance(rq, cs); 1619 1620 /* Be doubly sure the LRI have landed before proceeding */ 1621 err = engine->emit_flush(rq, EMIT_FLUSH); 1622 if (err) 1623 return err; 1624 1625 /* Re-invalidate the TLB for luck */ 1626 return engine->emit_flush(rq, EMIT_INVALIDATE); 1627 } 1628 1629 static int execlists_request_alloc(struct i915_request *request) 1630 { 1631 int ret; 1632 1633 GEM_BUG_ON(!intel_context_is_pinned(request->hw_context)); 1634 1635 /* 1636 * Flush enough space to reduce the likelihood of waiting after 1637 * we start building the request - in which case we will just 1638 * have to repeat work. 1639 */ 1640 request->reserved_space += EXECLISTS_REQUEST_SIZE; 1641 1642 /* 1643 * Note that after this point, we have committed to using 1644 * this request as it is being used to both track the 1645 * state of engine initialisation and liveness of the 1646 * golden renderstate above. Think twice before you try 1647 * to cancel/unwind this request now. 1648 */ 1649 1650 /* Unconditionally invalidate GPU caches and TLBs. */ 1651 if (i915_vm_is_4lvl(request->gem_context->vm)) 1652 ret = request->engine->emit_flush(request, EMIT_INVALIDATE); 1653 else 1654 ret = emit_pdps(request); 1655 if (ret) 1656 return ret; 1657 1658 request->reserved_space -= EXECLISTS_REQUEST_SIZE; 1659 return 0; 1660 } 1661 1662 /* 1663 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after 1664 * PIPE_CONTROL instruction. This is required for the flush to happen correctly 1665 * but there is a slight complication as this is applied in WA batch where the 1666 * values are only initialized once so we cannot take register value at the 1667 * beginning and reuse it further; hence we save its value to memory, upload a 1668 * constant value with bit21 set and then we restore it back with the saved value. 1669 * To simplify the WA, a constant value is formed by using the default value 1670 * of this register. This shouldn't be a problem because we are only modifying 1671 * it for a short period and this batch in non-premptible. We can ofcourse 1672 * use additional instructions that read the actual value of the register 1673 * at that time and set our bit of interest but it makes the WA complicated. 1674 * 1675 * This WA is also required for Gen9 so extracting as a function avoids 1676 * code duplication. 1677 */ 1678 static u32 * 1679 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) 1680 { 1681 /* NB no one else is allowed to scribble over scratch + 256! */ 1682 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; 1683 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); 1684 *batch++ = i915_scratch_offset(engine->i915) + 256; 1685 *batch++ = 0; 1686 1687 *batch++ = MI_LOAD_REGISTER_IMM(1); 1688 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); 1689 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; 1690 1691 batch = gen8_emit_pipe_control(batch, 1692 PIPE_CONTROL_CS_STALL | 1693 PIPE_CONTROL_DC_FLUSH_ENABLE, 1694 0); 1695 1696 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; 1697 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); 1698 *batch++ = i915_scratch_offset(engine->i915) + 256; 1699 *batch++ = 0; 1700 1701 return batch; 1702 } 1703 1704 /* 1705 * Typically we only have one indirect_ctx and per_ctx batch buffer which are 1706 * initialized at the beginning and shared across all contexts but this field 1707 * helps us to have multiple batches at different offsets and select them based 1708 * on a criteria. At the moment this batch always start at the beginning of the page 1709 * and at this point we don't have multiple wa_ctx batch buffers. 1710 * 1711 * The number of WA applied are not known at the beginning; we use this field 1712 * to return the no of DWORDS written. 1713 * 1714 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END 1715 * so it adds NOOPs as padding to make it cacheline aligned. 1716 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together 1717 * makes a complete batch buffer. 1718 */ 1719 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) 1720 { 1721 /* WaDisableCtxRestoreArbitration:bdw,chv */ 1722 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 1723 1724 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ 1725 if (IS_BROADWELL(engine->i915)) 1726 batch = gen8_emit_flush_coherentl3_wa(engine, batch); 1727 1728 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ 1729 /* Actual scratch location is at 128 bytes offset */ 1730 batch = gen8_emit_pipe_control(batch, 1731 PIPE_CONTROL_FLUSH_L3 | 1732 PIPE_CONTROL_GLOBAL_GTT_IVB | 1733 PIPE_CONTROL_CS_STALL | 1734 PIPE_CONTROL_QW_WRITE, 1735 i915_scratch_offset(engine->i915) + 1736 2 * CACHELINE_BYTES); 1737 1738 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 1739 1740 /* Pad to end of cacheline */ 1741 while ((unsigned long)batch % CACHELINE_BYTES) 1742 *batch++ = MI_NOOP; 1743 1744 /* 1745 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because 1746 * execution depends on the length specified in terms of cache lines 1747 * in the register CTX_RCS_INDIRECT_CTX 1748 */ 1749 1750 return batch; 1751 } 1752 1753 struct lri { 1754 i915_reg_t reg; 1755 u32 value; 1756 }; 1757 1758 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count) 1759 { 1760 GEM_BUG_ON(!count || count > 63); 1761 1762 *batch++ = MI_LOAD_REGISTER_IMM(count); 1763 do { 1764 *batch++ = i915_mmio_reg_offset(lri->reg); 1765 *batch++ = lri->value; 1766 } while (lri++, --count); 1767 *batch++ = MI_NOOP; 1768 1769 return batch; 1770 } 1771 1772 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) 1773 { 1774 static const struct lri lri[] = { 1775 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ 1776 { 1777 COMMON_SLICE_CHICKEN2, 1778 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE, 1779 0), 1780 }, 1781 1782 /* BSpec: 11391 */ 1783 { 1784 FF_SLICE_CHICKEN, 1785 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX, 1786 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX), 1787 }, 1788 1789 /* BSpec: 11299 */ 1790 { 1791 _3D_CHICKEN3, 1792 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX, 1793 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX), 1794 } 1795 }; 1796 1797 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 1798 1799 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ 1800 batch = gen8_emit_flush_coherentl3_wa(engine, batch); 1801 1802 batch = emit_lri(batch, lri, ARRAY_SIZE(lri)); 1803 1804 /* WaMediaPoolStateCmdInWABB:bxt,glk */ 1805 if (HAS_POOLED_EU(engine->i915)) { 1806 /* 1807 * EU pool configuration is setup along with golden context 1808 * during context initialization. This value depends on 1809 * device type (2x6 or 3x6) and needs to be updated based 1810 * on which subslice is disabled especially for 2x6 1811 * devices, however it is safe to load default 1812 * configuration of 3x6 device instead of masking off 1813 * corresponding bits because HW ignores bits of a disabled 1814 * subslice and drops down to appropriate config. Please 1815 * see render_state_setup() in i915_gem_render_state.c for 1816 * possible configurations, to avoid duplication they are 1817 * not shown here again. 1818 */ 1819 *batch++ = GEN9_MEDIA_POOL_STATE; 1820 *batch++ = GEN9_MEDIA_POOL_ENABLE; 1821 *batch++ = 0x00777000; 1822 *batch++ = 0; 1823 *batch++ = 0; 1824 *batch++ = 0; 1825 } 1826 1827 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 1828 1829 /* Pad to end of cacheline */ 1830 while ((unsigned long)batch % CACHELINE_BYTES) 1831 *batch++ = MI_NOOP; 1832 1833 return batch; 1834 } 1835 1836 static u32 * 1837 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) 1838 { 1839 int i; 1840 1841 /* 1842 * WaPipeControlBefore3DStateSamplePattern: cnl 1843 * 1844 * Ensure the engine is idle prior to programming a 1845 * 3DSTATE_SAMPLE_PATTERN during a context restore. 1846 */ 1847 batch = gen8_emit_pipe_control(batch, 1848 PIPE_CONTROL_CS_STALL, 1849 0); 1850 /* 1851 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for 1852 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in 1853 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is 1854 * confusing. Since gen8_emit_pipe_control() already advances the 1855 * batch by 6 dwords, we advance the other 10 here, completing a 1856 * cacheline. It's not clear if the workaround requires this padding 1857 * before other commands, or if it's just the regular padding we would 1858 * already have for the workaround bb, so leave it here for now. 1859 */ 1860 for (i = 0; i < 10; i++) 1861 *batch++ = MI_NOOP; 1862 1863 /* Pad to end of cacheline */ 1864 while ((unsigned long)batch % CACHELINE_BYTES) 1865 *batch++ = MI_NOOP; 1866 1867 return batch; 1868 } 1869 1870 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE) 1871 1872 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) 1873 { 1874 struct drm_i915_gem_object *obj; 1875 struct i915_vma *vma; 1876 int err; 1877 1878 obj = i915_gem_object_create_shmem(engine->i915, CTX_WA_BB_OBJ_SIZE); 1879 if (IS_ERR(obj)) 1880 return PTR_ERR(obj); 1881 1882 vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL); 1883 if (IS_ERR(vma)) { 1884 err = PTR_ERR(vma); 1885 goto err; 1886 } 1887 1888 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); 1889 if (err) 1890 goto err; 1891 1892 engine->wa_ctx.vma = vma; 1893 return 0; 1894 1895 err: 1896 i915_gem_object_put(obj); 1897 return err; 1898 } 1899 1900 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine) 1901 { 1902 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); 1903 } 1904 1905 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch); 1906 1907 static int intel_init_workaround_bb(struct intel_engine_cs *engine) 1908 { 1909 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; 1910 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx, 1911 &wa_ctx->per_ctx }; 1912 wa_bb_func_t wa_bb_fn[2]; 1913 struct page *page; 1914 void *batch, *batch_ptr; 1915 unsigned int i; 1916 int ret; 1917 1918 if (engine->class != RENDER_CLASS) 1919 return 0; 1920 1921 switch (INTEL_GEN(engine->i915)) { 1922 case 11: 1923 return 0; 1924 case 10: 1925 wa_bb_fn[0] = gen10_init_indirectctx_bb; 1926 wa_bb_fn[1] = NULL; 1927 break; 1928 case 9: 1929 wa_bb_fn[0] = gen9_init_indirectctx_bb; 1930 wa_bb_fn[1] = NULL; 1931 break; 1932 case 8: 1933 wa_bb_fn[0] = gen8_init_indirectctx_bb; 1934 wa_bb_fn[1] = NULL; 1935 break; 1936 default: 1937 MISSING_CASE(INTEL_GEN(engine->i915)); 1938 return 0; 1939 } 1940 1941 ret = lrc_setup_wa_ctx(engine); 1942 if (ret) { 1943 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); 1944 return ret; 1945 } 1946 1947 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); 1948 batch = batch_ptr = kmap_atomic(page); 1949 1950 /* 1951 * Emit the two workaround batch buffers, recording the offset from the 1952 * start of the workaround batch buffer object for each and their 1953 * respective sizes. 1954 */ 1955 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) { 1956 wa_bb[i]->offset = batch_ptr - batch; 1957 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, 1958 CACHELINE_BYTES))) { 1959 ret = -EINVAL; 1960 break; 1961 } 1962 if (wa_bb_fn[i]) 1963 batch_ptr = wa_bb_fn[i](engine, batch_ptr); 1964 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset); 1965 } 1966 1967 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE); 1968 1969 kunmap_atomic(batch); 1970 if (ret) 1971 lrc_destroy_wa_ctx(engine); 1972 1973 return ret; 1974 } 1975 1976 static void enable_execlists(struct intel_engine_cs *engine) 1977 { 1978 intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */ 1979 1980 if (INTEL_GEN(engine->i915) >= 11) 1981 ENGINE_WRITE(engine, 1982 RING_MODE_GEN7, 1983 _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); 1984 else 1985 ENGINE_WRITE(engine, 1986 RING_MODE_GEN7, 1987 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); 1988 1989 ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 1990 1991 ENGINE_WRITE(engine, 1992 RING_HWS_PGA, 1993 i915_ggtt_offset(engine->status_page.vma)); 1994 ENGINE_POSTING_READ(engine, RING_HWS_PGA); 1995 } 1996 1997 static bool unexpected_starting_state(struct intel_engine_cs *engine) 1998 { 1999 bool unexpected = false; 2000 2001 if (ENGINE_READ(engine, RING_MI_MODE) & STOP_RING) { 2002 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n"); 2003 unexpected = true; 2004 } 2005 2006 return unexpected; 2007 } 2008 2009 static int execlists_resume(struct intel_engine_cs *engine) 2010 { 2011 intel_engine_apply_workarounds(engine); 2012 intel_engine_apply_whitelist(engine); 2013 2014 intel_mocs_init_engine(engine); 2015 2016 intel_engine_reset_breadcrumbs(engine); 2017 2018 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) { 2019 struct drm_printer p = drm_debug_printer(__func__); 2020 2021 intel_engine_dump(engine, &p, NULL); 2022 } 2023 2024 enable_execlists(engine); 2025 2026 return 0; 2027 } 2028 2029 static void execlists_reset_prepare(struct intel_engine_cs *engine) 2030 { 2031 struct intel_engine_execlists * const execlists = &engine->execlists; 2032 unsigned long flags; 2033 2034 GEM_TRACE("%s: depth<-%d\n", engine->name, 2035 atomic_read(&execlists->tasklet.count)); 2036 2037 /* 2038 * Prevent request submission to the hardware until we have 2039 * completed the reset in i915_gem_reset_finish(). If a request 2040 * is completed by one engine, it may then queue a request 2041 * to a second via its execlists->tasklet *just* as we are 2042 * calling engine->resume() and also writing the ELSP. 2043 * Turning off the execlists->tasklet until the reset is over 2044 * prevents the race. 2045 */ 2046 __tasklet_disable_sync_once(&execlists->tasklet); 2047 GEM_BUG_ON(!reset_in_progress(execlists)); 2048 2049 intel_engine_stop_cs(engine); 2050 2051 /* And flush any current direct submission. */ 2052 spin_lock_irqsave(&engine->active.lock, flags); 2053 spin_unlock_irqrestore(&engine->active.lock, flags); 2054 } 2055 2056 static bool lrc_regs_ok(const struct i915_request *rq) 2057 { 2058 const struct intel_ring *ring = rq->ring; 2059 const u32 *regs = rq->hw_context->lrc_reg_state; 2060 2061 /* Quick spot check for the common signs of context corruption */ 2062 2063 if (regs[CTX_RING_BUFFER_CONTROL + 1] != 2064 (RING_CTL_SIZE(ring->size) | RING_VALID)) 2065 return false; 2066 2067 if (regs[CTX_RING_BUFFER_START + 1] != i915_ggtt_offset(ring->vma)) 2068 return false; 2069 2070 return true; 2071 } 2072 2073 static void reset_csb_pointers(struct intel_engine_execlists *execlists) 2074 { 2075 const unsigned int reset_value = execlists->csb_size - 1; 2076 2077 /* 2078 * After a reset, the HW starts writing into CSB entry [0]. We 2079 * therefore have to set our HEAD pointer back one entry so that 2080 * the *first* entry we check is entry 0. To complicate this further, 2081 * as we don't wait for the first interrupt after reset, we have to 2082 * fake the HW write to point back to the last entry so that our 2083 * inline comparison of our cached head position against the last HW 2084 * write works even before the first interrupt. 2085 */ 2086 execlists->csb_head = reset_value; 2087 WRITE_ONCE(*execlists->csb_write, reset_value); 2088 wmb(); /* Make sure this is visible to HW (paranoia?) */ 2089 2090 invalidate_csb_entries(&execlists->csb_status[0], 2091 &execlists->csb_status[reset_value]); 2092 } 2093 2094 static struct i915_request *active_request(struct i915_request *rq) 2095 { 2096 const struct list_head * const list = &rq->engine->active.requests; 2097 const struct intel_context * const context = rq->hw_context; 2098 struct i915_request *active = NULL; 2099 2100 list_for_each_entry_from_reverse(rq, list, sched.link) { 2101 if (i915_request_completed(rq)) 2102 break; 2103 2104 if (rq->hw_context != context) 2105 break; 2106 2107 active = rq; 2108 } 2109 2110 return active; 2111 } 2112 2113 static void __execlists_reset(struct intel_engine_cs *engine, bool stalled) 2114 { 2115 struct intel_engine_execlists * const execlists = &engine->execlists; 2116 struct intel_context *ce; 2117 struct i915_request *rq; 2118 u32 *regs; 2119 2120 process_csb(engine); /* drain preemption events */ 2121 2122 /* Following the reset, we need to reload the CSB read/write pointers */ 2123 reset_csb_pointers(&engine->execlists); 2124 2125 /* 2126 * Save the currently executing context, even if we completed 2127 * its request, it was still running at the time of the 2128 * reset and will have been clobbered. 2129 */ 2130 if (!port_isset(execlists->port)) 2131 goto out_clear; 2132 2133 rq = port_request(execlists->port); 2134 ce = rq->hw_context; 2135 2136 /* 2137 * Catch up with any missed context-switch interrupts. 2138 * 2139 * Ideally we would just read the remaining CSB entries now that we 2140 * know the gpu is idle. However, the CSB registers are sometimes^W 2141 * often trashed across a GPU reset! Instead we have to rely on 2142 * guessing the missed context-switch events by looking at what 2143 * requests were completed. 2144 */ 2145 execlists_cancel_port_requests(execlists); 2146 2147 rq = active_request(rq); 2148 if (!rq) 2149 goto out_replay; 2150 2151 /* 2152 * If this request hasn't started yet, e.g. it is waiting on a 2153 * semaphore, we need to avoid skipping the request or else we 2154 * break the signaling chain. However, if the context is corrupt 2155 * the request will not restart and we will be stuck with a wedged 2156 * device. It is quite often the case that if we issue a reset 2157 * while the GPU is loading the context image, that the context 2158 * image becomes corrupt. 2159 * 2160 * Otherwise, if we have not started yet, the request should replay 2161 * perfectly and we do not need to flag the result as being erroneous. 2162 */ 2163 if (!i915_request_started(rq) && lrc_regs_ok(rq)) 2164 goto out_replay; 2165 2166 /* 2167 * If the request was innocent, we leave the request in the ELSP 2168 * and will try to replay it on restarting. The context image may 2169 * have been corrupted by the reset, in which case we may have 2170 * to service a new GPU hang, but more likely we can continue on 2171 * without impact. 2172 * 2173 * If the request was guilty, we presume the context is corrupt 2174 * and have to at least restore the RING register in the context 2175 * image back to the expected values to skip over the guilty request. 2176 */ 2177 i915_reset_request(rq, stalled); 2178 if (!stalled && lrc_regs_ok(rq)) 2179 goto out_replay; 2180 2181 /* 2182 * We want a simple context + ring to execute the breadcrumb update. 2183 * We cannot rely on the context being intact across the GPU hang, 2184 * so clear it and rebuild just what we need for the breadcrumb. 2185 * All pending requests for this context will be zapped, and any 2186 * future request will be after userspace has had the opportunity 2187 * to recreate its own state. 2188 */ 2189 regs = ce->lrc_reg_state; 2190 if (engine->pinned_default_state) { 2191 memcpy(regs, /* skip restoring the vanilla PPHWSP */ 2192 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE, 2193 engine->context_size - PAGE_SIZE); 2194 } 2195 execlists_init_reg_state(regs, ce, engine, ce->ring); 2196 2197 out_replay: 2198 /* Rerun the request; its payload has been neutered (if guilty). */ 2199 ce->ring->head = 2200 rq ? intel_ring_wrap(ce->ring, rq->head) : ce->ring->tail; 2201 intel_ring_update_space(ce->ring); 2202 __execlists_update_reg_state(ce, engine); 2203 2204 /* Push back any incomplete requests for replay after the reset. */ 2205 __unwind_incomplete_requests(engine); 2206 2207 out_clear: 2208 execlists_clear_all_active(execlists); 2209 } 2210 2211 static void execlists_reset(struct intel_engine_cs *engine, bool stalled) 2212 { 2213 unsigned long flags; 2214 2215 GEM_TRACE("%s\n", engine->name); 2216 2217 spin_lock_irqsave(&engine->active.lock, flags); 2218 2219 __execlists_reset(engine, stalled); 2220 2221 spin_unlock_irqrestore(&engine->active.lock, flags); 2222 } 2223 2224 static void nop_submission_tasklet(unsigned long data) 2225 { 2226 /* The driver is wedged; don't process any more events. */ 2227 } 2228 2229 static void execlists_cancel_requests(struct intel_engine_cs *engine) 2230 { 2231 struct intel_engine_execlists * const execlists = &engine->execlists; 2232 struct i915_request *rq, *rn; 2233 struct rb_node *rb; 2234 unsigned long flags; 2235 2236 GEM_TRACE("%s\n", engine->name); 2237 2238 /* 2239 * Before we call engine->cancel_requests(), we should have exclusive 2240 * access to the submission state. This is arranged for us by the 2241 * caller disabling the interrupt generation, the tasklet and other 2242 * threads that may then access the same state, giving us a free hand 2243 * to reset state. However, we still need to let lockdep be aware that 2244 * we know this state may be accessed in hardirq context, so we 2245 * disable the irq around this manipulation and we want to keep 2246 * the spinlock focused on its duties and not accidentally conflate 2247 * coverage to the submission's irq state. (Similarly, although we 2248 * shouldn't need to disable irq around the manipulation of the 2249 * submission's irq state, we also wish to remind ourselves that 2250 * it is irq state.) 2251 */ 2252 spin_lock_irqsave(&engine->active.lock, flags); 2253 2254 __execlists_reset(engine, true); 2255 2256 /* Mark all executing requests as skipped. */ 2257 list_for_each_entry(rq, &engine->active.requests, sched.link) { 2258 if (!i915_request_signaled(rq)) 2259 dma_fence_set_error(&rq->fence, -EIO); 2260 2261 i915_request_mark_complete(rq); 2262 } 2263 2264 /* Flush the queued requests to the timeline list (for retiring). */ 2265 while ((rb = rb_first_cached(&execlists->queue))) { 2266 struct i915_priolist *p = to_priolist(rb); 2267 int i; 2268 2269 priolist_for_each_request_consume(rq, rn, p, i) { 2270 list_del_init(&rq->sched.link); 2271 __i915_request_submit(rq); 2272 dma_fence_set_error(&rq->fence, -EIO); 2273 i915_request_mark_complete(rq); 2274 } 2275 2276 rb_erase_cached(&p->node, &execlists->queue); 2277 i915_priolist_free(p); 2278 } 2279 2280 /* Cancel all attached virtual engines */ 2281 while ((rb = rb_first_cached(&execlists->virtual))) { 2282 struct virtual_engine *ve = 2283 rb_entry(rb, typeof(*ve), nodes[engine->id].rb); 2284 2285 rb_erase_cached(rb, &execlists->virtual); 2286 RB_CLEAR_NODE(rb); 2287 2288 spin_lock(&ve->base.active.lock); 2289 if (ve->request) { 2290 ve->request->engine = engine; 2291 __i915_request_submit(ve->request); 2292 dma_fence_set_error(&ve->request->fence, -EIO); 2293 i915_request_mark_complete(ve->request); 2294 ve->base.execlists.queue_priority_hint = INT_MIN; 2295 ve->request = NULL; 2296 } 2297 spin_unlock(&ve->base.active.lock); 2298 } 2299 2300 /* Remaining _unready_ requests will be nop'ed when submitted */ 2301 2302 execlists->queue_priority_hint = INT_MIN; 2303 execlists->queue = RB_ROOT_CACHED; 2304 GEM_BUG_ON(port_isset(execlists->port)); 2305 2306 GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet)); 2307 execlists->tasklet.func = nop_submission_tasklet; 2308 2309 spin_unlock_irqrestore(&engine->active.lock, flags); 2310 } 2311 2312 static void execlists_reset_finish(struct intel_engine_cs *engine) 2313 { 2314 struct intel_engine_execlists * const execlists = &engine->execlists; 2315 2316 /* 2317 * After a GPU reset, we may have requests to replay. Do so now while 2318 * we still have the forcewake to be sure that the GPU is not allowed 2319 * to sleep before we restart and reload a context. 2320 */ 2321 GEM_BUG_ON(!reset_in_progress(execlists)); 2322 if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) 2323 execlists->tasklet.func(execlists->tasklet.data); 2324 2325 if (__tasklet_enable(&execlists->tasklet)) 2326 /* And kick in case we missed a new request submission. */ 2327 tasklet_hi_schedule(&execlists->tasklet); 2328 GEM_TRACE("%s: depth->%d\n", engine->name, 2329 atomic_read(&execlists->tasklet.count)); 2330 } 2331 2332 static int gen8_emit_bb_start(struct i915_request *rq, 2333 u64 offset, u32 len, 2334 const unsigned int flags) 2335 { 2336 u32 *cs; 2337 2338 cs = intel_ring_begin(rq, 4); 2339 if (IS_ERR(cs)) 2340 return PTR_ERR(cs); 2341 2342 /* 2343 * WaDisableCtxRestoreArbitration:bdw,chv 2344 * 2345 * We don't need to perform MI_ARB_ENABLE as often as we do (in 2346 * particular all the gen that do not need the w/a at all!), if we 2347 * took care to make sure that on every switch into this context 2348 * (both ordinary and for preemption) that arbitrartion was enabled 2349 * we would be fine. However, for gen8 there is another w/a that 2350 * requires us to not preempt inside GPGPU execution, so we keep 2351 * arbitration disabled for gen8 batches. Arbitration will be 2352 * re-enabled before we close the request 2353 * (engine->emit_fini_breadcrumb). 2354 */ 2355 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 2356 2357 /* FIXME(BDW+): Address space and security selectors. */ 2358 *cs++ = MI_BATCH_BUFFER_START_GEN8 | 2359 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); 2360 *cs++ = lower_32_bits(offset); 2361 *cs++ = upper_32_bits(offset); 2362 2363 intel_ring_advance(rq, cs); 2364 2365 return 0; 2366 } 2367 2368 static int gen9_emit_bb_start(struct i915_request *rq, 2369 u64 offset, u32 len, 2370 const unsigned int flags) 2371 { 2372 u32 *cs; 2373 2374 cs = intel_ring_begin(rq, 6); 2375 if (IS_ERR(cs)) 2376 return PTR_ERR(cs); 2377 2378 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 2379 2380 *cs++ = MI_BATCH_BUFFER_START_GEN8 | 2381 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); 2382 *cs++ = lower_32_bits(offset); 2383 *cs++ = upper_32_bits(offset); 2384 2385 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 2386 *cs++ = MI_NOOP; 2387 2388 intel_ring_advance(rq, cs); 2389 2390 return 0; 2391 } 2392 2393 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) 2394 { 2395 ENGINE_WRITE(engine, RING_IMR, 2396 ~(engine->irq_enable_mask | engine->irq_keep_mask)); 2397 ENGINE_POSTING_READ(engine, RING_IMR); 2398 } 2399 2400 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) 2401 { 2402 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); 2403 } 2404 2405 static int gen8_emit_flush(struct i915_request *request, u32 mode) 2406 { 2407 u32 cmd, *cs; 2408 2409 cs = intel_ring_begin(request, 4); 2410 if (IS_ERR(cs)) 2411 return PTR_ERR(cs); 2412 2413 cmd = MI_FLUSH_DW + 1; 2414 2415 /* We always require a command barrier so that subsequent 2416 * commands, such as breadcrumb interrupts, are strictly ordered 2417 * wrt the contents of the write cache being flushed to memory 2418 * (and thus being coherent from the CPU). 2419 */ 2420 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 2421 2422 if (mode & EMIT_INVALIDATE) { 2423 cmd |= MI_INVALIDATE_TLB; 2424 if (request->engine->class == VIDEO_DECODE_CLASS) 2425 cmd |= MI_INVALIDATE_BSD; 2426 } 2427 2428 *cs++ = cmd; 2429 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; 2430 *cs++ = 0; /* upper addr */ 2431 *cs++ = 0; /* value */ 2432 intel_ring_advance(request, cs); 2433 2434 return 0; 2435 } 2436 2437 static int gen8_emit_flush_render(struct i915_request *request, 2438 u32 mode) 2439 { 2440 struct intel_engine_cs *engine = request->engine; 2441 u32 scratch_addr = 2442 i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES; 2443 bool vf_flush_wa = false, dc_flush_wa = false; 2444 u32 *cs, flags = 0; 2445 int len; 2446 2447 flags |= PIPE_CONTROL_CS_STALL; 2448 2449 if (mode & EMIT_FLUSH) { 2450 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 2451 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 2452 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; 2453 flags |= PIPE_CONTROL_FLUSH_ENABLE; 2454 } 2455 2456 if (mode & EMIT_INVALIDATE) { 2457 flags |= PIPE_CONTROL_TLB_INVALIDATE; 2458 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 2459 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 2460 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 2461 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 2462 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 2463 flags |= PIPE_CONTROL_QW_WRITE; 2464 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; 2465 2466 /* 2467 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL 2468 * pipe control. 2469 */ 2470 if (IS_GEN(request->i915, 9)) 2471 vf_flush_wa = true; 2472 2473 /* WaForGAMHang:kbl */ 2474 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) 2475 dc_flush_wa = true; 2476 } 2477 2478 len = 6; 2479 2480 if (vf_flush_wa) 2481 len += 6; 2482 2483 if (dc_flush_wa) 2484 len += 12; 2485 2486 cs = intel_ring_begin(request, len); 2487 if (IS_ERR(cs)) 2488 return PTR_ERR(cs); 2489 2490 if (vf_flush_wa) 2491 cs = gen8_emit_pipe_control(cs, 0, 0); 2492 2493 if (dc_flush_wa) 2494 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, 2495 0); 2496 2497 cs = gen8_emit_pipe_control(cs, flags, scratch_addr); 2498 2499 if (dc_flush_wa) 2500 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); 2501 2502 intel_ring_advance(request, cs); 2503 2504 return 0; 2505 } 2506 2507 /* 2508 * Reserve space for 2 NOOPs at the end of each request to be 2509 * used as a workaround for not being allowed to do lite 2510 * restore with HEAD==TAIL (WaIdleLiteRestore). 2511 */ 2512 static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs) 2513 { 2514 /* Ensure there's always at least one preemption point per-request. */ 2515 *cs++ = MI_ARB_CHECK; 2516 *cs++ = MI_NOOP; 2517 request->wa_tail = intel_ring_offset(request, cs); 2518 2519 return cs; 2520 } 2521 2522 static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs) 2523 { 2524 cs = gen8_emit_ggtt_write(cs, 2525 request->fence.seqno, 2526 request->timeline->hwsp_offset, 2527 0); 2528 2529 *cs++ = MI_USER_INTERRUPT; 2530 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 2531 2532 request->tail = intel_ring_offset(request, cs); 2533 assert_ring_tail_valid(request->ring, request->tail); 2534 2535 return gen8_emit_wa_tail(request, cs); 2536 } 2537 2538 static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) 2539 { 2540 /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */ 2541 cs = gen8_emit_ggtt_write_rcs(cs, 2542 request->fence.seqno, 2543 request->timeline->hwsp_offset, 2544 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | 2545 PIPE_CONTROL_DEPTH_CACHE_FLUSH | 2546 PIPE_CONTROL_DC_FLUSH_ENABLE); 2547 cs = gen8_emit_pipe_control(cs, 2548 PIPE_CONTROL_FLUSH_ENABLE | 2549 PIPE_CONTROL_CS_STALL, 2550 0); 2551 2552 *cs++ = MI_USER_INTERRUPT; 2553 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 2554 2555 request->tail = intel_ring_offset(request, cs); 2556 assert_ring_tail_valid(request->ring, request->tail); 2557 2558 return gen8_emit_wa_tail(request, cs); 2559 } 2560 2561 static int gen8_init_rcs_context(struct i915_request *rq) 2562 { 2563 int ret; 2564 2565 ret = intel_engine_emit_ctx_wa(rq); 2566 if (ret) 2567 return ret; 2568 2569 ret = intel_rcs_context_init_mocs(rq); 2570 /* 2571 * Failing to program the MOCS is non-fatal.The system will not 2572 * run at peak performance. So generate an error and carry on. 2573 */ 2574 if (ret) 2575 DRM_ERROR("MOCS failed to program: expect performance issues.\n"); 2576 2577 return i915_gem_render_state_emit(rq); 2578 } 2579 2580 static void execlists_park(struct intel_engine_cs *engine) 2581 { 2582 intel_engine_park(engine); 2583 } 2584 2585 void intel_execlists_set_default_submission(struct intel_engine_cs *engine) 2586 { 2587 engine->submit_request = execlists_submit_request; 2588 engine->cancel_requests = execlists_cancel_requests; 2589 engine->schedule = i915_schedule; 2590 engine->execlists.tasklet.func = execlists_submission_tasklet; 2591 2592 engine->reset.prepare = execlists_reset_prepare; 2593 engine->reset.reset = execlists_reset; 2594 engine->reset.finish = execlists_reset_finish; 2595 2596 engine->park = execlists_park; 2597 engine->unpark = NULL; 2598 2599 engine->flags |= I915_ENGINE_SUPPORTS_STATS; 2600 if (!intel_vgpu_active(engine->i915)) 2601 engine->flags |= I915_ENGINE_HAS_SEMAPHORES; 2602 if (engine->preempt_context && 2603 HAS_LOGICAL_RING_PREEMPTION(engine->i915)) 2604 engine->flags |= I915_ENGINE_HAS_PREEMPTION; 2605 } 2606 2607 static void execlists_destroy(struct intel_engine_cs *engine) 2608 { 2609 intel_engine_cleanup_common(engine); 2610 lrc_destroy_wa_ctx(engine); 2611 kfree(engine); 2612 } 2613 2614 static void 2615 logical_ring_default_vfuncs(struct intel_engine_cs *engine) 2616 { 2617 /* Default vfuncs which can be overriden by each engine. */ 2618 2619 engine->destroy = execlists_destroy; 2620 engine->resume = execlists_resume; 2621 2622 engine->reset.prepare = execlists_reset_prepare; 2623 engine->reset.reset = execlists_reset; 2624 engine->reset.finish = execlists_reset_finish; 2625 2626 engine->cops = &execlists_context_ops; 2627 engine->request_alloc = execlists_request_alloc; 2628 2629 engine->emit_flush = gen8_emit_flush; 2630 engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb; 2631 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb; 2632 2633 engine->set_default_submission = intel_execlists_set_default_submission; 2634 2635 if (INTEL_GEN(engine->i915) < 11) { 2636 engine->irq_enable = gen8_logical_ring_enable_irq; 2637 engine->irq_disable = gen8_logical_ring_disable_irq; 2638 } else { 2639 /* 2640 * TODO: On Gen11 interrupt masks need to be clear 2641 * to allow C6 entry. Keep interrupts enabled at 2642 * and take the hit of generating extra interrupts 2643 * until a more refined solution exists. 2644 */ 2645 } 2646 if (IS_GEN(engine->i915, 8)) 2647 engine->emit_bb_start = gen8_emit_bb_start; 2648 else 2649 engine->emit_bb_start = gen9_emit_bb_start; 2650 } 2651 2652 static inline void 2653 logical_ring_default_irqs(struct intel_engine_cs *engine) 2654 { 2655 unsigned int shift = 0; 2656 2657 if (INTEL_GEN(engine->i915) < 11) { 2658 const u8 irq_shifts[] = { 2659 [RCS0] = GEN8_RCS_IRQ_SHIFT, 2660 [BCS0] = GEN8_BCS_IRQ_SHIFT, 2661 [VCS0] = GEN8_VCS0_IRQ_SHIFT, 2662 [VCS1] = GEN8_VCS1_IRQ_SHIFT, 2663 [VECS0] = GEN8_VECS_IRQ_SHIFT, 2664 }; 2665 2666 shift = irq_shifts[engine->id]; 2667 } 2668 2669 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; 2670 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; 2671 } 2672 2673 int intel_execlists_submission_setup(struct intel_engine_cs *engine) 2674 { 2675 /* Intentionally left blank. */ 2676 engine->buffer = NULL; 2677 2678 tasklet_init(&engine->execlists.tasklet, 2679 execlists_submission_tasklet, (unsigned long)engine); 2680 2681 logical_ring_default_vfuncs(engine); 2682 logical_ring_default_irqs(engine); 2683 2684 if (engine->class == RENDER_CLASS) { 2685 engine->init_context = gen8_init_rcs_context; 2686 engine->emit_flush = gen8_emit_flush_render; 2687 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs; 2688 } 2689 2690 return 0; 2691 } 2692 2693 int intel_execlists_submission_init(struct intel_engine_cs *engine) 2694 { 2695 struct intel_engine_execlists * const execlists = &engine->execlists; 2696 struct drm_i915_private *i915 = engine->i915; 2697 struct intel_uncore *uncore = engine->uncore; 2698 u32 base = engine->mmio_base; 2699 int ret; 2700 2701 ret = intel_engine_init_common(engine); 2702 if (ret) 2703 return ret; 2704 2705 intel_engine_init_workarounds(engine); 2706 intel_engine_init_whitelist(engine); 2707 2708 if (intel_init_workaround_bb(engine)) 2709 /* 2710 * We continue even if we fail to initialize WA batch 2711 * because we only expect rare glitches but nothing 2712 * critical to prevent us from using GPU 2713 */ 2714 DRM_ERROR("WA batch buffer initialization failed\n"); 2715 2716 if (HAS_LOGICAL_RING_ELSQ(i915)) { 2717 execlists->submit_reg = uncore->regs + 2718 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base)); 2719 execlists->ctrl_reg = uncore->regs + 2720 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base)); 2721 } else { 2722 execlists->submit_reg = uncore->regs + 2723 i915_mmio_reg_offset(RING_ELSP(base)); 2724 } 2725 2726 execlists->preempt_complete_status = ~0u; 2727 if (engine->preempt_context) 2728 execlists->preempt_complete_status = 2729 upper_32_bits(engine->preempt_context->lrc_desc); 2730 2731 execlists->csb_status = 2732 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; 2733 2734 execlists->csb_write = 2735 &engine->status_page.addr[intel_hws_csb_write_index(i915)]; 2736 2737 if (INTEL_GEN(i915) < 11) 2738 execlists->csb_size = GEN8_CSB_ENTRIES; 2739 else 2740 execlists->csb_size = GEN11_CSB_ENTRIES; 2741 2742 reset_csb_pointers(execlists); 2743 2744 return 0; 2745 } 2746 2747 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) 2748 { 2749 u32 indirect_ctx_offset; 2750 2751 switch (INTEL_GEN(engine->i915)) { 2752 default: 2753 MISSING_CASE(INTEL_GEN(engine->i915)); 2754 /* fall through */ 2755 case 11: 2756 indirect_ctx_offset = 2757 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2758 break; 2759 case 10: 2760 indirect_ctx_offset = 2761 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2762 break; 2763 case 9: 2764 indirect_ctx_offset = 2765 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2766 break; 2767 case 8: 2768 indirect_ctx_offset = 2769 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; 2770 break; 2771 } 2772 2773 return indirect_ctx_offset; 2774 } 2775 2776 static void execlists_init_reg_state(u32 *regs, 2777 struct intel_context *ce, 2778 struct intel_engine_cs *engine, 2779 struct intel_ring *ring) 2780 { 2781 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->gem_context->vm); 2782 bool rcs = engine->class == RENDER_CLASS; 2783 u32 base = engine->mmio_base; 2784 2785 /* 2786 * A context is actually a big batch buffer with several 2787 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The 2788 * values we are setting here are only for the first context restore: 2789 * on a subsequent save, the GPU will recreate this batchbuffer with new 2790 * values (including all the missing MI_LOAD_REGISTER_IMM commands that 2791 * we are not initializing here). 2792 * 2793 * Must keep consistent with virtual_update_register_offsets(). 2794 */ 2795 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | 2796 MI_LRI_FORCE_POSTED; 2797 2798 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base), 2799 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) | 2800 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH)); 2801 if (INTEL_GEN(engine->i915) < 11) { 2802 regs[CTX_CONTEXT_CONTROL + 1] |= 2803 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT | 2804 CTX_CTRL_RS_CTX_ENABLE); 2805 } 2806 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0); 2807 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0); 2808 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); 2809 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), 2810 RING_CTL_SIZE(ring->size) | RING_VALID); 2811 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0); 2812 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0); 2813 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT); 2814 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0); 2815 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0); 2816 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0); 2817 if (rcs) { 2818 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; 2819 2820 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0); 2821 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET, 2822 RING_INDIRECT_CTX_OFFSET(base), 0); 2823 if (wa_ctx->indirect_ctx.size) { 2824 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); 2825 2826 regs[CTX_RCS_INDIRECT_CTX + 1] = 2827 (ggtt_offset + wa_ctx->indirect_ctx.offset) | 2828 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); 2829 2830 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = 2831 intel_lr_indirect_ctx_offset(engine) << 6; 2832 } 2833 2834 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0); 2835 if (wa_ctx->per_ctx.size) { 2836 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); 2837 2838 regs[CTX_BB_PER_CTX_PTR + 1] = 2839 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; 2840 } 2841 } 2842 2843 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; 2844 2845 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); 2846 /* PDP values well be assigned later if needed */ 2847 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0); 2848 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0); 2849 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(base, 2), 0); 2850 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(base, 2), 0); 2851 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(base, 1), 0); 2852 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(base, 1), 0); 2853 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(base, 0), 0); 2854 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(base, 0), 0); 2855 2856 if (i915_vm_is_4lvl(&ppgtt->vm)) { 2857 /* 64b PPGTT (48bit canonical) 2858 * PDP0_DESCRIPTOR contains the base address to PML4 and 2859 * other PDP Descriptors are ignored. 2860 */ 2861 ASSIGN_CTX_PML4(ppgtt, regs); 2862 } else { 2863 ASSIGN_CTX_PDP(ppgtt, regs, 3); 2864 ASSIGN_CTX_PDP(ppgtt, regs, 2); 2865 ASSIGN_CTX_PDP(ppgtt, regs, 1); 2866 ASSIGN_CTX_PDP(ppgtt, regs, 0); 2867 } 2868 2869 if (rcs) { 2870 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); 2871 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0); 2872 2873 i915_oa_init_reg_state(engine, ce, regs); 2874 } 2875 2876 regs[CTX_END] = MI_BATCH_BUFFER_END; 2877 if (INTEL_GEN(engine->i915) >= 10) 2878 regs[CTX_END] |= BIT(0); 2879 } 2880 2881 static int 2882 populate_lr_context(struct intel_context *ce, 2883 struct drm_i915_gem_object *ctx_obj, 2884 struct intel_engine_cs *engine, 2885 struct intel_ring *ring) 2886 { 2887 void *vaddr; 2888 u32 *regs; 2889 int ret; 2890 2891 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); 2892 if (IS_ERR(vaddr)) { 2893 ret = PTR_ERR(vaddr); 2894 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); 2895 return ret; 2896 } 2897 2898 if (engine->default_state) { 2899 /* 2900 * We only want to copy over the template context state; 2901 * skipping over the headers reserved for GuC communication, 2902 * leaving those as zero. 2903 */ 2904 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE; 2905 void *defaults; 2906 2907 defaults = i915_gem_object_pin_map(engine->default_state, 2908 I915_MAP_WB); 2909 if (IS_ERR(defaults)) { 2910 ret = PTR_ERR(defaults); 2911 goto err_unpin_ctx; 2912 } 2913 2914 memcpy(vaddr + start, defaults + start, engine->context_size); 2915 i915_gem_object_unpin_map(engine->default_state); 2916 } 2917 2918 /* The second page of the context object contains some fields which must 2919 * be set up prior to the first execution. */ 2920 regs = vaddr + LRC_STATE_PN * PAGE_SIZE; 2921 execlists_init_reg_state(regs, ce, engine, ring); 2922 if (!engine->default_state) 2923 regs[CTX_CONTEXT_CONTROL + 1] |= 2924 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 2925 if (ce->gem_context == engine->i915->preempt_context && 2926 INTEL_GEN(engine->i915) < 11) 2927 regs[CTX_CONTEXT_CONTROL + 1] |= 2928 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | 2929 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT); 2930 2931 ret = 0; 2932 err_unpin_ctx: 2933 __i915_gem_object_flush_map(ctx_obj, 2934 LRC_HEADER_PAGES * PAGE_SIZE, 2935 engine->context_size); 2936 i915_gem_object_unpin_map(ctx_obj); 2937 return ret; 2938 } 2939 2940 static struct i915_timeline *get_timeline(struct i915_gem_context *ctx) 2941 { 2942 if (ctx->timeline) 2943 return i915_timeline_get(ctx->timeline); 2944 else 2945 return i915_timeline_create(ctx->i915, NULL); 2946 } 2947 2948 static int execlists_context_deferred_alloc(struct intel_context *ce, 2949 struct intel_engine_cs *engine) 2950 { 2951 struct drm_i915_gem_object *ctx_obj; 2952 struct i915_vma *vma; 2953 u32 context_size; 2954 struct intel_ring *ring; 2955 struct i915_timeline *timeline; 2956 int ret; 2957 2958 if (ce->state) 2959 return 0; 2960 2961 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); 2962 2963 /* 2964 * Before the actual start of the context image, we insert a few pages 2965 * for our own use and for sharing with the GuC. 2966 */ 2967 context_size += LRC_HEADER_PAGES * PAGE_SIZE; 2968 2969 ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size); 2970 if (IS_ERR(ctx_obj)) 2971 return PTR_ERR(ctx_obj); 2972 2973 vma = i915_vma_instance(ctx_obj, &engine->i915->ggtt.vm, NULL); 2974 if (IS_ERR(vma)) { 2975 ret = PTR_ERR(vma); 2976 goto error_deref_obj; 2977 } 2978 2979 timeline = get_timeline(ce->gem_context); 2980 if (IS_ERR(timeline)) { 2981 ret = PTR_ERR(timeline); 2982 goto error_deref_obj; 2983 } 2984 2985 ring = intel_engine_create_ring(engine, 2986 timeline, 2987 ce->gem_context->ring_size); 2988 i915_timeline_put(timeline); 2989 if (IS_ERR(ring)) { 2990 ret = PTR_ERR(ring); 2991 goto error_deref_obj; 2992 } 2993 2994 ret = populate_lr_context(ce, ctx_obj, engine, ring); 2995 if (ret) { 2996 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); 2997 goto error_ring_free; 2998 } 2999 3000 ce->ring = ring; 3001 ce->state = vma; 3002 3003 return 0; 3004 3005 error_ring_free: 3006 intel_ring_put(ring); 3007 error_deref_obj: 3008 i915_gem_object_put(ctx_obj); 3009 return ret; 3010 } 3011 3012 static struct list_head *virtual_queue(struct virtual_engine *ve) 3013 { 3014 return &ve->base.execlists.default_priolist.requests[0]; 3015 } 3016 3017 static void virtual_context_destroy(struct kref *kref) 3018 { 3019 struct virtual_engine *ve = 3020 container_of(kref, typeof(*ve), context.ref); 3021 unsigned int n; 3022 3023 GEM_BUG_ON(!list_empty(virtual_queue(ve))); 3024 GEM_BUG_ON(ve->request); 3025 GEM_BUG_ON(ve->context.inflight); 3026 3027 for (n = 0; n < ve->num_siblings; n++) { 3028 struct intel_engine_cs *sibling = ve->siblings[n]; 3029 struct rb_node *node = &ve->nodes[sibling->id].rb; 3030 3031 if (RB_EMPTY_NODE(node)) 3032 continue; 3033 3034 spin_lock_irq(&sibling->active.lock); 3035 3036 /* Detachment is lazily performed in the execlists tasklet */ 3037 if (!RB_EMPTY_NODE(node)) 3038 rb_erase_cached(node, &sibling->execlists.virtual); 3039 3040 spin_unlock_irq(&sibling->active.lock); 3041 } 3042 GEM_BUG_ON(__tasklet_is_scheduled(&ve->base.execlists.tasklet)); 3043 3044 if (ve->context.state) 3045 __execlists_context_fini(&ve->context); 3046 3047 kfree(ve->bonds); 3048 kfree(ve); 3049 } 3050 3051 static void virtual_engine_initial_hint(struct virtual_engine *ve) 3052 { 3053 int swp; 3054 3055 /* 3056 * Pick a random sibling on starting to help spread the load around. 3057 * 3058 * New contexts are typically created with exactly the same order 3059 * of siblings, and often started in batches. Due to the way we iterate 3060 * the array of sibling when submitting requests, sibling[0] is 3061 * prioritised for dequeuing. If we make sure that sibling[0] is fairly 3062 * randomised across the system, we also help spread the load by the 3063 * first engine we inspect being different each time. 3064 * 3065 * NB This does not force us to execute on this engine, it will just 3066 * typically be the first we inspect for submission. 3067 */ 3068 swp = prandom_u32_max(ve->num_siblings); 3069 if (!swp) 3070 return; 3071 3072 swap(ve->siblings[swp], ve->siblings[0]); 3073 virtual_update_register_offsets(ve->context.lrc_reg_state, 3074 ve->siblings[0]); 3075 } 3076 3077 static int virtual_context_pin(struct intel_context *ce) 3078 { 3079 struct virtual_engine *ve = container_of(ce, typeof(*ve), context); 3080 int err; 3081 3082 /* Note: we must use a real engine class for setting up reg state */ 3083 err = __execlists_context_pin(ce, ve->siblings[0]); 3084 if (err) 3085 return err; 3086 3087 virtual_engine_initial_hint(ve); 3088 return 0; 3089 } 3090 3091 static void virtual_context_enter(struct intel_context *ce) 3092 { 3093 struct virtual_engine *ve = container_of(ce, typeof(*ve), context); 3094 unsigned int n; 3095 3096 for (n = 0; n < ve->num_siblings; n++) 3097 intel_engine_pm_get(ve->siblings[n]); 3098 } 3099 3100 static void virtual_context_exit(struct intel_context *ce) 3101 { 3102 struct virtual_engine *ve = container_of(ce, typeof(*ve), context); 3103 unsigned int n; 3104 3105 ce->saturated = 0; 3106 for (n = 0; n < ve->num_siblings; n++) 3107 intel_engine_pm_put(ve->siblings[n]); 3108 } 3109 3110 static const struct intel_context_ops virtual_context_ops = { 3111 .pin = virtual_context_pin, 3112 .unpin = execlists_context_unpin, 3113 3114 .enter = virtual_context_enter, 3115 .exit = virtual_context_exit, 3116 3117 .destroy = virtual_context_destroy, 3118 }; 3119 3120 static intel_engine_mask_t virtual_submission_mask(struct virtual_engine *ve) 3121 { 3122 struct i915_request *rq; 3123 intel_engine_mask_t mask; 3124 3125 rq = READ_ONCE(ve->request); 3126 if (!rq) 3127 return 0; 3128 3129 /* The rq is ready for submission; rq->execution_mask is now stable. */ 3130 mask = rq->execution_mask; 3131 if (unlikely(!mask)) { 3132 /* Invalid selection, submit to a random engine in error */ 3133 i915_request_skip(rq, -ENODEV); 3134 mask = ve->siblings[0]->mask; 3135 } 3136 3137 GEM_TRACE("%s: rq=%llx:%lld, mask=%x, prio=%d\n", 3138 ve->base.name, 3139 rq->fence.context, rq->fence.seqno, 3140 mask, ve->base.execlists.queue_priority_hint); 3141 3142 return mask; 3143 } 3144 3145 static void virtual_submission_tasklet(unsigned long data) 3146 { 3147 struct virtual_engine * const ve = (struct virtual_engine *)data; 3148 const int prio = ve->base.execlists.queue_priority_hint; 3149 intel_engine_mask_t mask; 3150 unsigned int n; 3151 3152 rcu_read_lock(); 3153 mask = virtual_submission_mask(ve); 3154 rcu_read_unlock(); 3155 if (unlikely(!mask)) 3156 return; 3157 3158 local_irq_disable(); 3159 for (n = 0; READ_ONCE(ve->request) && n < ve->num_siblings; n++) { 3160 struct intel_engine_cs *sibling = ve->siblings[n]; 3161 struct ve_node * const node = &ve->nodes[sibling->id]; 3162 struct rb_node **parent, *rb; 3163 bool first; 3164 3165 if (unlikely(!(mask & sibling->mask))) { 3166 if (!RB_EMPTY_NODE(&node->rb)) { 3167 spin_lock(&sibling->active.lock); 3168 rb_erase_cached(&node->rb, 3169 &sibling->execlists.virtual); 3170 RB_CLEAR_NODE(&node->rb); 3171 spin_unlock(&sibling->active.lock); 3172 } 3173 continue; 3174 } 3175 3176 spin_lock(&sibling->active.lock); 3177 3178 if (!RB_EMPTY_NODE(&node->rb)) { 3179 /* 3180 * Cheat and avoid rebalancing the tree if we can 3181 * reuse this node in situ. 3182 */ 3183 first = rb_first_cached(&sibling->execlists.virtual) == 3184 &node->rb; 3185 if (prio == node->prio || (prio > node->prio && first)) 3186 goto submit_engine; 3187 3188 rb_erase_cached(&node->rb, &sibling->execlists.virtual); 3189 } 3190 3191 rb = NULL; 3192 first = true; 3193 parent = &sibling->execlists.virtual.rb_root.rb_node; 3194 while (*parent) { 3195 struct ve_node *other; 3196 3197 rb = *parent; 3198 other = rb_entry(rb, typeof(*other), rb); 3199 if (prio > other->prio) { 3200 parent = &rb->rb_left; 3201 } else { 3202 parent = &rb->rb_right; 3203 first = false; 3204 } 3205 } 3206 3207 rb_link_node(&node->rb, rb, parent); 3208 rb_insert_color_cached(&node->rb, 3209 &sibling->execlists.virtual, 3210 first); 3211 3212 submit_engine: 3213 GEM_BUG_ON(RB_EMPTY_NODE(&node->rb)); 3214 node->prio = prio; 3215 if (first && prio > sibling->execlists.queue_priority_hint) { 3216 sibling->execlists.queue_priority_hint = prio; 3217 tasklet_hi_schedule(&sibling->execlists.tasklet); 3218 } 3219 3220 spin_unlock(&sibling->active.lock); 3221 } 3222 local_irq_enable(); 3223 } 3224 3225 static void virtual_submit_request(struct i915_request *rq) 3226 { 3227 struct virtual_engine *ve = to_virtual_engine(rq->engine); 3228 3229 GEM_TRACE("%s: rq=%llx:%lld\n", 3230 ve->base.name, 3231 rq->fence.context, 3232 rq->fence.seqno); 3233 3234 GEM_BUG_ON(ve->base.submit_request != virtual_submit_request); 3235 3236 GEM_BUG_ON(ve->request); 3237 GEM_BUG_ON(!list_empty(virtual_queue(ve))); 3238 3239 ve->base.execlists.queue_priority_hint = rq_prio(rq); 3240 WRITE_ONCE(ve->request, rq); 3241 3242 list_move_tail(&rq->sched.link, virtual_queue(ve)); 3243 3244 tasklet_schedule(&ve->base.execlists.tasklet); 3245 } 3246 3247 static struct ve_bond * 3248 virtual_find_bond(struct virtual_engine *ve, 3249 const struct intel_engine_cs *master) 3250 { 3251 int i; 3252 3253 for (i = 0; i < ve->num_bonds; i++) { 3254 if (ve->bonds[i].master == master) 3255 return &ve->bonds[i]; 3256 } 3257 3258 return NULL; 3259 } 3260 3261 static void 3262 virtual_bond_execute(struct i915_request *rq, struct dma_fence *signal) 3263 { 3264 struct virtual_engine *ve = to_virtual_engine(rq->engine); 3265 struct ve_bond *bond; 3266 3267 bond = virtual_find_bond(ve, to_request(signal)->engine); 3268 if (bond) { 3269 intel_engine_mask_t old, new, cmp; 3270 3271 cmp = READ_ONCE(rq->execution_mask); 3272 do { 3273 old = cmp; 3274 new = cmp & bond->sibling_mask; 3275 } while ((cmp = cmpxchg(&rq->execution_mask, old, new)) != old); 3276 } 3277 } 3278 3279 struct intel_context * 3280 intel_execlists_create_virtual(struct i915_gem_context *ctx, 3281 struct intel_engine_cs **siblings, 3282 unsigned int count) 3283 { 3284 struct virtual_engine *ve; 3285 unsigned int n; 3286 int err; 3287 3288 if (count == 0) 3289 return ERR_PTR(-EINVAL); 3290 3291 if (count == 1) 3292 return intel_context_create(ctx, siblings[0]); 3293 3294 ve = kzalloc(struct_size(ve, siblings, count), GFP_KERNEL); 3295 if (!ve) 3296 return ERR_PTR(-ENOMEM); 3297 3298 ve->base.i915 = ctx->i915; 3299 ve->base.id = -1; 3300 ve->base.class = OTHER_CLASS; 3301 ve->base.uabi_class = I915_ENGINE_CLASS_INVALID; 3302 ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL; 3303 ve->base.flags = I915_ENGINE_IS_VIRTUAL; 3304 3305 snprintf(ve->base.name, sizeof(ve->base.name), "virtual"); 3306 3307 intel_engine_init_active(&ve->base, ENGINE_VIRTUAL); 3308 3309 intel_engine_init_execlists(&ve->base); 3310 3311 ve->base.cops = &virtual_context_ops; 3312 ve->base.request_alloc = execlists_request_alloc; 3313 3314 ve->base.schedule = i915_schedule; 3315 ve->base.submit_request = virtual_submit_request; 3316 ve->base.bond_execute = virtual_bond_execute; 3317 3318 INIT_LIST_HEAD(virtual_queue(ve)); 3319 ve->base.execlists.queue_priority_hint = INT_MIN; 3320 tasklet_init(&ve->base.execlists.tasklet, 3321 virtual_submission_tasklet, 3322 (unsigned long)ve); 3323 3324 intel_context_init(&ve->context, ctx, &ve->base); 3325 3326 for (n = 0; n < count; n++) { 3327 struct intel_engine_cs *sibling = siblings[n]; 3328 3329 GEM_BUG_ON(!is_power_of_2(sibling->mask)); 3330 if (sibling->mask & ve->base.mask) { 3331 DRM_DEBUG("duplicate %s entry in load balancer\n", 3332 sibling->name); 3333 err = -EINVAL; 3334 goto err_put; 3335 } 3336 3337 /* 3338 * The virtual engine implementation is tightly coupled to 3339 * the execlists backend -- we push out request directly 3340 * into a tree inside each physical engine. We could support 3341 * layering if we handle cloning of the requests and 3342 * submitting a copy into each backend. 3343 */ 3344 if (sibling->execlists.tasklet.func != 3345 execlists_submission_tasklet) { 3346 err = -ENODEV; 3347 goto err_put; 3348 } 3349 3350 GEM_BUG_ON(RB_EMPTY_NODE(&ve->nodes[sibling->id].rb)); 3351 RB_CLEAR_NODE(&ve->nodes[sibling->id].rb); 3352 3353 ve->siblings[ve->num_siblings++] = sibling; 3354 ve->base.mask |= sibling->mask; 3355 3356 /* 3357 * All physical engines must be compatible for their emission 3358 * functions (as we build the instructions during request 3359 * construction and do not alter them before submission 3360 * on the physical engine). We use the engine class as a guide 3361 * here, although that could be refined. 3362 */ 3363 if (ve->base.class != OTHER_CLASS) { 3364 if (ve->base.class != sibling->class) { 3365 DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n", 3366 sibling->class, ve->base.class); 3367 err = -EINVAL; 3368 goto err_put; 3369 } 3370 continue; 3371 } 3372 3373 ve->base.class = sibling->class; 3374 ve->base.uabi_class = sibling->uabi_class; 3375 snprintf(ve->base.name, sizeof(ve->base.name), 3376 "v%dx%d", ve->base.class, count); 3377 ve->base.context_size = sibling->context_size; 3378 3379 ve->base.emit_bb_start = sibling->emit_bb_start; 3380 ve->base.emit_flush = sibling->emit_flush; 3381 ve->base.emit_init_breadcrumb = sibling->emit_init_breadcrumb; 3382 ve->base.emit_fini_breadcrumb = sibling->emit_fini_breadcrumb; 3383 ve->base.emit_fini_breadcrumb_dw = 3384 sibling->emit_fini_breadcrumb_dw; 3385 } 3386 3387 return &ve->context; 3388 3389 err_put: 3390 intel_context_put(&ve->context); 3391 return ERR_PTR(err); 3392 } 3393 3394 struct intel_context * 3395 intel_execlists_clone_virtual(struct i915_gem_context *ctx, 3396 struct intel_engine_cs *src) 3397 { 3398 struct virtual_engine *se = to_virtual_engine(src); 3399 struct intel_context *dst; 3400 3401 dst = intel_execlists_create_virtual(ctx, 3402 se->siblings, 3403 se->num_siblings); 3404 if (IS_ERR(dst)) 3405 return dst; 3406 3407 if (se->num_bonds) { 3408 struct virtual_engine *de = to_virtual_engine(dst->engine); 3409 3410 de->bonds = kmemdup(se->bonds, 3411 sizeof(*se->bonds) * se->num_bonds, 3412 GFP_KERNEL); 3413 if (!de->bonds) { 3414 intel_context_put(dst); 3415 return ERR_PTR(-ENOMEM); 3416 } 3417 3418 de->num_bonds = se->num_bonds; 3419 } 3420 3421 return dst; 3422 } 3423 3424 int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine, 3425 const struct intel_engine_cs *master, 3426 const struct intel_engine_cs *sibling) 3427 { 3428 struct virtual_engine *ve = to_virtual_engine(engine); 3429 struct ve_bond *bond; 3430 int n; 3431 3432 /* Sanity check the sibling is part of the virtual engine */ 3433 for (n = 0; n < ve->num_siblings; n++) 3434 if (sibling == ve->siblings[n]) 3435 break; 3436 if (n == ve->num_siblings) 3437 return -EINVAL; 3438 3439 bond = virtual_find_bond(ve, master); 3440 if (bond) { 3441 bond->sibling_mask |= sibling->mask; 3442 return 0; 3443 } 3444 3445 bond = krealloc(ve->bonds, 3446 sizeof(*bond) * (ve->num_bonds + 1), 3447 GFP_KERNEL); 3448 if (!bond) 3449 return -ENOMEM; 3450 3451 bond[ve->num_bonds].master = master; 3452 bond[ve->num_bonds].sibling_mask = sibling->mask; 3453 3454 ve->bonds = bond; 3455 ve->num_bonds++; 3456 3457 return 0; 3458 } 3459 3460 void intel_execlists_show_requests(struct intel_engine_cs *engine, 3461 struct drm_printer *m, 3462 void (*show_request)(struct drm_printer *m, 3463 struct i915_request *rq, 3464 const char *prefix), 3465 unsigned int max) 3466 { 3467 const struct intel_engine_execlists *execlists = &engine->execlists; 3468 struct i915_request *rq, *last; 3469 unsigned long flags; 3470 unsigned int count; 3471 struct rb_node *rb; 3472 3473 spin_lock_irqsave(&engine->active.lock, flags); 3474 3475 last = NULL; 3476 count = 0; 3477 list_for_each_entry(rq, &engine->active.requests, sched.link) { 3478 if (count++ < max - 1) 3479 show_request(m, rq, "\t\tE "); 3480 else 3481 last = rq; 3482 } 3483 if (last) { 3484 if (count > max) { 3485 drm_printf(m, 3486 "\t\t...skipping %d executing requests...\n", 3487 count - max); 3488 } 3489 show_request(m, last, "\t\tE "); 3490 } 3491 3492 last = NULL; 3493 count = 0; 3494 if (execlists->queue_priority_hint != INT_MIN) 3495 drm_printf(m, "\t\tQueue priority hint: %d\n", 3496 execlists->queue_priority_hint); 3497 for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) { 3498 struct i915_priolist *p = rb_entry(rb, typeof(*p), node); 3499 int i; 3500 3501 priolist_for_each_request(rq, p, i) { 3502 if (count++ < max - 1) 3503 show_request(m, rq, "\t\tQ "); 3504 else 3505 last = rq; 3506 } 3507 } 3508 if (last) { 3509 if (count > max) { 3510 drm_printf(m, 3511 "\t\t...skipping %d queued requests...\n", 3512 count - max); 3513 } 3514 show_request(m, last, "\t\tQ "); 3515 } 3516 3517 last = NULL; 3518 count = 0; 3519 for (rb = rb_first_cached(&execlists->virtual); rb; rb = rb_next(rb)) { 3520 struct virtual_engine *ve = 3521 rb_entry(rb, typeof(*ve), nodes[engine->id].rb); 3522 struct i915_request *rq = READ_ONCE(ve->request); 3523 3524 if (rq) { 3525 if (count++ < max - 1) 3526 show_request(m, rq, "\t\tV "); 3527 else 3528 last = rq; 3529 } 3530 } 3531 if (last) { 3532 if (count > max) { 3533 drm_printf(m, 3534 "\t\t...skipping %d virtual requests...\n", 3535 count - max); 3536 } 3537 show_request(m, last, "\t\tV "); 3538 } 3539 3540 spin_unlock_irqrestore(&engine->active.lock, flags); 3541 } 3542 3543 void intel_lr_context_reset(struct intel_engine_cs *engine, 3544 struct intel_context *ce, 3545 u32 head, 3546 bool scrub) 3547 { 3548 /* 3549 * We want a simple context + ring to execute the breadcrumb update. 3550 * We cannot rely on the context being intact across the GPU hang, 3551 * so clear it and rebuild just what we need for the breadcrumb. 3552 * All pending requests for this context will be zapped, and any 3553 * future request will be after userspace has had the opportunity 3554 * to recreate its own state. 3555 */ 3556 if (scrub) { 3557 u32 *regs = ce->lrc_reg_state; 3558 3559 if (engine->pinned_default_state) { 3560 memcpy(regs, /* skip restoring the vanilla PPHWSP */ 3561 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE, 3562 engine->context_size - PAGE_SIZE); 3563 } 3564 execlists_init_reg_state(regs, ce, engine, ce->ring); 3565 } 3566 3567 /* Rerun the request; its payload has been neutered (if guilty). */ 3568 ce->ring->head = head; 3569 intel_ring_update_space(ce->ring); 3570 3571 __execlists_update_reg_state(ce, engine); 3572 } 3573 3574 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 3575 #include "selftest_lrc.c" 3576 #endif 3577