1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <asm/tsc.h> 7 #include <linux/cpufreq.h> 8 9 #include "i915_drv.h" 10 #include "i915_reg.h" 11 #include "intel_gt.h" 12 #include "intel_llc.h" 13 #include "intel_pcode.h" 14 15 struct ia_constants { 16 unsigned int min_gpu_freq; 17 unsigned int max_gpu_freq; 18 19 unsigned int min_ring_freq; 20 unsigned int max_ia_freq; 21 }; 22 23 static struct intel_gt *llc_to_gt(struct intel_llc *llc) 24 { 25 return container_of(llc, struct intel_gt, llc); 26 } 27 28 static unsigned int cpu_max_MHz(void) 29 { 30 struct cpufreq_policy *policy; 31 unsigned int max_khz; 32 33 policy = cpufreq_cpu_get(0); 34 if (policy) { 35 max_khz = policy->cpuinfo.max_freq; 36 cpufreq_cpu_put(policy); 37 } else { 38 /* 39 * Default to measured freq if none found, PCU will ensure we 40 * don't go over 41 */ 42 max_khz = tsc_khz; 43 } 44 45 return max_khz / 1000; 46 } 47 48 static bool get_ia_constants(struct intel_llc *llc, 49 struct ia_constants *consts) 50 { 51 struct drm_i915_private *i915 = llc_to_gt(llc)->i915; 52 struct intel_rps *rps = &llc_to_gt(llc)->rps; 53 54 if (!HAS_LLC(i915) || IS_DGFX(i915)) 55 return false; 56 57 if (rps->max_freq <= rps->min_freq) 58 return false; 59 60 consts->max_ia_freq = cpu_max_MHz(); 61 62 consts->min_ring_freq = 63 intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf; 64 /* convert DDR frequency from units of 266.6MHz to bandwidth */ 65 consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3); 66 67 consts->min_gpu_freq = rps->min_freq; 68 consts->max_gpu_freq = rps->max_freq; 69 if (GRAPHICS_VER(i915) >= 9) { 70 /* Convert GT frequency to 50 HZ units */ 71 consts->min_gpu_freq /= GEN9_FREQ_SCALER; 72 consts->max_gpu_freq /= GEN9_FREQ_SCALER; 73 } 74 75 return true; 76 } 77 78 static void calc_ia_freq(struct intel_llc *llc, 79 unsigned int gpu_freq, 80 const struct ia_constants *consts, 81 unsigned int *out_ia_freq, 82 unsigned int *out_ring_freq) 83 { 84 struct drm_i915_private *i915 = llc_to_gt(llc)->i915; 85 const int diff = consts->max_gpu_freq - gpu_freq; 86 unsigned int ia_freq = 0, ring_freq = 0; 87 88 if (GRAPHICS_VER(i915) >= 9) { 89 /* 90 * ring_freq = 2 * GT. ring_freq is in 100MHz units 91 * No floor required for ring frequency on SKL. 92 */ 93 ring_freq = gpu_freq; 94 } else if (GRAPHICS_VER(i915) >= 8) { 95 /* max(2 * GT, DDR). NB: GT is 50MHz units */ 96 ring_freq = max(consts->min_ring_freq, gpu_freq); 97 } else if (IS_HASWELL(i915)) { 98 ring_freq = mult_frac(gpu_freq, 5, 4); 99 ring_freq = max(consts->min_ring_freq, ring_freq); 100 /* leave ia_freq as the default, chosen by cpufreq */ 101 } else { 102 const int min_freq = 15; 103 const int scale = 180; 104 105 /* 106 * On older processors, there is no separate ring 107 * clock domain, so in order to boost the bandwidth 108 * of the ring, we need to upclock the CPU (ia_freq). 109 * 110 * For GPU frequencies less than 750MHz, 111 * just use the lowest ring freq. 112 */ 113 if (gpu_freq < min_freq) 114 ia_freq = 800; 115 else 116 ia_freq = consts->max_ia_freq - diff * scale / 2; 117 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 118 } 119 120 *out_ia_freq = ia_freq; 121 *out_ring_freq = ring_freq; 122 } 123 124 static void gen6_update_ring_freq(struct intel_llc *llc) 125 { 126 struct drm_i915_private *i915 = llc_to_gt(llc)->i915; 127 struct ia_constants consts; 128 unsigned int gpu_freq; 129 130 if (!get_ia_constants(llc, &consts)) 131 return; 132 133 /* 134 * For each potential GPU frequency, load a ring frequency we'd like 135 * to use for memory access. We do this by specifying the IA frequency 136 * the PCU should use as a reference to determine the ring frequency. 137 */ 138 for (gpu_freq = consts.max_gpu_freq; 139 gpu_freq >= consts.min_gpu_freq; 140 gpu_freq--) { 141 unsigned int ia_freq, ring_freq; 142 143 calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq); 144 snb_pcode_write(i915, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 145 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | 146 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | 147 gpu_freq); 148 } 149 } 150 151 void intel_llc_enable(struct intel_llc *llc) 152 { 153 gen6_update_ring_freq(llc); 154 } 155 156 void intel_llc_disable(struct intel_llc *llc) 157 { 158 /* Currently there is no HW configuration to be done to disable. */ 159 } 160 161 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 162 #include "selftest_llc.c" 163 #endif 164