1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2019 Intel Corporation 5 */ 6 7 #include <linux/cpufreq.h> 8 9 #include "i915_drv.h" 10 #include "intel_gt.h" 11 #include "intel_llc.h" 12 #include "intel_sideband.h" 13 14 struct ia_constants { 15 unsigned int min_gpu_freq; 16 unsigned int max_gpu_freq; 17 18 unsigned int min_ring_freq; 19 unsigned int max_ia_freq; 20 }; 21 22 static struct intel_gt *llc_to_gt(struct intel_llc *llc) 23 { 24 return container_of(llc, struct intel_gt, llc); 25 } 26 27 static unsigned int cpu_max_MHz(void) 28 { 29 struct cpufreq_policy *policy; 30 unsigned int max_khz; 31 32 policy = cpufreq_cpu_get(0); 33 if (policy) { 34 max_khz = policy->cpuinfo.max_freq; 35 cpufreq_cpu_put(policy); 36 } else { 37 /* 38 * Default to measured freq if none found, PCU will ensure we 39 * don't go over 40 */ 41 max_khz = tsc_khz; 42 } 43 44 return max_khz / 1000; 45 } 46 47 static bool get_ia_constants(struct intel_llc *llc, 48 struct ia_constants *consts) 49 { 50 struct drm_i915_private *i915 = llc_to_gt(llc)->i915; 51 struct intel_rps *rps = &llc_to_gt(llc)->rps; 52 53 if (!HAS_LLC(i915) || IS_DGFX(i915)) 54 return false; 55 56 if (rps->max_freq <= rps->min_freq) 57 return false; 58 59 consts->max_ia_freq = cpu_max_MHz(); 60 61 consts->min_ring_freq = 62 intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf; 63 /* convert DDR frequency from units of 266.6MHz to bandwidth */ 64 consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3); 65 66 consts->min_gpu_freq = rps->min_freq; 67 consts->max_gpu_freq = rps->max_freq; 68 if (INTEL_GEN(i915) >= 9) { 69 /* Convert GT frequency to 50 HZ units */ 70 consts->min_gpu_freq /= GEN9_FREQ_SCALER; 71 consts->max_gpu_freq /= GEN9_FREQ_SCALER; 72 } 73 74 return true; 75 } 76 77 static void calc_ia_freq(struct intel_llc *llc, 78 unsigned int gpu_freq, 79 const struct ia_constants *consts, 80 unsigned int *out_ia_freq, 81 unsigned int *out_ring_freq) 82 { 83 struct drm_i915_private *i915 = llc_to_gt(llc)->i915; 84 const int diff = consts->max_gpu_freq - gpu_freq; 85 unsigned int ia_freq = 0, ring_freq = 0; 86 87 if (INTEL_GEN(i915) >= 9) { 88 /* 89 * ring_freq = 2 * GT. ring_freq is in 100MHz units 90 * No floor required for ring frequency on SKL. 91 */ 92 ring_freq = gpu_freq; 93 } else if (INTEL_GEN(i915) >= 8) { 94 /* max(2 * GT, DDR). NB: GT is 50MHz units */ 95 ring_freq = max(consts->min_ring_freq, gpu_freq); 96 } else if (IS_HASWELL(i915)) { 97 ring_freq = mult_frac(gpu_freq, 5, 4); 98 ring_freq = max(consts->min_ring_freq, ring_freq); 99 /* leave ia_freq as the default, chosen by cpufreq */ 100 } else { 101 const int min_freq = 15; 102 const int scale = 180; 103 104 /* 105 * On older processors, there is no separate ring 106 * clock domain, so in order to boost the bandwidth 107 * of the ring, we need to upclock the CPU (ia_freq). 108 * 109 * For GPU frequencies less than 750MHz, 110 * just use the lowest ring freq. 111 */ 112 if (gpu_freq < min_freq) 113 ia_freq = 800; 114 else 115 ia_freq = consts->max_ia_freq - diff * scale / 2; 116 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 117 } 118 119 *out_ia_freq = ia_freq; 120 *out_ring_freq = ring_freq; 121 } 122 123 static void gen6_update_ring_freq(struct intel_llc *llc) 124 { 125 struct drm_i915_private *i915 = llc_to_gt(llc)->i915; 126 struct ia_constants consts; 127 unsigned int gpu_freq; 128 129 if (!get_ia_constants(llc, &consts)) 130 return; 131 132 /* 133 * For each potential GPU frequency, load a ring frequency we'd like 134 * to use for memory access. We do this by specifying the IA frequency 135 * the PCU should use as a reference to determine the ring frequency. 136 */ 137 for (gpu_freq = consts.max_gpu_freq; 138 gpu_freq >= consts.min_gpu_freq; 139 gpu_freq--) { 140 unsigned int ia_freq, ring_freq; 141 142 calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq); 143 sandybridge_pcode_write(i915, 144 GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 145 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | 146 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | 147 gpu_freq); 148 } 149 } 150 151 void intel_llc_enable(struct intel_llc *llc) 152 { 153 gen6_update_ring_freq(llc); 154 } 155 156 void intel_llc_disable(struct intel_llc *llc) 157 { 158 /* Currently there is no HW configuration to be done to disable. */ 159 } 160 161 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 162 #include "selftest_llc.c" 163 #endif 164