1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <asm/tsc.h> 7 #include <linux/cpufreq.h> 8 9 #include "i915_drv.h" 10 #include "i915_reg.h" 11 #include "intel_gt.h" 12 #include "intel_llc.h" 13 #include "intel_mchbar_regs.h" 14 #include "intel_pcode.h" 15 16 struct ia_constants { 17 unsigned int min_gpu_freq; 18 unsigned int max_gpu_freq; 19 20 unsigned int min_ring_freq; 21 unsigned int max_ia_freq; 22 }; 23 24 static struct intel_gt *llc_to_gt(struct intel_llc *llc) 25 { 26 return container_of(llc, struct intel_gt, llc); 27 } 28 29 static unsigned int cpu_max_MHz(void) 30 { 31 struct cpufreq_policy *policy; 32 unsigned int max_khz; 33 34 policy = cpufreq_cpu_get(0); 35 if (policy) { 36 max_khz = policy->cpuinfo.max_freq; 37 cpufreq_cpu_put(policy); 38 } else { 39 /* 40 * Default to measured freq if none found, PCU will ensure we 41 * don't go over 42 */ 43 max_khz = tsc_khz; 44 } 45 46 return max_khz / 1000; 47 } 48 49 static bool get_ia_constants(struct intel_llc *llc, 50 struct ia_constants *consts) 51 { 52 struct drm_i915_private *i915 = llc_to_gt(llc)->i915; 53 struct intel_rps *rps = &llc_to_gt(llc)->rps; 54 55 if (!HAS_LLC(i915) || IS_DGFX(i915)) 56 return false; 57 58 if (rps->max_freq <= rps->min_freq) 59 return false; 60 61 consts->max_ia_freq = cpu_max_MHz(); 62 63 consts->min_ring_freq = 64 intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf; 65 /* convert DDR frequency from units of 266.6MHz to bandwidth */ 66 consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3); 67 68 consts->min_gpu_freq = rps->min_freq; 69 consts->max_gpu_freq = rps->max_freq; 70 if (GRAPHICS_VER(i915) >= 9) { 71 /* Convert GT frequency to 50 HZ units */ 72 consts->min_gpu_freq /= GEN9_FREQ_SCALER; 73 consts->max_gpu_freq /= GEN9_FREQ_SCALER; 74 } 75 76 return true; 77 } 78 79 static void calc_ia_freq(struct intel_llc *llc, 80 unsigned int gpu_freq, 81 const struct ia_constants *consts, 82 unsigned int *out_ia_freq, 83 unsigned int *out_ring_freq) 84 { 85 struct drm_i915_private *i915 = llc_to_gt(llc)->i915; 86 const int diff = consts->max_gpu_freq - gpu_freq; 87 unsigned int ia_freq = 0, ring_freq = 0; 88 89 if (GRAPHICS_VER(i915) >= 9) { 90 /* 91 * ring_freq = 2 * GT. ring_freq is in 100MHz units 92 * No floor required for ring frequency on SKL. 93 */ 94 ring_freq = gpu_freq; 95 } else if (GRAPHICS_VER(i915) >= 8) { 96 /* max(2 * GT, DDR). NB: GT is 50MHz units */ 97 ring_freq = max(consts->min_ring_freq, gpu_freq); 98 } else if (IS_HASWELL(i915)) { 99 ring_freq = mult_frac(gpu_freq, 5, 4); 100 ring_freq = max(consts->min_ring_freq, ring_freq); 101 /* leave ia_freq as the default, chosen by cpufreq */ 102 } else { 103 const int min_freq = 15; 104 const int scale = 180; 105 106 /* 107 * On older processors, there is no separate ring 108 * clock domain, so in order to boost the bandwidth 109 * of the ring, we need to upclock the CPU (ia_freq). 110 * 111 * For GPU frequencies less than 750MHz, 112 * just use the lowest ring freq. 113 */ 114 if (gpu_freq < min_freq) 115 ia_freq = 800; 116 else 117 ia_freq = consts->max_ia_freq - diff * scale / 2; 118 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 119 } 120 121 *out_ia_freq = ia_freq; 122 *out_ring_freq = ring_freq; 123 } 124 125 static void gen6_update_ring_freq(struct intel_llc *llc) 126 { 127 struct drm_i915_private *i915 = llc_to_gt(llc)->i915; 128 struct ia_constants consts; 129 unsigned int gpu_freq; 130 131 if (!get_ia_constants(llc, &consts)) 132 return; 133 134 /* 135 * For each potential GPU frequency, load a ring frequency we'd like 136 * to use for memory access. We do this by specifying the IA frequency 137 * the PCU should use as a reference to determine the ring frequency. 138 */ 139 for (gpu_freq = consts.max_gpu_freq; 140 gpu_freq >= consts.min_gpu_freq; 141 gpu_freq--) { 142 unsigned int ia_freq, ring_freq; 143 144 calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq); 145 snb_pcode_write(i915, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 146 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | 147 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | 148 gpu_freq); 149 } 150 } 151 152 void intel_llc_enable(struct intel_llc *llc) 153 { 154 gen6_update_ring_freq(llc); 155 } 156 157 void intel_llc_disable(struct intel_llc *llc) 158 { 159 /* Currently there is no HW configuration to be done to disable. */ 160 } 161 162 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 163 #include "selftest_llc.c" 164 #endif 165