1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * Please try to maintain the following order within this file unless it makes 6 * sense to do otherwise. From top to bottom: 7 * 1. typedefs 8 * 2. #defines, and macros 9 * 3. structure definitions 10 * 4. function prototypes 11 * 12 * Within each section, please try to order by generation in ascending order, 13 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 14 */ 15 16 #ifndef __INTEL_GTT_H__ 17 #define __INTEL_GTT_H__ 18 19 #include <linux/io-mapping.h> 20 #include <linux/kref.h> 21 #include <linux/mm.h> 22 #include <linux/pagevec.h> 23 #include <linux/scatterlist.h> 24 #include <linux/workqueue.h> 25 26 #include <drm/drm_mm.h> 27 28 #include "gt/intel_reset.h" 29 #include "i915_selftest.h" 30 #include "i915_vma_types.h" 31 32 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 33 34 #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT) 35 #define DBG(...) trace_printk(__VA_ARGS__) 36 #else 37 #define DBG(...) 38 #endif 39 40 #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */ 41 42 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) 43 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) 44 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) 45 46 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 47 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 48 49 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE 50 51 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 52 53 #define I915_FENCE_REG_NONE -1 54 #define I915_MAX_NUM_FENCES 32 55 /* 32 fences + sign bit for FENCE_REG_NONE */ 56 #define I915_MAX_NUM_FENCE_BITS 6 57 58 typedef u32 gen6_pte_t; 59 typedef u64 gen8_pte_t; 60 61 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT) 62 63 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 64 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 65 #define I915_PDES 512 66 #define I915_PDE_MASK (I915_PDES - 1) 67 68 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 69 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 70 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 71 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 72 #define GEN6_PTE_CACHE_LLC (2 << 1) 73 #define GEN6_PTE_UNCACHED (1 << 1) 74 #define GEN6_PTE_VALID REG_BIT(0) 75 76 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 77 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 78 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 79 #define GEN6_PDE_SHIFT 22 80 #define GEN6_PDE_VALID REG_BIT(0) 81 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 82 83 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 84 85 #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2) 86 #define BYT_PTE_WRITEABLE REG_BIT(1) 87 88 /* 89 * Cacheability Control is a 4-bit value. The low three bits are stored in bits 90 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 91 */ 92 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 93 (((bits) & 0x8) << (11 - 3))) 94 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 95 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 96 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 97 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 98 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 99 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 100 #define HSW_PTE_UNCACHED (0) 101 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 102 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 103 104 /* 105 * GEN8 32b style address is defined as a 3 level page table: 106 * 31:30 | 29:21 | 20:12 | 11:0 107 * PDPE | PDE | PTE | offset 108 * The difference as compared to normal x86 3 level page table is the PDPEs are 109 * programmed via register. 110 * 111 * GEN8 48b style address is defined as a 4 level page table: 112 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 113 * PML4E | PDPE | PDE | PTE | offset 114 */ 115 #define GEN8_3LVL_PDPES 4 116 117 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 118 #define PPAT_CACHED_PDE 0 /* WB LLC */ 119 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 120 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 121 122 #define CHV_PPAT_SNOOP REG_BIT(6) 123 #define GEN8_PPAT_AGE(x) ((x)<<4) 124 #define GEN8_PPAT_LLCeLLC (3<<2) 125 #define GEN8_PPAT_LLCELLC (2<<2) 126 #define GEN8_PPAT_LLC (1<<2) 127 #define GEN8_PPAT_WB (3<<0) 128 #define GEN8_PPAT_WT (2<<0) 129 #define GEN8_PPAT_WC (1<<0) 130 #define GEN8_PPAT_UC (0<<0) 131 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 132 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 133 134 #define GEN8_PDE_IPS_64K BIT(11) 135 #define GEN8_PDE_PS_2M BIT(7) 136 137 struct i915_fence_reg; 138 139 #define for_each_sgt_daddr(__dp, __iter, __sgt) \ 140 __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE) 141 142 struct i915_page_dma { 143 struct page *page; 144 union { 145 dma_addr_t daddr; 146 147 /* 148 * For gen6/gen7 only. This is the offset in the GGTT 149 * where the page directory entries for PPGTT begin 150 */ 151 u32 ggtt_offset; 152 }; 153 }; 154 155 struct i915_page_scratch { 156 struct i915_page_dma base; 157 u64 encode; 158 }; 159 160 struct i915_page_table { 161 struct i915_page_dma base; 162 atomic_t used; 163 }; 164 165 struct i915_page_directory { 166 struct i915_page_table pt; 167 spinlock_t lock; 168 void *entry[512]; 169 }; 170 171 #define __px_choose_expr(x, type, expr, other) \ 172 __builtin_choose_expr( \ 173 __builtin_types_compatible_p(typeof(x), type) || \ 174 __builtin_types_compatible_p(typeof(x), const type), \ 175 ({ type __x = (type)(x); expr; }), \ 176 other) 177 178 #define px_base(px) \ 179 __px_choose_expr(px, struct i915_page_dma *, __x, \ 180 __px_choose_expr(px, struct i915_page_scratch *, &__x->base, \ 181 __px_choose_expr(px, struct i915_page_table *, &__x->base, \ 182 __px_choose_expr(px, struct i915_page_directory *, &__x->pt.base, \ 183 (void)0)))) 184 #define px_dma(px) (px_base(px)->daddr) 185 186 #define px_pt(px) \ 187 __px_choose_expr(px, struct i915_page_table *, __x, \ 188 __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \ 189 (void)0)) 190 #define px_used(px) (&px_pt(px)->used) 191 192 enum i915_cache_level; 193 194 struct drm_i915_file_private; 195 struct drm_i915_gem_object; 196 struct i915_vma; 197 struct intel_gt; 198 199 struct i915_vma_ops { 200 /* Map an object into an address space with the given cache flags. */ 201 int (*bind_vma)(struct i915_address_space *vm, 202 struct i915_vma *vma, 203 enum i915_cache_level cache_level, 204 u32 flags); 205 /* 206 * Unmap an object from an address space. This usually consists of 207 * setting the valid PTE entries to a reserved scratch page. 208 */ 209 void (*unbind_vma)(struct i915_address_space *vm, 210 struct i915_vma *vma); 211 212 int (*set_pages)(struct i915_vma *vma); 213 void (*clear_pages)(struct i915_vma *vma); 214 }; 215 216 struct pagestash { 217 spinlock_t lock; 218 struct pagevec pvec; 219 }; 220 221 void stash_init(struct pagestash *stash); 222 223 struct i915_address_space { 224 struct kref ref; 225 struct rcu_work rcu; 226 227 struct drm_mm mm; 228 struct intel_gt *gt; 229 struct drm_i915_private *i915; 230 struct device *dma; 231 /* 232 * Every address space belongs to a struct file - except for the global 233 * GTT that is owned by the driver (and so @file is set to NULL). In 234 * principle, no information should leak from one context to another 235 * (or between files/processes etc) unless explicitly shared by the 236 * owner. Tracking the owner is important in order to free up per-file 237 * objects along with the file, to aide resource tracking, and to 238 * assign blame. 239 */ 240 struct drm_i915_file_private *file; 241 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 242 u64 reserved; /* size addr space reserved */ 243 244 unsigned int bind_async_flags; 245 246 /* 247 * Each active user context has its own address space (in full-ppgtt). 248 * Since the vm may be shared between multiple contexts, we count how 249 * many contexts keep us "open". Once open hits zero, we are closed 250 * and do not allow any new attachments, and proceed to shutdown our 251 * vma and page directories. 252 */ 253 atomic_t open; 254 255 struct mutex mutex; /* protects vma and our lists */ 256 #define VM_CLASS_GGTT 0 257 #define VM_CLASS_PPGTT 1 258 259 struct i915_page_scratch scratch[4]; 260 unsigned int scratch_order; 261 unsigned int top; 262 263 /** 264 * List of vma currently bound. 265 */ 266 struct list_head bound_list; 267 268 struct pagestash free_pages; 269 270 /* Global GTT */ 271 bool is_ggtt:1; 272 273 /* Some systems require uncached updates of the page directories */ 274 bool pt_kmap_wc:1; 275 276 /* Some systems support read-only mappings for GGTT and/or PPGTT */ 277 bool has_read_only:1; 278 279 u64 (*pte_encode)(dma_addr_t addr, 280 enum i915_cache_level level, 281 u32 flags); /* Create a valid PTE */ 282 #define PTE_READ_ONLY BIT(0) 283 284 int (*allocate_va_range)(struct i915_address_space *vm, 285 u64 start, u64 length); 286 void (*clear_range)(struct i915_address_space *vm, 287 u64 start, u64 length); 288 void (*insert_page)(struct i915_address_space *vm, 289 dma_addr_t addr, 290 u64 offset, 291 enum i915_cache_level cache_level, 292 u32 flags); 293 void (*insert_entries)(struct i915_address_space *vm, 294 struct i915_vma *vma, 295 enum i915_cache_level cache_level, 296 u32 flags); 297 void (*cleanup)(struct i915_address_space *vm); 298 299 struct i915_vma_ops vma_ops; 300 301 I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 302 I915_SELFTEST_DECLARE(bool scrub_64K); 303 }; 304 305 /* 306 * The Graphics Translation Table is the way in which GEN hardware translates a 307 * Graphics Virtual Address into a Physical Address. In addition to the normal 308 * collateral associated with any va->pa translations GEN hardware also has a 309 * portion of the GTT which can be mapped by the CPU and remain both coherent 310 * and correct (in cases like swizzling). That region is referred to as GMADR in 311 * the spec. 312 */ 313 struct i915_ggtt { 314 struct i915_address_space vm; 315 316 struct io_mapping iomap; /* Mapping to our CPU mappable region */ 317 struct resource gmadr; /* GMADR resource */ 318 resource_size_t mappable_end; /* End offset that we can CPU map */ 319 320 /** "Graphics Stolen Memory" holds the global PTEs */ 321 void __iomem *gsm; 322 void (*invalidate)(struct i915_ggtt *ggtt); 323 324 /** PPGTT used for aliasing the PPGTT with the GTT */ 325 struct i915_ppgtt *alias; 326 327 bool do_idle_maps; 328 329 int mtrr; 330 331 /** Bit 6 swizzling required for X tiling */ 332 u32 bit_6_swizzle_x; 333 /** Bit 6 swizzling required for Y tiling */ 334 u32 bit_6_swizzle_y; 335 336 u32 pin_bias; 337 338 unsigned int num_fences; 339 struct i915_fence_reg *fence_regs; 340 struct list_head fence_list; 341 342 /** 343 * List of all objects in gtt_space, currently mmaped by userspace. 344 * All objects within this list must also be on bound_list. 345 */ 346 struct list_head userfault_list; 347 348 /* Manual runtime pm autosuspend delay for user GGTT mmaps */ 349 struct intel_wakeref_auto userfault_wakeref; 350 351 struct mutex error_mutex; 352 struct drm_mm_node error_capture; 353 struct drm_mm_node uc_fw; 354 }; 355 356 struct i915_ppgtt { 357 struct i915_address_space vm; 358 359 struct i915_page_directory *pd; 360 }; 361 362 #define i915_is_ggtt(vm) ((vm)->is_ggtt) 363 364 static inline bool 365 i915_vm_is_4lvl(const struct i915_address_space *vm) 366 { 367 return (vm->total - 1) >> 32; 368 } 369 370 static inline bool 371 i915_vm_has_scratch_64K(struct i915_address_space *vm) 372 { 373 return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K); 374 } 375 376 static inline bool 377 i915_vm_has_cache_coloring(struct i915_address_space *vm) 378 { 379 return i915_is_ggtt(vm) && vm->mm.color_adjust; 380 } 381 382 static inline struct i915_ggtt * 383 i915_vm_to_ggtt(struct i915_address_space *vm) 384 { 385 BUILD_BUG_ON(offsetof(struct i915_ggtt, vm)); 386 GEM_BUG_ON(!i915_is_ggtt(vm)); 387 return container_of(vm, struct i915_ggtt, vm); 388 } 389 390 static inline struct i915_ppgtt * 391 i915_vm_to_ppgtt(struct i915_address_space *vm) 392 { 393 BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm)); 394 GEM_BUG_ON(i915_is_ggtt(vm)); 395 return container_of(vm, struct i915_ppgtt, vm); 396 } 397 398 static inline struct i915_address_space * 399 i915_vm_get(struct i915_address_space *vm) 400 { 401 kref_get(&vm->ref); 402 return vm; 403 } 404 405 void i915_vm_release(struct kref *kref); 406 407 static inline void i915_vm_put(struct i915_address_space *vm) 408 { 409 kref_put(&vm->ref, i915_vm_release); 410 } 411 412 static inline struct i915_address_space * 413 i915_vm_open(struct i915_address_space *vm) 414 { 415 GEM_BUG_ON(!atomic_read(&vm->open)); 416 atomic_inc(&vm->open); 417 return i915_vm_get(vm); 418 } 419 420 static inline bool 421 i915_vm_tryopen(struct i915_address_space *vm) 422 { 423 if (atomic_add_unless(&vm->open, 1, 0)) 424 return i915_vm_get(vm); 425 426 return false; 427 } 428 429 void __i915_vm_close(struct i915_address_space *vm); 430 431 static inline void 432 i915_vm_close(struct i915_address_space *vm) 433 { 434 GEM_BUG_ON(!atomic_read(&vm->open)); 435 __i915_vm_close(vm); 436 437 i915_vm_put(vm); 438 } 439 440 void i915_address_space_init(struct i915_address_space *vm, int subclass); 441 void i915_address_space_fini(struct i915_address_space *vm); 442 443 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 444 { 445 const u32 mask = NUM_PTE(pde_shift) - 1; 446 447 return (address >> PAGE_SHIFT) & mask; 448 } 449 450 /* 451 * Helper to counts the number of PTEs within the given length. This count 452 * does not cross a page table boundary, so the max value would be 453 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 454 */ 455 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 456 { 457 const u64 mask = ~((1ULL << pde_shift) - 1); 458 u64 end; 459 460 GEM_BUG_ON(length == 0); 461 GEM_BUG_ON(offset_in_page(addr | length)); 462 463 end = addr + length; 464 465 if ((addr & mask) != (end & mask)) 466 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 467 468 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 469 } 470 471 static inline u32 i915_pde_index(u64 addr, u32 shift) 472 { 473 return (addr >> shift) & I915_PDE_MASK; 474 } 475 476 static inline struct i915_page_table * 477 i915_pt_entry(const struct i915_page_directory * const pd, 478 const unsigned short n) 479 { 480 return pd->entry[n]; 481 } 482 483 static inline struct i915_page_directory * 484 i915_pd_entry(const struct i915_page_directory * const pdp, 485 const unsigned short n) 486 { 487 return pdp->entry[n]; 488 } 489 490 static inline dma_addr_t 491 i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n) 492 { 493 struct i915_page_dma *pt = ppgtt->pd->entry[n]; 494 495 return px_dma(pt ?: px_base(&ppgtt->vm.scratch[ppgtt->vm.top])); 496 } 497 498 void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt); 499 500 int i915_ggtt_probe_hw(struct drm_i915_private *i915); 501 int i915_ggtt_init_hw(struct drm_i915_private *i915); 502 int i915_ggtt_enable_hw(struct drm_i915_private *i915); 503 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt); 504 void i915_ggtt_disable_guc(struct i915_ggtt *ggtt); 505 int i915_init_ggtt(struct drm_i915_private *i915); 506 void i915_ggtt_driver_release(struct drm_i915_private *i915); 507 508 static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt) 509 { 510 return ggtt->mappable_end > 0; 511 } 512 513 int i915_ppgtt_init_hw(struct intel_gt *gt); 514 515 struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt); 516 517 void i915_ggtt_suspend(struct i915_ggtt *gtt); 518 void i915_ggtt_resume(struct i915_ggtt *ggtt); 519 520 int setup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p); 521 void cleanup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p); 522 523 #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page) 524 525 void 526 fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count); 527 528 #define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64)) 529 #define fill32_px(px, v) do { \ 530 u64 v__ = lower_32_bits(v); \ 531 fill_px((px), v__ << 32 | v__); \ 532 } while (0) 533 534 int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp); 535 void cleanup_scratch_page(struct i915_address_space *vm); 536 void free_scratch(struct i915_address_space *vm); 537 538 struct i915_page_table *alloc_pt(struct i915_address_space *vm); 539 struct i915_page_directory *alloc_pd(struct i915_address_space *vm); 540 struct i915_page_directory *__alloc_pd(size_t sz); 541 542 void free_pd(struct i915_address_space *vm, struct i915_page_dma *pd); 543 544 #define free_px(vm, px) free_pd(vm, px_base(px)) 545 546 void 547 __set_pd_entry(struct i915_page_directory * const pd, 548 const unsigned short idx, 549 struct i915_page_dma * const to, 550 u64 (*encode)(const dma_addr_t, const enum i915_cache_level)); 551 552 #define set_pd_entry(pd, idx, to) \ 553 __set_pd_entry((pd), (idx), px_base(to), gen8_pde_encode) 554 555 void 556 clear_pd_entry(struct i915_page_directory * const pd, 557 const unsigned short idx, 558 const struct i915_page_scratch * const scratch); 559 560 bool 561 release_pd_entry(struct i915_page_directory * const pd, 562 const unsigned short idx, 563 struct i915_page_table * const pt, 564 const struct i915_page_scratch * const scratch); 565 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt); 566 567 int ggtt_set_pages(struct i915_vma *vma); 568 int ppgtt_set_pages(struct i915_vma *vma); 569 void clear_pages(struct i915_vma *vma); 570 571 int ppgtt_bind_vma(struct i915_address_space *vm, 572 struct i915_vma *vma, 573 enum i915_cache_level cache_level, 574 u32 flags); 575 void ppgtt_unbind_vma(struct i915_address_space *vm, 576 struct i915_vma *vma); 577 578 void gtt_write_workarounds(struct intel_gt *gt); 579 580 void setup_private_pat(struct intel_uncore *uncore); 581 582 static inline struct sgt_dma { 583 struct scatterlist *sg; 584 dma_addr_t dma, max; 585 } sgt_dma(struct i915_vma *vma) { 586 struct scatterlist *sg = vma->pages->sgl; 587 dma_addr_t addr = sg_dma_address(sg); 588 589 return (struct sgt_dma){ sg, addr, addr + sg->length }; 590 } 591 592 #endif 593