1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * Please try to maintain the following order within this file unless it makes 6 * sense to do otherwise. From top to bottom: 7 * 1. typedefs 8 * 2. #defines, and macros 9 * 3. structure definitions 10 * 4. function prototypes 11 * 12 * Within each section, please try to order by generation in ascending order, 13 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 14 */ 15 16 #ifndef __INTEL_GTT_H__ 17 #define __INTEL_GTT_H__ 18 19 #include <linux/io-mapping.h> 20 #include <linux/kref.h> 21 #include <linux/mm.h> 22 #include <linux/pagevec.h> 23 #include <linux/scatterlist.h> 24 #include <linux/workqueue.h> 25 26 #include <drm/drm_mm.h> 27 28 #include "gt/intel_reset.h" 29 #include "i915_selftest.h" 30 #include "i915_vma_resource.h" 31 #include "i915_vma_types.h" 32 #include "i915_params.h" 33 #include "intel_memory_region.h" 34 35 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 36 37 #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT) 38 #define DBG(...) trace_printk(__VA_ARGS__) 39 #else 40 #define DBG(...) 41 #endif 42 43 #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */ 44 45 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) 46 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) 47 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) 48 49 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 50 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 51 52 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE 53 54 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 55 56 #define I915_FENCE_REG_NONE -1 57 #define I915_MAX_NUM_FENCES 32 58 /* 32 fences + sign bit for FENCE_REG_NONE */ 59 #define I915_MAX_NUM_FENCE_BITS 6 60 61 typedef u32 gen6_pte_t; 62 typedef u64 gen8_pte_t; 63 64 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT) 65 66 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 67 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 68 #define I915_PDES 512 69 #define I915_PDE_MASK (I915_PDES - 1) 70 71 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 72 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 73 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 74 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 75 #define GEN6_PTE_CACHE_LLC (2 << 1) 76 #define GEN6_PTE_UNCACHED (1 << 1) 77 #define GEN6_PTE_VALID REG_BIT(0) 78 79 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 80 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 81 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 82 #define GEN6_PDE_SHIFT 22 83 #define GEN6_PDE_VALID REG_BIT(0) 84 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 85 86 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 87 88 #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2) 89 #define BYT_PTE_WRITEABLE REG_BIT(1) 90 91 #define MTL_PPGTT_PTE_PAT3 BIT_ULL(62) 92 #define GEN12_PPGTT_PTE_LM BIT_ULL(11) 93 #define GEN12_PPGTT_PTE_PAT2 BIT_ULL(7) 94 #define GEN12_PPGTT_PTE_PAT1 BIT_ULL(4) 95 #define GEN12_PPGTT_PTE_PAT0 BIT_ULL(3) 96 97 #define GEN12_GGTT_PTE_LM BIT_ULL(1) 98 #define MTL_GGTT_PTE_PAT0 BIT_ULL(52) 99 #define MTL_GGTT_PTE_PAT1 BIT_ULL(53) 100 #define GEN12_GGTT_PTE_ADDR_MASK GENMASK_ULL(45, 12) 101 #define MTL_GGTT_PTE_PAT_MASK GENMASK_ULL(53, 52) 102 103 #define GEN12_PDE_64K BIT(6) 104 #define GEN12_PTE_PS64 BIT(8) 105 106 /* 107 * Cacheability Control is a 4-bit value. The low three bits are stored in bits 108 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 109 */ 110 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 111 (((bits) & 0x8) << (11 - 3))) 112 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 113 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 114 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 115 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 116 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 117 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 118 #define HSW_PTE_UNCACHED (0) 119 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 120 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 121 122 /* 123 * GEN8 32b style address is defined as a 3 level page table: 124 * 31:30 | 29:21 | 20:12 | 11:0 125 * PDPE | PDE | PTE | offset 126 * The difference as compared to normal x86 3 level page table is the PDPEs are 127 * programmed via register. 128 * 129 * GEN8 48b style address is defined as a 4 level page table: 130 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 131 * PML4E | PDPE | PDE | PTE | offset 132 */ 133 #define GEN8_3LVL_PDPES 4 134 135 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 136 #define PPAT_CACHED_PDE 0 /* WB LLC */ 137 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 138 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 139 140 #define CHV_PPAT_SNOOP REG_BIT(6) 141 #define GEN8_PPAT_AGE(x) ((x)<<4) 142 #define GEN8_PPAT_LLCeLLC (3<<2) 143 #define GEN8_PPAT_LLCELLC (2<<2) 144 #define GEN8_PPAT_LLC (1<<2) 145 #define GEN8_PPAT_WB (3<<0) 146 #define GEN8_PPAT_WT (2<<0) 147 #define GEN8_PPAT_WC (1<<0) 148 #define GEN8_PPAT_UC (0<<0) 149 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 150 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 151 152 #define GEN8_PAGE_PRESENT BIT_ULL(0) 153 #define GEN8_PAGE_RW BIT_ULL(1) 154 155 #define GEN8_PDE_IPS_64K BIT(11) 156 #define GEN8_PDE_PS_2M BIT(7) 157 158 #define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2) 159 #define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0) 160 #define MTL_PPAT_L4_3_UC REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3) 161 #define MTL_PPAT_L4_1_WT REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1) 162 #define MTL_PPAT_L4_0_WB REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0) 163 #define MTL_3_COH_2W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3) 164 #define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2) 165 166 enum i915_cache_level; 167 168 struct drm_i915_gem_object; 169 struct i915_fence_reg; 170 struct i915_vma; 171 struct intel_gt; 172 173 #define for_each_sgt_daddr(__dp, __iter, __sgt) \ 174 __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE) 175 176 struct i915_page_table { 177 struct drm_i915_gem_object *base; 178 union { 179 atomic_t used; 180 struct i915_page_table *stash; 181 }; 182 bool is_compact; 183 }; 184 185 struct i915_page_directory { 186 struct i915_page_table pt; 187 spinlock_t lock; 188 void **entry; 189 }; 190 191 #define __px_choose_expr(x, type, expr, other) \ 192 __builtin_choose_expr( \ 193 __builtin_types_compatible_p(typeof(x), type) || \ 194 __builtin_types_compatible_p(typeof(x), const type), \ 195 ({ type __x = (type)(x); expr; }), \ 196 other) 197 198 #define px_base(px) \ 199 __px_choose_expr(px, struct drm_i915_gem_object *, __x, \ 200 __px_choose_expr(px, struct i915_page_table *, __x->base, \ 201 __px_choose_expr(px, struct i915_page_directory *, __x->pt.base, \ 202 (void)0))) 203 204 struct page *__px_page(struct drm_i915_gem_object *p); 205 dma_addr_t __px_dma(struct drm_i915_gem_object *p); 206 #define px_dma(px) (__px_dma(px_base(px))) 207 208 void *__px_vaddr(struct drm_i915_gem_object *p); 209 #define px_vaddr(px) (__px_vaddr(px_base(px))) 210 211 #define px_pt(px) \ 212 __px_choose_expr(px, struct i915_page_table *, __x, \ 213 __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \ 214 (void)0)) 215 #define px_used(px) (&px_pt(px)->used) 216 217 struct i915_vm_pt_stash { 218 /* preallocated chains of page tables/directories */ 219 struct i915_page_table *pt[2]; 220 /* 221 * Optionally override the alignment/size of the physical page that 222 * contains each PT. If not set defaults back to the usual 223 * I915_GTT_PAGE_SIZE_4K. This does not influence the other paging 224 * structures. MUST be a power-of-two. ONLY applicable on discrete 225 * platforms. 226 */ 227 int pt_sz; 228 }; 229 230 struct i915_vma_ops { 231 /* Map an object into an address space with the given cache flags. */ 232 void (*bind_vma)(struct i915_address_space *vm, 233 struct i915_vm_pt_stash *stash, 234 struct i915_vma_resource *vma_res, 235 enum i915_cache_level cache_level, 236 u32 flags); 237 /* 238 * Unmap an object from an address space. This usually consists of 239 * setting the valid PTE entries to a reserved scratch page. 240 */ 241 void (*unbind_vma)(struct i915_address_space *vm, 242 struct i915_vma_resource *vma_res); 243 244 }; 245 246 struct i915_address_space { 247 struct kref ref; 248 struct work_struct release_work; 249 250 struct drm_mm mm; 251 struct intel_gt *gt; 252 struct drm_i915_private *i915; 253 struct device *dma; 254 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 255 u64 reserved; /* size addr space reserved */ 256 u64 min_alignment[INTEL_MEMORY_STOLEN_LOCAL + 1]; 257 258 unsigned int bind_async_flags; 259 260 struct mutex mutex; /* protects vma and our lists */ 261 262 struct kref resv_ref; /* kref to keep the reservation lock alive. */ 263 struct dma_resv _resv; /* reservation lock for all pd objects, and buffer pool */ 264 #define VM_CLASS_GGTT 0 265 #define VM_CLASS_PPGTT 1 266 #define VM_CLASS_DPT 2 267 268 struct drm_i915_gem_object *scratch[4]; 269 /** 270 * List of vma currently bound. 271 */ 272 struct list_head bound_list; 273 274 /** 275 * List of vmas not yet bound or evicted. 276 */ 277 struct list_head unbound_list; 278 279 /* Global GTT */ 280 bool is_ggtt:1; 281 282 /* Display page table */ 283 bool is_dpt:1; 284 285 /* Some systems support read-only mappings for GGTT and/or PPGTT */ 286 bool has_read_only:1; 287 288 /* Skip pte rewrite on unbind for suspend. Protected by @mutex */ 289 bool skip_pte_rewrite:1; 290 291 u8 top; 292 u8 pd_shift; 293 u8 scratch_order; 294 295 /* Flags used when creating page-table objects for this vm */ 296 unsigned long lmem_pt_obj_flags; 297 298 /* Interval tree for pending unbind vma resources */ 299 struct rb_root_cached pending_unbind; 300 301 struct drm_i915_gem_object * 302 (*alloc_pt_dma)(struct i915_address_space *vm, int sz); 303 struct drm_i915_gem_object * 304 (*alloc_scratch_dma)(struct i915_address_space *vm, int sz); 305 306 u64 (*pte_encode)(dma_addr_t addr, 307 enum i915_cache_level level, 308 u32 flags); /* Create a valid PTE */ 309 #define PTE_READ_ONLY BIT(0) 310 #define PTE_LM BIT(1) 311 312 void (*allocate_va_range)(struct i915_address_space *vm, 313 struct i915_vm_pt_stash *stash, 314 u64 start, u64 length); 315 void (*clear_range)(struct i915_address_space *vm, 316 u64 start, u64 length); 317 void (*scratch_range)(struct i915_address_space *vm, 318 u64 start, u64 length); 319 void (*insert_page)(struct i915_address_space *vm, 320 dma_addr_t addr, 321 u64 offset, 322 enum i915_cache_level cache_level, 323 u32 flags); 324 void (*insert_entries)(struct i915_address_space *vm, 325 struct i915_vma_resource *vma_res, 326 enum i915_cache_level cache_level, 327 u32 flags); 328 void (*raw_insert_page)(struct i915_address_space *vm, 329 dma_addr_t addr, 330 u64 offset, 331 enum i915_cache_level cache_level, 332 u32 flags); 333 void (*raw_insert_entries)(struct i915_address_space *vm, 334 struct i915_vma_resource *vma_res, 335 enum i915_cache_level cache_level, 336 u32 flags); 337 void (*cleanup)(struct i915_address_space *vm); 338 339 void (*foreach)(struct i915_address_space *vm, 340 u64 start, u64 length, 341 void (*fn)(struct i915_address_space *vm, 342 struct i915_page_table *pt, 343 void *data), 344 void *data); 345 346 struct i915_vma_ops vma_ops; 347 348 I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 349 I915_SELFTEST_DECLARE(bool scrub_64K); 350 }; 351 352 /* 353 * The Graphics Translation Table is the way in which GEN hardware translates a 354 * Graphics Virtual Address into a Physical Address. In addition to the normal 355 * collateral associated with any va->pa translations GEN hardware also has a 356 * portion of the GTT which can be mapped by the CPU and remain both coherent 357 * and correct (in cases like swizzling). That region is referred to as GMADR in 358 * the spec. 359 */ 360 struct i915_ggtt { 361 struct i915_address_space vm; 362 363 struct io_mapping iomap; /* Mapping to our CPU mappable region */ 364 struct resource gmadr; /* GMADR resource */ 365 resource_size_t mappable_end; /* End offset that we can CPU map */ 366 367 /** "Graphics Stolen Memory" holds the global PTEs */ 368 void __iomem *gsm; 369 void (*invalidate)(struct i915_ggtt *ggtt); 370 371 /** PPGTT used for aliasing the PPGTT with the GTT */ 372 struct i915_ppgtt *alias; 373 374 bool do_idle_maps; 375 376 int mtrr; 377 378 /** Bit 6 swizzling required for X tiling */ 379 u32 bit_6_swizzle_x; 380 /** Bit 6 swizzling required for Y tiling */ 381 u32 bit_6_swizzle_y; 382 383 u32 pin_bias; 384 385 unsigned int num_fences; 386 struct i915_fence_reg *fence_regs; 387 struct list_head fence_list; 388 389 /** 390 * List of all objects in gtt_space, currently mmaped by userspace. 391 * All objects within this list must also be on bound_list. 392 */ 393 struct list_head userfault_list; 394 395 struct mutex error_mutex; 396 struct drm_mm_node error_capture; 397 struct drm_mm_node uc_fw; 398 399 /** List of GTs mapping this GGTT */ 400 struct list_head gt_list; 401 }; 402 403 struct i915_ppgtt { 404 struct i915_address_space vm; 405 406 struct i915_page_directory *pd; 407 }; 408 409 #define i915_is_ggtt(vm) ((vm)->is_ggtt) 410 #define i915_is_dpt(vm) ((vm)->is_dpt) 411 #define i915_is_ggtt_or_dpt(vm) (i915_is_ggtt(vm) || i915_is_dpt(vm)) 412 413 bool intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915); 414 415 int __must_check 416 i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww); 417 418 static inline bool 419 i915_vm_is_4lvl(const struct i915_address_space *vm) 420 { 421 return (vm->total - 1) >> 32; 422 } 423 424 static inline bool 425 i915_vm_has_scratch_64K(struct i915_address_space *vm) 426 { 427 return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K); 428 } 429 430 static inline u64 i915_vm_min_alignment(struct i915_address_space *vm, 431 enum intel_memory_type type) 432 { 433 /* avoid INTEL_MEMORY_MOCK overflow */ 434 if ((int)type >= ARRAY_SIZE(vm->min_alignment)) 435 type = INTEL_MEMORY_SYSTEM; 436 437 return vm->min_alignment[type]; 438 } 439 440 static inline u64 i915_vm_obj_min_alignment(struct i915_address_space *vm, 441 struct drm_i915_gem_object *obj) 442 { 443 struct intel_memory_region *mr = READ_ONCE(obj->mm.region); 444 enum intel_memory_type type = mr ? mr->type : INTEL_MEMORY_SYSTEM; 445 446 return i915_vm_min_alignment(vm, type); 447 } 448 449 static inline bool 450 i915_vm_has_cache_coloring(struct i915_address_space *vm) 451 { 452 return i915_is_ggtt(vm) && vm->mm.color_adjust; 453 } 454 455 static inline struct i915_ggtt * 456 i915_vm_to_ggtt(struct i915_address_space *vm) 457 { 458 BUILD_BUG_ON(offsetof(struct i915_ggtt, vm)); 459 GEM_BUG_ON(!i915_is_ggtt(vm)); 460 return container_of(vm, struct i915_ggtt, vm); 461 } 462 463 static inline struct i915_ppgtt * 464 i915_vm_to_ppgtt(struct i915_address_space *vm) 465 { 466 BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm)); 467 GEM_BUG_ON(i915_is_ggtt_or_dpt(vm)); 468 return container_of(vm, struct i915_ppgtt, vm); 469 } 470 471 static inline struct i915_address_space * 472 i915_vm_get(struct i915_address_space *vm) 473 { 474 kref_get(&vm->ref); 475 return vm; 476 } 477 478 static inline struct i915_address_space * 479 i915_vm_tryget(struct i915_address_space *vm) 480 { 481 return kref_get_unless_zero(&vm->ref) ? vm : NULL; 482 } 483 484 static inline void assert_vm_alive(struct i915_address_space *vm) 485 { 486 GEM_BUG_ON(!kref_read(&vm->ref)); 487 } 488 489 /** 490 * i915_vm_resv_get - Obtain a reference on the vm's reservation lock 491 * @vm: The vm whose reservation lock we want to share. 492 * 493 * Return: A pointer to the vm's reservation lock. 494 */ 495 static inline struct dma_resv *i915_vm_resv_get(struct i915_address_space *vm) 496 { 497 kref_get(&vm->resv_ref); 498 return &vm->_resv; 499 } 500 501 void i915_vm_release(struct kref *kref); 502 503 void i915_vm_resv_release(struct kref *kref); 504 505 static inline void i915_vm_put(struct i915_address_space *vm) 506 { 507 kref_put(&vm->ref, i915_vm_release); 508 } 509 510 /** 511 * i915_vm_resv_put - Release a reference on the vm's reservation lock 512 * @resv: Pointer to a reservation lock obtained from i915_vm_resv_get() 513 */ 514 static inline void i915_vm_resv_put(struct i915_address_space *vm) 515 { 516 kref_put(&vm->resv_ref, i915_vm_resv_release); 517 } 518 519 void i915_address_space_init(struct i915_address_space *vm, int subclass); 520 void i915_address_space_fini(struct i915_address_space *vm); 521 522 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 523 { 524 const u32 mask = NUM_PTE(pde_shift) - 1; 525 526 return (address >> PAGE_SHIFT) & mask; 527 } 528 529 /* 530 * Helper to counts the number of PTEs within the given length. This count 531 * does not cross a page table boundary, so the max value would be 532 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 533 */ 534 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 535 { 536 const u64 mask = ~((1ULL << pde_shift) - 1); 537 u64 end; 538 539 GEM_BUG_ON(length == 0); 540 GEM_BUG_ON(offset_in_page(addr | length)); 541 542 end = addr + length; 543 544 if ((addr & mask) != (end & mask)) 545 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 546 547 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 548 } 549 550 static inline u32 i915_pde_index(u64 addr, u32 shift) 551 { 552 return (addr >> shift) & I915_PDE_MASK; 553 } 554 555 static inline struct i915_page_table * 556 i915_pt_entry(const struct i915_page_directory * const pd, 557 const unsigned short n) 558 { 559 return pd->entry[n]; 560 } 561 562 static inline struct i915_page_directory * 563 i915_pd_entry(const struct i915_page_directory * const pdp, 564 const unsigned short n) 565 { 566 return pdp->entry[n]; 567 } 568 569 static inline dma_addr_t 570 i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n) 571 { 572 struct i915_page_table *pt = ppgtt->pd->entry[n]; 573 574 return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]); 575 } 576 577 void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt, 578 unsigned long lmem_pt_obj_flags); 579 void intel_ggtt_bind_vma(struct i915_address_space *vm, 580 struct i915_vm_pt_stash *stash, 581 struct i915_vma_resource *vma_res, 582 enum i915_cache_level cache_level, 583 u32 flags); 584 void intel_ggtt_unbind_vma(struct i915_address_space *vm, 585 struct i915_vma_resource *vma_res); 586 587 int i915_ggtt_probe_hw(struct drm_i915_private *i915); 588 int i915_ggtt_init_hw(struct drm_i915_private *i915); 589 int i915_ggtt_enable_hw(struct drm_i915_private *i915); 590 int i915_init_ggtt(struct drm_i915_private *i915); 591 void i915_ggtt_driver_release(struct drm_i915_private *i915); 592 void i915_ggtt_driver_late_release(struct drm_i915_private *i915); 593 struct i915_ggtt *i915_ggtt_create(struct drm_i915_private *i915); 594 595 static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt) 596 { 597 return ggtt->mappable_end > 0; 598 } 599 600 int i915_ppgtt_init_hw(struct intel_gt *gt); 601 602 struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt, 603 unsigned long lmem_pt_obj_flags); 604 605 void i915_ggtt_suspend_vm(struct i915_address_space *vm); 606 bool i915_ggtt_resume_vm(struct i915_address_space *vm); 607 void i915_ggtt_suspend(struct i915_ggtt *gtt); 608 void i915_ggtt_resume(struct i915_ggtt *ggtt); 609 610 void 611 fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count); 612 613 #define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64)) 614 #define fill32_px(px, v) do { \ 615 u64 v__ = lower_32_bits(v); \ 616 fill_px((px), v__ << 32 | v__); \ 617 } while (0) 618 619 int setup_scratch_page(struct i915_address_space *vm); 620 void free_scratch(struct i915_address_space *vm); 621 622 struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz); 623 struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz); 624 struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz); 625 struct i915_page_directory *alloc_pd(struct i915_address_space *vm); 626 struct i915_page_directory *__alloc_pd(int npde); 627 628 int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj); 629 int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj); 630 631 void free_px(struct i915_address_space *vm, 632 struct i915_page_table *pt, int lvl); 633 #define free_pt(vm, px) free_px(vm, px, 0) 634 #define free_pd(vm, px) free_px(vm, px_pt(px), 1) 635 636 void 637 __set_pd_entry(struct i915_page_directory * const pd, 638 const unsigned short idx, 639 struct i915_page_table *pt, 640 u64 (*encode)(const dma_addr_t, const enum i915_cache_level)); 641 642 #define set_pd_entry(pd, idx, to) \ 643 __set_pd_entry((pd), (idx), px_pt(to), gen8_pde_encode) 644 645 void 646 clear_pd_entry(struct i915_page_directory * const pd, 647 const unsigned short idx, 648 const struct drm_i915_gem_object * const scratch); 649 650 bool 651 release_pd_entry(struct i915_page_directory * const pd, 652 const unsigned short idx, 653 struct i915_page_table * const pt, 654 const struct drm_i915_gem_object * const scratch); 655 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt); 656 657 void ppgtt_bind_vma(struct i915_address_space *vm, 658 struct i915_vm_pt_stash *stash, 659 struct i915_vma_resource *vma_res, 660 enum i915_cache_level cache_level, 661 u32 flags); 662 void ppgtt_unbind_vma(struct i915_address_space *vm, 663 struct i915_vma_resource *vma_res); 664 665 void gtt_write_workarounds(struct intel_gt *gt); 666 667 void setup_private_pat(struct intel_gt *gt); 668 669 int i915_vm_alloc_pt_stash(struct i915_address_space *vm, 670 struct i915_vm_pt_stash *stash, 671 u64 size); 672 int i915_vm_map_pt_stash(struct i915_address_space *vm, 673 struct i915_vm_pt_stash *stash); 674 void i915_vm_free_pt_stash(struct i915_address_space *vm, 675 struct i915_vm_pt_stash *stash); 676 677 struct i915_vma * 678 __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size); 679 680 struct i915_vma * 681 __vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size); 682 683 static inline struct sgt_dma { 684 struct scatterlist *sg; 685 dma_addr_t dma, max; 686 } sgt_dma(struct i915_vma_resource *vma_res) { 687 struct scatterlist *sg = vma_res->bi.pages->sgl; 688 dma_addr_t addr = sg_dma_address(sg); 689 690 return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) }; 691 } 692 693 #endif 694