1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * Please try to maintain the following order within this file unless it makes 6 * sense to do otherwise. From top to bottom: 7 * 1. typedefs 8 * 2. #defines, and macros 9 * 3. structure definitions 10 * 4. function prototypes 11 * 12 * Within each section, please try to order by generation in ascending order, 13 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 14 */ 15 16 #ifndef __INTEL_GTT_H__ 17 #define __INTEL_GTT_H__ 18 19 #include <linux/io-mapping.h> 20 #include <linux/kref.h> 21 #include <linux/mm.h> 22 #include <linux/pagevec.h> 23 #include <linux/scatterlist.h> 24 #include <linux/workqueue.h> 25 26 #include <drm/drm_mm.h> 27 28 #include "gt/intel_reset.h" 29 #include "i915_selftest.h" 30 #include "i915_vma_resource.h" 31 #include "i915_vma_types.h" 32 #include "i915_params.h" 33 #include "intel_memory_region.h" 34 35 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 36 37 #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT) 38 #define DBG(...) trace_printk(__VA_ARGS__) 39 #else 40 #define DBG(...) 41 #endif 42 43 #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */ 44 45 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) 46 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) 47 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) 48 49 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 50 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 51 52 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE 53 54 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 55 56 #define I915_FENCE_REG_NONE -1 57 #define I915_MAX_NUM_FENCES 32 58 /* 32 fences + sign bit for FENCE_REG_NONE */ 59 #define I915_MAX_NUM_FENCE_BITS 6 60 61 typedef u32 gen6_pte_t; 62 typedef u64 gen8_pte_t; 63 64 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT) 65 66 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 67 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 68 #define I915_PDES 512 69 #define I915_PDE_MASK (I915_PDES - 1) 70 71 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 72 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 73 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 74 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 75 #define GEN6_PTE_CACHE_LLC (2 << 1) 76 #define GEN6_PTE_UNCACHED (1 << 1) 77 #define GEN6_PTE_VALID REG_BIT(0) 78 79 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 80 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 81 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 82 #define GEN6_PDE_SHIFT 22 83 #define GEN6_PDE_VALID REG_BIT(0) 84 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 85 86 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 87 88 #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2) 89 #define BYT_PTE_WRITEABLE REG_BIT(1) 90 91 #define GEN12_PPGTT_PTE_LM BIT_ULL(11) 92 93 #define GEN12_GGTT_PTE_LM BIT_ULL(1) 94 95 #define GEN12_PDE_64K BIT(6) 96 #define GEN12_PTE_PS64 BIT(8) 97 98 /* 99 * Cacheability Control is a 4-bit value. The low three bits are stored in bits 100 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 101 */ 102 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 103 (((bits) & 0x8) << (11 - 3))) 104 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 105 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 106 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 107 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 108 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 109 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 110 #define HSW_PTE_UNCACHED (0) 111 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 112 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 113 114 /* 115 * GEN8 32b style address is defined as a 3 level page table: 116 * 31:30 | 29:21 | 20:12 | 11:0 117 * PDPE | PDE | PTE | offset 118 * The difference as compared to normal x86 3 level page table is the PDPEs are 119 * programmed via register. 120 * 121 * GEN8 48b style address is defined as a 4 level page table: 122 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 123 * PML4E | PDPE | PDE | PTE | offset 124 */ 125 #define GEN8_3LVL_PDPES 4 126 127 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 128 #define PPAT_CACHED_PDE 0 /* WB LLC */ 129 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 130 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 131 132 #define CHV_PPAT_SNOOP REG_BIT(6) 133 #define GEN8_PPAT_AGE(x) ((x)<<4) 134 #define GEN8_PPAT_LLCeLLC (3<<2) 135 #define GEN8_PPAT_LLCELLC (2<<2) 136 #define GEN8_PPAT_LLC (1<<2) 137 #define GEN8_PPAT_WB (3<<0) 138 #define GEN8_PPAT_WT (2<<0) 139 #define GEN8_PPAT_WC (1<<0) 140 #define GEN8_PPAT_UC (0<<0) 141 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 142 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 143 144 #define GEN8_PAGE_PRESENT BIT_ULL(0) 145 #define GEN8_PAGE_RW BIT_ULL(1) 146 147 #define GEN8_PDE_IPS_64K BIT(11) 148 #define GEN8_PDE_PS_2M BIT(7) 149 150 enum i915_cache_level; 151 152 struct drm_i915_gem_object; 153 struct i915_fence_reg; 154 struct i915_vma; 155 struct intel_gt; 156 157 #define for_each_sgt_daddr(__dp, __iter, __sgt) \ 158 __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE) 159 160 struct i915_page_table { 161 struct drm_i915_gem_object *base; 162 union { 163 atomic_t used; 164 struct i915_page_table *stash; 165 }; 166 bool is_compact; 167 }; 168 169 struct i915_page_directory { 170 struct i915_page_table pt; 171 spinlock_t lock; 172 void **entry; 173 }; 174 175 #define __px_choose_expr(x, type, expr, other) \ 176 __builtin_choose_expr( \ 177 __builtin_types_compatible_p(typeof(x), type) || \ 178 __builtin_types_compatible_p(typeof(x), const type), \ 179 ({ type __x = (type)(x); expr; }), \ 180 other) 181 182 #define px_base(px) \ 183 __px_choose_expr(px, struct drm_i915_gem_object *, __x, \ 184 __px_choose_expr(px, struct i915_page_table *, __x->base, \ 185 __px_choose_expr(px, struct i915_page_directory *, __x->pt.base, \ 186 (void)0))) 187 188 struct page *__px_page(struct drm_i915_gem_object *p); 189 dma_addr_t __px_dma(struct drm_i915_gem_object *p); 190 #define px_dma(px) (__px_dma(px_base(px))) 191 192 void *__px_vaddr(struct drm_i915_gem_object *p); 193 #define px_vaddr(px) (__px_vaddr(px_base(px))) 194 195 #define px_pt(px) \ 196 __px_choose_expr(px, struct i915_page_table *, __x, \ 197 __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \ 198 (void)0)) 199 #define px_used(px) (&px_pt(px)->used) 200 201 struct i915_vm_pt_stash { 202 /* preallocated chains of page tables/directories */ 203 struct i915_page_table *pt[2]; 204 /* 205 * Optionally override the alignment/size of the physical page that 206 * contains each PT. If not set defaults back to the usual 207 * I915_GTT_PAGE_SIZE_4K. This does not influence the other paging 208 * structures. MUST be a power-of-two. ONLY applicable on discrete 209 * platforms. 210 */ 211 int pt_sz; 212 }; 213 214 struct i915_vma_ops { 215 /* Map an object into an address space with the given cache flags. */ 216 void (*bind_vma)(struct i915_address_space *vm, 217 struct i915_vm_pt_stash *stash, 218 struct i915_vma_resource *vma_res, 219 enum i915_cache_level cache_level, 220 u32 flags); 221 /* 222 * Unmap an object from an address space. This usually consists of 223 * setting the valid PTE entries to a reserved scratch page. 224 */ 225 void (*unbind_vma)(struct i915_address_space *vm, 226 struct i915_vma_resource *vma_res); 227 228 }; 229 230 struct i915_address_space { 231 struct kref ref; 232 struct work_struct release_work; 233 234 struct drm_mm mm; 235 struct intel_gt *gt; 236 struct drm_i915_private *i915; 237 struct device *dma; 238 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 239 u64 reserved; /* size addr space reserved */ 240 u64 min_alignment[INTEL_MEMORY_STOLEN_LOCAL + 1]; 241 242 unsigned int bind_async_flags; 243 244 struct mutex mutex; /* protects vma and our lists */ 245 246 struct kref resv_ref; /* kref to keep the reservation lock alive. */ 247 struct dma_resv _resv; /* reservation lock for all pd objects, and buffer pool */ 248 #define VM_CLASS_GGTT 0 249 #define VM_CLASS_PPGTT 1 250 #define VM_CLASS_DPT 2 251 252 struct drm_i915_gem_object *scratch[4]; 253 /** 254 * List of vma currently bound. 255 */ 256 struct list_head bound_list; 257 258 /** 259 * List of vmas not yet bound or evicted. 260 */ 261 struct list_head unbound_list; 262 263 /* Global GTT */ 264 bool is_ggtt:1; 265 266 /* Display page table */ 267 bool is_dpt:1; 268 269 /* Some systems support read-only mappings for GGTT and/or PPGTT */ 270 bool has_read_only:1; 271 272 /* Skip pte rewrite on unbind for suspend. Protected by @mutex */ 273 bool skip_pte_rewrite:1; 274 275 u8 top; 276 u8 pd_shift; 277 u8 scratch_order; 278 279 /* Flags used when creating page-table objects for this vm */ 280 unsigned long lmem_pt_obj_flags; 281 282 /* Interval tree for pending unbind vma resources */ 283 struct rb_root_cached pending_unbind; 284 285 struct drm_i915_gem_object * 286 (*alloc_pt_dma)(struct i915_address_space *vm, int sz); 287 struct drm_i915_gem_object * 288 (*alloc_scratch_dma)(struct i915_address_space *vm, int sz); 289 290 u64 (*pte_encode)(dma_addr_t addr, 291 enum i915_cache_level level, 292 u32 flags); /* Create a valid PTE */ 293 #define PTE_READ_ONLY BIT(0) 294 #define PTE_LM BIT(1) 295 296 void (*allocate_va_range)(struct i915_address_space *vm, 297 struct i915_vm_pt_stash *stash, 298 u64 start, u64 length); 299 void (*clear_range)(struct i915_address_space *vm, 300 u64 start, u64 length); 301 void (*insert_page)(struct i915_address_space *vm, 302 dma_addr_t addr, 303 u64 offset, 304 enum i915_cache_level cache_level, 305 u32 flags); 306 void (*insert_entries)(struct i915_address_space *vm, 307 struct i915_vma_resource *vma_res, 308 enum i915_cache_level cache_level, 309 u32 flags); 310 void (*raw_insert_page)(struct i915_address_space *vm, 311 dma_addr_t addr, 312 u64 offset, 313 enum i915_cache_level cache_level, 314 u32 flags); 315 void (*raw_insert_entries)(struct i915_address_space *vm, 316 struct i915_vma_resource *vma_res, 317 enum i915_cache_level cache_level, 318 u32 flags); 319 void (*cleanup)(struct i915_address_space *vm); 320 321 void (*foreach)(struct i915_address_space *vm, 322 u64 start, u64 length, 323 void (*fn)(struct i915_address_space *vm, 324 struct i915_page_table *pt, 325 void *data), 326 void *data); 327 328 struct i915_vma_ops vma_ops; 329 330 I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 331 I915_SELFTEST_DECLARE(bool scrub_64K); 332 }; 333 334 /* 335 * The Graphics Translation Table is the way in which GEN hardware translates a 336 * Graphics Virtual Address into a Physical Address. In addition to the normal 337 * collateral associated with any va->pa translations GEN hardware also has a 338 * portion of the GTT which can be mapped by the CPU and remain both coherent 339 * and correct (in cases like swizzling). That region is referred to as GMADR in 340 * the spec. 341 */ 342 struct i915_ggtt { 343 struct i915_address_space vm; 344 345 struct io_mapping iomap; /* Mapping to our CPU mappable region */ 346 struct resource gmadr; /* GMADR resource */ 347 resource_size_t mappable_end; /* End offset that we can CPU map */ 348 349 /** "Graphics Stolen Memory" holds the global PTEs */ 350 void __iomem *gsm; 351 void (*invalidate)(struct i915_ggtt *ggtt); 352 353 /** PPGTT used for aliasing the PPGTT with the GTT */ 354 struct i915_ppgtt *alias; 355 356 bool do_idle_maps; 357 358 int mtrr; 359 360 /** Bit 6 swizzling required for X tiling */ 361 u32 bit_6_swizzle_x; 362 /** Bit 6 swizzling required for Y tiling */ 363 u32 bit_6_swizzle_y; 364 365 u32 pin_bias; 366 367 unsigned int num_fences; 368 struct i915_fence_reg *fence_regs; 369 struct list_head fence_list; 370 371 /** 372 * List of all objects in gtt_space, currently mmaped by userspace. 373 * All objects within this list must also be on bound_list. 374 */ 375 struct list_head userfault_list; 376 377 struct mutex error_mutex; 378 struct drm_mm_node error_capture; 379 struct drm_mm_node uc_fw; 380 381 /** List of GTs mapping this GGTT */ 382 struct list_head gt_list; 383 }; 384 385 struct i915_ppgtt { 386 struct i915_address_space vm; 387 388 struct i915_page_directory *pd; 389 }; 390 391 #define i915_is_ggtt(vm) ((vm)->is_ggtt) 392 #define i915_is_dpt(vm) ((vm)->is_dpt) 393 #define i915_is_ggtt_or_dpt(vm) (i915_is_ggtt(vm) || i915_is_dpt(vm)) 394 395 bool intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915); 396 397 int __must_check 398 i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww); 399 400 static inline bool 401 i915_vm_is_4lvl(const struct i915_address_space *vm) 402 { 403 return (vm->total - 1) >> 32; 404 } 405 406 static inline bool 407 i915_vm_has_scratch_64K(struct i915_address_space *vm) 408 { 409 return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K); 410 } 411 412 static inline u64 i915_vm_min_alignment(struct i915_address_space *vm, 413 enum intel_memory_type type) 414 { 415 /* avoid INTEL_MEMORY_MOCK overflow */ 416 if ((int)type >= ARRAY_SIZE(vm->min_alignment)) 417 type = INTEL_MEMORY_SYSTEM; 418 419 return vm->min_alignment[type]; 420 } 421 422 static inline u64 i915_vm_obj_min_alignment(struct i915_address_space *vm, 423 struct drm_i915_gem_object *obj) 424 { 425 struct intel_memory_region *mr = READ_ONCE(obj->mm.region); 426 enum intel_memory_type type = mr ? mr->type : INTEL_MEMORY_SYSTEM; 427 428 return i915_vm_min_alignment(vm, type); 429 } 430 431 static inline bool 432 i915_vm_has_cache_coloring(struct i915_address_space *vm) 433 { 434 return i915_is_ggtt(vm) && vm->mm.color_adjust; 435 } 436 437 static inline struct i915_ggtt * 438 i915_vm_to_ggtt(struct i915_address_space *vm) 439 { 440 BUILD_BUG_ON(offsetof(struct i915_ggtt, vm)); 441 GEM_BUG_ON(!i915_is_ggtt(vm)); 442 return container_of(vm, struct i915_ggtt, vm); 443 } 444 445 static inline struct i915_ppgtt * 446 i915_vm_to_ppgtt(struct i915_address_space *vm) 447 { 448 BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm)); 449 GEM_BUG_ON(i915_is_ggtt_or_dpt(vm)); 450 return container_of(vm, struct i915_ppgtt, vm); 451 } 452 453 static inline struct i915_address_space * 454 i915_vm_get(struct i915_address_space *vm) 455 { 456 kref_get(&vm->ref); 457 return vm; 458 } 459 460 static inline struct i915_address_space * 461 i915_vm_tryget(struct i915_address_space *vm) 462 { 463 return kref_get_unless_zero(&vm->ref) ? vm : NULL; 464 } 465 466 static inline void assert_vm_alive(struct i915_address_space *vm) 467 { 468 GEM_BUG_ON(!kref_read(&vm->ref)); 469 } 470 471 /** 472 * i915_vm_resv_get - Obtain a reference on the vm's reservation lock 473 * @vm: The vm whose reservation lock we want to share. 474 * 475 * Return: A pointer to the vm's reservation lock. 476 */ 477 static inline struct dma_resv *i915_vm_resv_get(struct i915_address_space *vm) 478 { 479 kref_get(&vm->resv_ref); 480 return &vm->_resv; 481 } 482 483 void i915_vm_release(struct kref *kref); 484 485 void i915_vm_resv_release(struct kref *kref); 486 487 static inline void i915_vm_put(struct i915_address_space *vm) 488 { 489 kref_put(&vm->ref, i915_vm_release); 490 } 491 492 /** 493 * i915_vm_resv_put - Release a reference on the vm's reservation lock 494 * @resv: Pointer to a reservation lock obtained from i915_vm_resv_get() 495 */ 496 static inline void i915_vm_resv_put(struct i915_address_space *vm) 497 { 498 kref_put(&vm->resv_ref, i915_vm_resv_release); 499 } 500 501 void i915_address_space_init(struct i915_address_space *vm, int subclass); 502 void i915_address_space_fini(struct i915_address_space *vm); 503 504 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 505 { 506 const u32 mask = NUM_PTE(pde_shift) - 1; 507 508 return (address >> PAGE_SHIFT) & mask; 509 } 510 511 /* 512 * Helper to counts the number of PTEs within the given length. This count 513 * does not cross a page table boundary, so the max value would be 514 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 515 */ 516 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 517 { 518 const u64 mask = ~((1ULL << pde_shift) - 1); 519 u64 end; 520 521 GEM_BUG_ON(length == 0); 522 GEM_BUG_ON(offset_in_page(addr | length)); 523 524 end = addr + length; 525 526 if ((addr & mask) != (end & mask)) 527 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 528 529 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 530 } 531 532 static inline u32 i915_pde_index(u64 addr, u32 shift) 533 { 534 return (addr >> shift) & I915_PDE_MASK; 535 } 536 537 static inline struct i915_page_table * 538 i915_pt_entry(const struct i915_page_directory * const pd, 539 const unsigned short n) 540 { 541 return pd->entry[n]; 542 } 543 544 static inline struct i915_page_directory * 545 i915_pd_entry(const struct i915_page_directory * const pdp, 546 const unsigned short n) 547 { 548 return pdp->entry[n]; 549 } 550 551 static inline dma_addr_t 552 i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n) 553 { 554 struct i915_page_table *pt = ppgtt->pd->entry[n]; 555 556 return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]); 557 } 558 559 void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt, 560 unsigned long lmem_pt_obj_flags); 561 void intel_ggtt_bind_vma(struct i915_address_space *vm, 562 struct i915_vm_pt_stash *stash, 563 struct i915_vma_resource *vma_res, 564 enum i915_cache_level cache_level, 565 u32 flags); 566 void intel_ggtt_unbind_vma(struct i915_address_space *vm, 567 struct i915_vma_resource *vma_res); 568 569 int i915_ggtt_probe_hw(struct drm_i915_private *i915); 570 int i915_ggtt_init_hw(struct drm_i915_private *i915); 571 int i915_ggtt_enable_hw(struct drm_i915_private *i915); 572 int i915_init_ggtt(struct drm_i915_private *i915); 573 void i915_ggtt_driver_release(struct drm_i915_private *i915); 574 void i915_ggtt_driver_late_release(struct drm_i915_private *i915); 575 struct i915_ggtt *i915_ggtt_create(struct drm_i915_private *i915); 576 577 static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt) 578 { 579 return ggtt->mappable_end > 0; 580 } 581 582 int i915_ppgtt_init_hw(struct intel_gt *gt); 583 584 struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt, 585 unsigned long lmem_pt_obj_flags); 586 587 void i915_ggtt_suspend_vm(struct i915_address_space *vm); 588 bool i915_ggtt_resume_vm(struct i915_address_space *vm); 589 void i915_ggtt_suspend(struct i915_ggtt *gtt); 590 void i915_ggtt_resume(struct i915_ggtt *ggtt); 591 592 void 593 fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count); 594 595 #define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64)) 596 #define fill32_px(px, v) do { \ 597 u64 v__ = lower_32_bits(v); \ 598 fill_px((px), v__ << 32 | v__); \ 599 } while (0) 600 601 int setup_scratch_page(struct i915_address_space *vm); 602 void free_scratch(struct i915_address_space *vm); 603 604 struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz); 605 struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz); 606 struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz); 607 struct i915_page_directory *alloc_pd(struct i915_address_space *vm); 608 struct i915_page_directory *__alloc_pd(int npde); 609 610 int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj); 611 int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj); 612 613 void free_px(struct i915_address_space *vm, 614 struct i915_page_table *pt, int lvl); 615 #define free_pt(vm, px) free_px(vm, px, 0) 616 #define free_pd(vm, px) free_px(vm, px_pt(px), 1) 617 618 void 619 __set_pd_entry(struct i915_page_directory * const pd, 620 const unsigned short idx, 621 struct i915_page_table *pt, 622 u64 (*encode)(const dma_addr_t, const enum i915_cache_level)); 623 624 #define set_pd_entry(pd, idx, to) \ 625 __set_pd_entry((pd), (idx), px_pt(to), gen8_pde_encode) 626 627 void 628 clear_pd_entry(struct i915_page_directory * const pd, 629 const unsigned short idx, 630 const struct drm_i915_gem_object * const scratch); 631 632 bool 633 release_pd_entry(struct i915_page_directory * const pd, 634 const unsigned short idx, 635 struct i915_page_table * const pt, 636 const struct drm_i915_gem_object * const scratch); 637 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt); 638 639 void ppgtt_bind_vma(struct i915_address_space *vm, 640 struct i915_vm_pt_stash *stash, 641 struct i915_vma_resource *vma_res, 642 enum i915_cache_level cache_level, 643 u32 flags); 644 void ppgtt_unbind_vma(struct i915_address_space *vm, 645 struct i915_vma_resource *vma_res); 646 647 void gtt_write_workarounds(struct intel_gt *gt); 648 649 void setup_private_pat(struct intel_gt *gt); 650 651 int i915_vm_alloc_pt_stash(struct i915_address_space *vm, 652 struct i915_vm_pt_stash *stash, 653 u64 size); 654 int i915_vm_map_pt_stash(struct i915_address_space *vm, 655 struct i915_vm_pt_stash *stash); 656 void i915_vm_free_pt_stash(struct i915_address_space *vm, 657 struct i915_vm_pt_stash *stash); 658 659 struct i915_vma * 660 __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size); 661 662 struct i915_vma * 663 __vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size); 664 665 static inline struct sgt_dma { 666 struct scatterlist *sg; 667 dma_addr_t dma, max; 668 } sgt_dma(struct i915_vma_resource *vma_res) { 669 struct scatterlist *sg = vma_res->bi.pages->sgl; 670 dma_addr_t addr = sg_dma_address(sg); 671 672 return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) }; 673 } 674 675 #endif 676