12c86e55dSMatthew Auld /* SPDX-License-Identifier: MIT */ 22c86e55dSMatthew Auld /* 32c86e55dSMatthew Auld * Copyright © 2020 Intel Corporation 42c86e55dSMatthew Auld * 52c86e55dSMatthew Auld * Please try to maintain the following order within this file unless it makes 62c86e55dSMatthew Auld * sense to do otherwise. From top to bottom: 72c86e55dSMatthew Auld * 1. typedefs 82c86e55dSMatthew Auld * 2. #defines, and macros 92c86e55dSMatthew Auld * 3. structure definitions 102c86e55dSMatthew Auld * 4. function prototypes 112c86e55dSMatthew Auld * 122c86e55dSMatthew Auld * Within each section, please try to order by generation in ascending order, 132c86e55dSMatthew Auld * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 142c86e55dSMatthew Auld */ 152c86e55dSMatthew Auld 162c86e55dSMatthew Auld #ifndef __INTEL_GTT_H__ 172c86e55dSMatthew Auld #define __INTEL_GTT_H__ 182c86e55dSMatthew Auld 192c86e55dSMatthew Auld #include <linux/io-mapping.h> 202c86e55dSMatthew Auld #include <linux/kref.h> 212c86e55dSMatthew Auld #include <linux/mm.h> 222c86e55dSMatthew Auld #include <linux/pagevec.h> 232c86e55dSMatthew Auld #include <linux/scatterlist.h> 242c86e55dSMatthew Auld #include <linux/workqueue.h> 252c86e55dSMatthew Auld 262c86e55dSMatthew Auld #include <drm/drm_mm.h> 272c86e55dSMatthew Auld 282c86e55dSMatthew Auld #include "gt/intel_reset.h" 292c86e55dSMatthew Auld #include "i915_selftest.h" 3039a2bd34SThomas Hellström #include "i915_vma_resource.h" 312c86e55dSMatthew Auld #include "i915_vma_types.h" 3287bd701eSMatthew Auld #include "i915_params.h" 3387bd701eSMatthew Auld #include "intel_memory_region.h" 342c86e55dSMatthew Auld 352c86e55dSMatthew Auld #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 362c86e55dSMatthew Auld 372c86e55dSMatthew Auld #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT) 382c86e55dSMatthew Auld #define DBG(...) trace_printk(__VA_ARGS__) 392c86e55dSMatthew Auld #else 402c86e55dSMatthew Auld #define DBG(...) 412c86e55dSMatthew Auld #endif 422c86e55dSMatthew Auld 432c86e55dSMatthew Auld #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */ 442c86e55dSMatthew Auld 452c86e55dSMatthew Auld #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) 462c86e55dSMatthew Auld #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) 472c86e55dSMatthew Auld #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) 482c86e55dSMatthew Auld 492c86e55dSMatthew Auld #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 502c86e55dSMatthew Auld #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 512c86e55dSMatthew Auld 522c86e55dSMatthew Auld #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE 532c86e55dSMatthew Auld 542c86e55dSMatthew Auld #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 552c86e55dSMatthew Auld 562c86e55dSMatthew Auld #define I915_FENCE_REG_NONE -1 572c86e55dSMatthew Auld #define I915_MAX_NUM_FENCES 32 582c86e55dSMatthew Auld /* 32 fences + sign bit for FENCE_REG_NONE */ 592c86e55dSMatthew Auld #define I915_MAX_NUM_FENCE_BITS 6 602c86e55dSMatthew Auld 612c86e55dSMatthew Auld typedef u32 gen6_pte_t; 622c86e55dSMatthew Auld typedef u64 gen8_pte_t; 632c86e55dSMatthew Auld 642c86e55dSMatthew Auld #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT) 652c86e55dSMatthew Auld 662c86e55dSMatthew Auld #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 672c86e55dSMatthew Auld #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 682c86e55dSMatthew Auld #define I915_PDES 512 692c86e55dSMatthew Auld #define I915_PDE_MASK (I915_PDES - 1) 702c86e55dSMatthew Auld 712c86e55dSMatthew Auld /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 722c86e55dSMatthew Auld #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 732c86e55dSMatthew Auld #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 742c86e55dSMatthew Auld #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 752c86e55dSMatthew Auld #define GEN6_PTE_CACHE_LLC (2 << 1) 762c86e55dSMatthew Auld #define GEN6_PTE_UNCACHED (1 << 1) 772c86e55dSMatthew Auld #define GEN6_PTE_VALID REG_BIT(0) 782c86e55dSMatthew Auld 792c86e55dSMatthew Auld #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 802c86e55dSMatthew Auld #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 812c86e55dSMatthew Auld #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 822c86e55dSMatthew Auld #define GEN6_PDE_SHIFT 22 832c86e55dSMatthew Auld #define GEN6_PDE_VALID REG_BIT(0) 842c86e55dSMatthew Auld #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 852c86e55dSMatthew Auld 862c86e55dSMatthew Auld #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 872c86e55dSMatthew Auld 882c86e55dSMatthew Auld #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2) 892c86e55dSMatthew Auld #define BYT_PTE_WRITEABLE REG_BIT(1) 902c86e55dSMatthew Auld 9111724eeaSMatthew Auld #define GEN12_PPGTT_PTE_LM BIT_ULL(11) 92e762bdf5SMatthew Auld 93e762bdf5SMatthew Auld #define GEN12_GGTT_PTE_LM BIT_ULL(1) 9411724eeaSMatthew Auld 955189e312SMatthew Auld #define GEN12_PDE_64K BIT(6) 968133a6daSMatthew Auld #define GEN12_PTE_PS64 BIT(8) 975189e312SMatthew Auld 982c86e55dSMatthew Auld /* 992c86e55dSMatthew Auld * Cacheability Control is a 4-bit value. The low three bits are stored in bits 1002c86e55dSMatthew Auld * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 1012c86e55dSMatthew Auld */ 1022c86e55dSMatthew Auld #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 1032c86e55dSMatthew Auld (((bits) & 0x8) << (11 - 3))) 1042c86e55dSMatthew Auld #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 1052c86e55dSMatthew Auld #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 1062c86e55dSMatthew Auld #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 1072c86e55dSMatthew Auld #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 1082c86e55dSMatthew Auld #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 1092c86e55dSMatthew Auld #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 1102c86e55dSMatthew Auld #define HSW_PTE_UNCACHED (0) 1112c86e55dSMatthew Auld #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 1122c86e55dSMatthew Auld #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 1132c86e55dSMatthew Auld 1142c86e55dSMatthew Auld /* 1152c86e55dSMatthew Auld * GEN8 32b style address is defined as a 3 level page table: 1162c86e55dSMatthew Auld * 31:30 | 29:21 | 20:12 | 11:0 1172c86e55dSMatthew Auld * PDPE | PDE | PTE | offset 1182c86e55dSMatthew Auld * The difference as compared to normal x86 3 level page table is the PDPEs are 1192c86e55dSMatthew Auld * programmed via register. 1202c86e55dSMatthew Auld * 1212c86e55dSMatthew Auld * GEN8 48b style address is defined as a 4 level page table: 1222c86e55dSMatthew Auld * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 1232c86e55dSMatthew Auld * PML4E | PDPE | PDE | PTE | offset 1242c86e55dSMatthew Auld */ 1252c86e55dSMatthew Auld #define GEN8_3LVL_PDPES 4 1262c86e55dSMatthew Auld 1272c86e55dSMatthew Auld #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 1282c86e55dSMatthew Auld #define PPAT_CACHED_PDE 0 /* WB LLC */ 1292c86e55dSMatthew Auld #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 1302c86e55dSMatthew Auld #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 1312c86e55dSMatthew Auld 1322c86e55dSMatthew Auld #define CHV_PPAT_SNOOP REG_BIT(6) 1332c86e55dSMatthew Auld #define GEN8_PPAT_AGE(x) ((x)<<4) 1342c86e55dSMatthew Auld #define GEN8_PPAT_LLCeLLC (3<<2) 1352c86e55dSMatthew Auld #define GEN8_PPAT_LLCELLC (2<<2) 1362c86e55dSMatthew Auld #define GEN8_PPAT_LLC (1<<2) 1372c86e55dSMatthew Auld #define GEN8_PPAT_WB (3<<0) 1382c86e55dSMatthew Auld #define GEN8_PPAT_WT (2<<0) 1392c86e55dSMatthew Auld #define GEN8_PPAT_WC (1<<0) 1402c86e55dSMatthew Auld #define GEN8_PPAT_UC (0<<0) 1412c86e55dSMatthew Auld #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 1422c86e55dSMatthew Auld #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 1432c86e55dSMatthew Auld 1445f978167SMichael Cheng #define GEN8_PAGE_PRESENT BIT_ULL(0) 1455f978167SMichael Cheng #define GEN8_PAGE_RW BIT_ULL(1) 1465f978167SMichael Cheng 1472c86e55dSMatthew Auld #define GEN8_PDE_IPS_64K BIT(11) 1482c86e55dSMatthew Auld #define GEN8_PDE_PS_2M BIT(7) 1492c86e55dSMatthew Auld 15089351925SChris Wilson enum i915_cache_level; 15189351925SChris Wilson 15289351925SChris Wilson struct drm_i915_gem_object; 1530b6bc81dSChris Wilson struct i915_fence_reg; 15489351925SChris Wilson struct i915_vma; 15589351925SChris Wilson struct intel_gt; 1560b6bc81dSChris Wilson 1572c86e55dSMatthew Auld #define for_each_sgt_daddr(__dp, __iter, __sgt) \ 1582c86e55dSMatthew Auld __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE) 1592c86e55dSMatthew Auld 1602c86e55dSMatthew Auld struct i915_page_table { 16189351925SChris Wilson struct drm_i915_gem_object *base; 162cd0452aaSChris Wilson union { 1632c86e55dSMatthew Auld atomic_t used; 164cd0452aaSChris Wilson struct i915_page_table *stash; 165cd0452aaSChris Wilson }; 1665189e312SMatthew Auld bool is_compact; 1672c86e55dSMatthew Auld }; 1682c86e55dSMatthew Auld 1692c86e55dSMatthew Auld struct i915_page_directory { 1702c86e55dSMatthew Auld struct i915_page_table pt; 1712c86e55dSMatthew Auld spinlock_t lock; 17282adf901SChris Wilson void **entry; 1732c86e55dSMatthew Auld }; 1742c86e55dSMatthew Auld 1752c86e55dSMatthew Auld #define __px_choose_expr(x, type, expr, other) \ 1762c86e55dSMatthew Auld __builtin_choose_expr( \ 1772c86e55dSMatthew Auld __builtin_types_compatible_p(typeof(x), type) || \ 1782c86e55dSMatthew Auld __builtin_types_compatible_p(typeof(x), const type), \ 1792c86e55dSMatthew Auld ({ type __x = (type)(x); expr; }), \ 1802c86e55dSMatthew Auld other) 1812c86e55dSMatthew Auld 1822c86e55dSMatthew Auld #define px_base(px) \ 18389351925SChris Wilson __px_choose_expr(px, struct drm_i915_gem_object *, __x, \ 18489351925SChris Wilson __px_choose_expr(px, struct i915_page_table *, __x->base, \ 18589351925SChris Wilson __px_choose_expr(px, struct i915_page_directory *, __x->pt.base, \ 18689351925SChris Wilson (void)0))) 18789351925SChris Wilson 18889351925SChris Wilson struct page *__px_page(struct drm_i915_gem_object *p); 18989351925SChris Wilson dma_addr_t __px_dma(struct drm_i915_gem_object *p); 19089351925SChris Wilson #define px_dma(px) (__px_dma(px_base(px))) 1912c86e55dSMatthew Auld 192529b9ec8SMatthew Auld void *__px_vaddr(struct drm_i915_gem_object *p); 193529b9ec8SMatthew Auld #define px_vaddr(px) (__px_vaddr(px_base(px))) 194529b9ec8SMatthew Auld 1952c86e55dSMatthew Auld #define px_pt(px) \ 1962c86e55dSMatthew Auld __px_choose_expr(px, struct i915_page_table *, __x, \ 1972c86e55dSMatthew Auld __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \ 1982c86e55dSMatthew Auld (void)0)) 1992c86e55dSMatthew Auld #define px_used(px) (&px_pt(px)->used) 2002c86e55dSMatthew Auld 201cd0452aaSChris Wilson struct i915_vm_pt_stash { 202cd0452aaSChris Wilson /* preallocated chains of page tables/directories */ 203cd0452aaSChris Wilson struct i915_page_table *pt[2]; 2042cff4b9eSMatthew Auld /* 2052cff4b9eSMatthew Auld * Optionally override the alignment/size of the physical page that 2062cff4b9eSMatthew Auld * contains each PT. If not set defaults back to the usual 2072cff4b9eSMatthew Auld * I915_GTT_PAGE_SIZE_4K. This does not influence the other paging 2082cff4b9eSMatthew Auld * structures. MUST be a power-of-two. ONLY applicable on discrete 2092cff4b9eSMatthew Auld * platforms. 2102cff4b9eSMatthew Auld */ 2112cff4b9eSMatthew Auld int pt_sz; 212cd0452aaSChris Wilson }; 213cd0452aaSChris Wilson 2142c86e55dSMatthew Auld struct i915_vma_ops { 2152c86e55dSMatthew Auld /* Map an object into an address space with the given cache flags. */ 216cd0452aaSChris Wilson void (*bind_vma)(struct i915_address_space *vm, 217cd0452aaSChris Wilson struct i915_vm_pt_stash *stash, 21839a2bd34SThomas Hellström struct i915_vma_resource *vma_res, 2192c86e55dSMatthew Auld enum i915_cache_level cache_level, 2202c86e55dSMatthew Auld u32 flags); 2212c86e55dSMatthew Auld /* 2222c86e55dSMatthew Auld * Unmap an object from an address space. This usually consists of 2232c86e55dSMatthew Auld * setting the valid PTE entries to a reserved scratch page. 2242c86e55dSMatthew Auld */ 22512b07256SChris Wilson void (*unbind_vma)(struct i915_address_space *vm, 22639a2bd34SThomas Hellström struct i915_vma_resource *vma_res); 22739a2bd34SThomas Hellström 2282c86e55dSMatthew Auld }; 2292c86e55dSMatthew Auld 2302c86e55dSMatthew Auld struct i915_address_space { 2312c86e55dSMatthew Auld struct kref ref; 232dcc5d820SDaniel Vetter struct work_struct release_work; 2332c86e55dSMatthew Auld 2342c86e55dSMatthew Auld struct drm_mm mm; 2352c86e55dSMatthew Auld struct intel_gt *gt; 2362c86e55dSMatthew Auld struct drm_i915_private *i915; 2372c86e55dSMatthew Auld struct device *dma; 2382c86e55dSMatthew Auld u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 2392c86e55dSMatthew Auld u64 reserved; /* size addr space reserved */ 24087bd701eSMatthew Auld u64 min_alignment[INTEL_MEMORY_STOLEN_LOCAL + 1]; 2412c86e55dSMatthew Auld 2422c86e55dSMatthew Auld unsigned int bind_async_flags; 2432c86e55dSMatthew Auld 2442c86e55dSMatthew Auld struct mutex mutex; /* protects vma and our lists */ 2454d8151aeSThomas Hellström 2464d8151aeSThomas Hellström struct kref resv_ref; /* kref to keep the reservation lock alive. */ 2474d8151aeSThomas Hellström struct dma_resv _resv; /* reservation lock for all pd objects, and buffer pool */ 2482c86e55dSMatthew Auld #define VM_CLASS_GGTT 0 2492c86e55dSMatthew Auld #define VM_CLASS_PPGTT 1 25033e7a975SVille Syrjälä #define VM_CLASS_DPT 2 2512c86e55dSMatthew Auld 25289351925SChris Wilson struct drm_i915_gem_object *scratch[4]; 2532c86e55dSMatthew Auld /** 2542c86e55dSMatthew Auld * List of vma currently bound. 2552c86e55dSMatthew Auld */ 2562c86e55dSMatthew Auld struct list_head bound_list; 2572c86e55dSMatthew Auld 258e1a7ab4fSThomas Hellström /** 259e1a7ab4fSThomas Hellström * List of vmas not yet bound or evicted. 260e1a7ab4fSThomas Hellström */ 261e1a7ab4fSThomas Hellström struct list_head unbound_list; 262e1a7ab4fSThomas Hellström 2632c86e55dSMatthew Auld /* Global GTT */ 2642c86e55dSMatthew Auld bool is_ggtt:1; 2652c86e55dSMatthew Auld 26633e7a975SVille Syrjälä /* Display page table */ 26733e7a975SVille Syrjälä bool is_dpt:1; 26833e7a975SVille Syrjälä 2692c86e55dSMatthew Auld /* Some systems support read-only mappings for GGTT and/or PPGTT */ 2702c86e55dSMatthew Auld bool has_read_only:1; 2712c86e55dSMatthew Auld 272e1a7ab4fSThomas Hellström /* Skip pte rewrite on unbind for suspend. Protected by @mutex */ 273e1a7ab4fSThomas Hellström bool skip_pte_rewrite:1; 274e1a7ab4fSThomas Hellström 275cd0452aaSChris Wilson u8 top; 276cd0452aaSChris Wilson u8 pd_shift; 277cd0452aaSChris Wilson u8 scratch_order; 278cd0452aaSChris Wilson 279a259cc14SThomas Hellström /* Flags used when creating page-table objects for this vm */ 280a259cc14SThomas Hellström unsigned long lmem_pt_obj_flags; 281a259cc14SThomas Hellström 2822f6b90daSThomas Hellström /* Interval tree for pending unbind vma resources */ 2832f6b90daSThomas Hellström struct rb_root_cached pending_unbind; 2842f6b90daSThomas Hellström 28589351925SChris Wilson struct drm_i915_gem_object * 28689351925SChris Wilson (*alloc_pt_dma)(struct i915_address_space *vm, int sz); 287fef53be0SMatthew Auld struct drm_i915_gem_object * 288fef53be0SMatthew Auld (*alloc_scratch_dma)(struct i915_address_space *vm, int sz); 28989351925SChris Wilson 2902c86e55dSMatthew Auld u64 (*pte_encode)(dma_addr_t addr, 2912c86e55dSMatthew Auld enum i915_cache_level level, 2922c86e55dSMatthew Auld u32 flags); /* Create a valid PTE */ 2932c86e55dSMatthew Auld #define PTE_READ_ONLY BIT(0) 29411724eeaSMatthew Auld #define PTE_LM BIT(1) 2952c86e55dSMatthew Auld 296cd0452aaSChris Wilson void (*allocate_va_range)(struct i915_address_space *vm, 297cd0452aaSChris Wilson struct i915_vm_pt_stash *stash, 2982c86e55dSMatthew Auld u64 start, u64 length); 2992c86e55dSMatthew Auld void (*clear_range)(struct i915_address_space *vm, 3002c86e55dSMatthew Auld u64 start, u64 length); 301*b288d740SAndrzej Hajda void (*scratch_range)(struct i915_address_space *vm, 302*b288d740SAndrzej Hajda u64 start, u64 length); 3032c86e55dSMatthew Auld void (*insert_page)(struct i915_address_space *vm, 3042c86e55dSMatthew Auld dma_addr_t addr, 3052c86e55dSMatthew Auld u64 offset, 3062c86e55dSMatthew Auld enum i915_cache_level cache_level, 3072c86e55dSMatthew Auld u32 flags); 3082c86e55dSMatthew Auld void (*insert_entries)(struct i915_address_space *vm, 30939a2bd34SThomas Hellström struct i915_vma_resource *vma_res, 3102c86e55dSMatthew Auld enum i915_cache_level cache_level, 3112c86e55dSMatthew Auld u32 flags); 312a0696856SNirmoy Das void (*raw_insert_page)(struct i915_address_space *vm, 313a0696856SNirmoy Das dma_addr_t addr, 314a0696856SNirmoy Das u64 offset, 315a0696856SNirmoy Das enum i915_cache_level cache_level, 316a0696856SNirmoy Das u32 flags); 317a0696856SNirmoy Das void (*raw_insert_entries)(struct i915_address_space *vm, 318a0696856SNirmoy Das struct i915_vma_resource *vma_res, 319a0696856SNirmoy Das enum i915_cache_level cache_level, 320a0696856SNirmoy Das u32 flags); 3212c86e55dSMatthew Auld void (*cleanup)(struct i915_address_space *vm); 3222c86e55dSMatthew Auld 3233607e1e9SChris Wilson void (*foreach)(struct i915_address_space *vm, 3243607e1e9SChris Wilson u64 start, u64 length, 3253607e1e9SChris Wilson void (*fn)(struct i915_address_space *vm, 3263607e1e9SChris Wilson struct i915_page_table *pt, 3273607e1e9SChris Wilson void *data), 3283607e1e9SChris Wilson void *data); 3293607e1e9SChris Wilson 3302c86e55dSMatthew Auld struct i915_vma_ops vma_ops; 3312c86e55dSMatthew Auld 3322c86e55dSMatthew Auld I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 3332c86e55dSMatthew Auld I915_SELFTEST_DECLARE(bool scrub_64K); 3342c86e55dSMatthew Auld }; 3352c86e55dSMatthew Auld 3362c86e55dSMatthew Auld /* 3372c86e55dSMatthew Auld * The Graphics Translation Table is the way in which GEN hardware translates a 3382c86e55dSMatthew Auld * Graphics Virtual Address into a Physical Address. In addition to the normal 3392c86e55dSMatthew Auld * collateral associated with any va->pa translations GEN hardware also has a 3402c86e55dSMatthew Auld * portion of the GTT which can be mapped by the CPU and remain both coherent 3412c86e55dSMatthew Auld * and correct (in cases like swizzling). That region is referred to as GMADR in 3422c86e55dSMatthew Auld * the spec. 3432c86e55dSMatthew Auld */ 3442c86e55dSMatthew Auld struct i915_ggtt { 3452c86e55dSMatthew Auld struct i915_address_space vm; 3462c86e55dSMatthew Auld 3472c86e55dSMatthew Auld struct io_mapping iomap; /* Mapping to our CPU mappable region */ 3482c86e55dSMatthew Auld struct resource gmadr; /* GMADR resource */ 3492c86e55dSMatthew Auld resource_size_t mappable_end; /* End offset that we can CPU map */ 3502c86e55dSMatthew Auld 3512c86e55dSMatthew Auld /** "Graphics Stolen Memory" holds the global PTEs */ 3522c86e55dSMatthew Auld void __iomem *gsm; 3532c86e55dSMatthew Auld void (*invalidate)(struct i915_ggtt *ggtt); 3542c86e55dSMatthew Auld 3552c86e55dSMatthew Auld /** PPGTT used for aliasing the PPGTT with the GTT */ 3562c86e55dSMatthew Auld struct i915_ppgtt *alias; 3572c86e55dSMatthew Auld 3582c86e55dSMatthew Auld bool do_idle_maps; 3592c86e55dSMatthew Auld 3602c86e55dSMatthew Auld int mtrr; 3612c86e55dSMatthew Auld 3622c86e55dSMatthew Auld /** Bit 6 swizzling required for X tiling */ 3632c86e55dSMatthew Auld u32 bit_6_swizzle_x; 3642c86e55dSMatthew Auld /** Bit 6 swizzling required for Y tiling */ 3652c86e55dSMatthew Auld u32 bit_6_swizzle_y; 3662c86e55dSMatthew Auld 3672c86e55dSMatthew Auld u32 pin_bias; 3682c86e55dSMatthew Auld 3692c86e55dSMatthew Auld unsigned int num_fences; 3700b6bc81dSChris Wilson struct i915_fence_reg *fence_regs; 3712c86e55dSMatthew Auld struct list_head fence_list; 3722c86e55dSMatthew Auld 3732c86e55dSMatthew Auld /** 3742c86e55dSMatthew Auld * List of all objects in gtt_space, currently mmaped by userspace. 3752c86e55dSMatthew Auld * All objects within this list must also be on bound_list. 3762c86e55dSMatthew Auld */ 3772c86e55dSMatthew Auld struct list_head userfault_list; 3782c86e55dSMatthew Auld 379742379c0SChris Wilson struct mutex error_mutex; 3802c86e55dSMatthew Auld struct drm_mm_node error_capture; 3812c86e55dSMatthew Auld struct drm_mm_node uc_fw; 3820f857158SAravind Iddamsetty 3830f857158SAravind Iddamsetty /** List of GTs mapping this GGTT */ 3840f857158SAravind Iddamsetty struct list_head gt_list; 3852c86e55dSMatthew Auld }; 3862c86e55dSMatthew Auld 3872c86e55dSMatthew Auld struct i915_ppgtt { 3882c86e55dSMatthew Auld struct i915_address_space vm; 3892c86e55dSMatthew Auld 3902c86e55dSMatthew Auld struct i915_page_directory *pd; 3912c86e55dSMatthew Auld }; 3922c86e55dSMatthew Auld 3932c86e55dSMatthew Auld #define i915_is_ggtt(vm) ((vm)->is_ggtt) 39433e7a975SVille Syrjälä #define i915_is_dpt(vm) ((vm)->is_dpt) 39574862d4cSImre Deak #define i915_is_ggtt_or_dpt(vm) (i915_is_ggtt(vm) || i915_is_dpt(vm)) 3962c86e55dSMatthew Auld 397a7f46d5bSTvrtko Ursulin bool intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915); 398a7f46d5bSTvrtko Ursulin 39926ad4f8bSMaarten Lankhorst int __must_check 40026ad4f8bSMaarten Lankhorst i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww); 40126ad4f8bSMaarten Lankhorst 4022c86e55dSMatthew Auld static inline bool 4032c86e55dSMatthew Auld i915_vm_is_4lvl(const struct i915_address_space *vm) 4042c86e55dSMatthew Auld { 4052c86e55dSMatthew Auld return (vm->total - 1) >> 32; 4062c86e55dSMatthew Auld } 4072c86e55dSMatthew Auld 4082c86e55dSMatthew Auld static inline bool 4092c86e55dSMatthew Auld i915_vm_has_scratch_64K(struct i915_address_space *vm) 4102c86e55dSMatthew Auld { 4112c86e55dSMatthew Auld return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K); 4122c86e55dSMatthew Auld } 4132c86e55dSMatthew Auld 41487bd701eSMatthew Auld static inline u64 i915_vm_min_alignment(struct i915_address_space *vm, 41587bd701eSMatthew Auld enum intel_memory_type type) 41687bd701eSMatthew Auld { 41787bd701eSMatthew Auld /* avoid INTEL_MEMORY_MOCK overflow */ 41887bd701eSMatthew Auld if ((int)type >= ARRAY_SIZE(vm->min_alignment)) 41987bd701eSMatthew Auld type = INTEL_MEMORY_SYSTEM; 42087bd701eSMatthew Auld 42187bd701eSMatthew Auld return vm->min_alignment[type]; 42287bd701eSMatthew Auld } 42387bd701eSMatthew Auld 42487bd701eSMatthew Auld static inline u64 i915_vm_obj_min_alignment(struct i915_address_space *vm, 42587bd701eSMatthew Auld struct drm_i915_gem_object *obj) 42687bd701eSMatthew Auld { 42787bd701eSMatthew Auld struct intel_memory_region *mr = READ_ONCE(obj->mm.region); 42887bd701eSMatthew Auld enum intel_memory_type type = mr ? mr->type : INTEL_MEMORY_SYSTEM; 42987bd701eSMatthew Auld 43087bd701eSMatthew Auld return i915_vm_min_alignment(vm, type); 43187bd701eSMatthew Auld } 43287bd701eSMatthew Auld 4332c86e55dSMatthew Auld static inline bool 4342c86e55dSMatthew Auld i915_vm_has_cache_coloring(struct i915_address_space *vm) 4352c86e55dSMatthew Auld { 4362c86e55dSMatthew Auld return i915_is_ggtt(vm) && vm->mm.color_adjust; 4372c86e55dSMatthew Auld } 4382c86e55dSMatthew Auld 4392c86e55dSMatthew Auld static inline struct i915_ggtt * 4402c86e55dSMatthew Auld i915_vm_to_ggtt(struct i915_address_space *vm) 4412c86e55dSMatthew Auld { 4422c86e55dSMatthew Auld BUILD_BUG_ON(offsetof(struct i915_ggtt, vm)); 4432c86e55dSMatthew Auld GEM_BUG_ON(!i915_is_ggtt(vm)); 4442c86e55dSMatthew Auld return container_of(vm, struct i915_ggtt, vm); 4452c86e55dSMatthew Auld } 4462c86e55dSMatthew Auld 4472c86e55dSMatthew Auld static inline struct i915_ppgtt * 4482c86e55dSMatthew Auld i915_vm_to_ppgtt(struct i915_address_space *vm) 4492c86e55dSMatthew Auld { 4502c86e55dSMatthew Auld BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm)); 45174862d4cSImre Deak GEM_BUG_ON(i915_is_ggtt_or_dpt(vm)); 4522c86e55dSMatthew Auld return container_of(vm, struct i915_ppgtt, vm); 4532c86e55dSMatthew Auld } 4542c86e55dSMatthew Auld 4552c86e55dSMatthew Auld static inline struct i915_address_space * 4562c86e55dSMatthew Auld i915_vm_get(struct i915_address_space *vm) 4572c86e55dSMatthew Auld { 4582c86e55dSMatthew Auld kref_get(&vm->ref); 4592c86e55dSMatthew Auld return vm; 4602c86e55dSMatthew Auld } 4612c86e55dSMatthew Auld 462e1a7ab4fSThomas Hellström static inline struct i915_address_space * 463e1a7ab4fSThomas Hellström i915_vm_tryget(struct i915_address_space *vm) 464e1a7ab4fSThomas Hellström { 465e1a7ab4fSThomas Hellström return kref_get_unless_zero(&vm->ref) ? vm : NULL; 466e1a7ab4fSThomas Hellström } 467e1a7ab4fSThomas Hellström 468e1a7ab4fSThomas Hellström static inline void assert_vm_alive(struct i915_address_space *vm) 469e1a7ab4fSThomas Hellström { 470e1a7ab4fSThomas Hellström GEM_BUG_ON(!kref_read(&vm->ref)); 471e1a7ab4fSThomas Hellström } 472e1a7ab4fSThomas Hellström 4734d8151aeSThomas Hellström /** 4744d8151aeSThomas Hellström * i915_vm_resv_get - Obtain a reference on the vm's reservation lock 4754d8151aeSThomas Hellström * @vm: The vm whose reservation lock we want to share. 4764d8151aeSThomas Hellström * 4774d8151aeSThomas Hellström * Return: A pointer to the vm's reservation lock. 4784d8151aeSThomas Hellström */ 4794d8151aeSThomas Hellström static inline struct dma_resv *i915_vm_resv_get(struct i915_address_space *vm) 4804d8151aeSThomas Hellström { 4814d8151aeSThomas Hellström kref_get(&vm->resv_ref); 4824d8151aeSThomas Hellström return &vm->_resv; 4834d8151aeSThomas Hellström } 4844d8151aeSThomas Hellström 4852c86e55dSMatthew Auld void i915_vm_release(struct kref *kref); 4862c86e55dSMatthew Auld 4874d8151aeSThomas Hellström void i915_vm_resv_release(struct kref *kref); 4884d8151aeSThomas Hellström 4892c86e55dSMatthew Auld static inline void i915_vm_put(struct i915_address_space *vm) 4902c86e55dSMatthew Auld { 4912c86e55dSMatthew Auld kref_put(&vm->ref, i915_vm_release); 4922c86e55dSMatthew Auld } 4932c86e55dSMatthew Auld 4944d8151aeSThomas Hellström /** 4954d8151aeSThomas Hellström * i915_vm_resv_put - Release a reference on the vm's reservation lock 4964d8151aeSThomas Hellström * @resv: Pointer to a reservation lock obtained from i915_vm_resv_get() 4974d8151aeSThomas Hellström */ 4984d8151aeSThomas Hellström static inline void i915_vm_resv_put(struct i915_address_space *vm) 4994d8151aeSThomas Hellström { 5004d8151aeSThomas Hellström kref_put(&vm->resv_ref, i915_vm_resv_release); 5014d8151aeSThomas Hellström } 5024d8151aeSThomas Hellström 5032c86e55dSMatthew Auld void i915_address_space_init(struct i915_address_space *vm, int subclass); 5042c86e55dSMatthew Auld void i915_address_space_fini(struct i915_address_space *vm); 5052c86e55dSMatthew Auld 5062c86e55dSMatthew Auld static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 5072c86e55dSMatthew Auld { 5082c86e55dSMatthew Auld const u32 mask = NUM_PTE(pde_shift) - 1; 5092c86e55dSMatthew Auld 5102c86e55dSMatthew Auld return (address >> PAGE_SHIFT) & mask; 5112c86e55dSMatthew Auld } 5122c86e55dSMatthew Auld 5132c86e55dSMatthew Auld /* 5142c86e55dSMatthew Auld * Helper to counts the number of PTEs within the given length. This count 5152c86e55dSMatthew Auld * does not cross a page table boundary, so the max value would be 5162c86e55dSMatthew Auld * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 5172c86e55dSMatthew Auld */ 5182c86e55dSMatthew Auld static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 5192c86e55dSMatthew Auld { 5202c86e55dSMatthew Auld const u64 mask = ~((1ULL << pde_shift) - 1); 5212c86e55dSMatthew Auld u64 end; 5222c86e55dSMatthew Auld 5232c86e55dSMatthew Auld GEM_BUG_ON(length == 0); 5242c86e55dSMatthew Auld GEM_BUG_ON(offset_in_page(addr | length)); 5252c86e55dSMatthew Auld 5262c86e55dSMatthew Auld end = addr + length; 5272c86e55dSMatthew Auld 5282c86e55dSMatthew Auld if ((addr & mask) != (end & mask)) 5292c86e55dSMatthew Auld return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 5302c86e55dSMatthew Auld 5312c86e55dSMatthew Auld return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 5322c86e55dSMatthew Auld } 5332c86e55dSMatthew Auld 5342c86e55dSMatthew Auld static inline u32 i915_pde_index(u64 addr, u32 shift) 5352c86e55dSMatthew Auld { 5362c86e55dSMatthew Auld return (addr >> shift) & I915_PDE_MASK; 5372c86e55dSMatthew Auld } 5382c86e55dSMatthew Auld 5392c86e55dSMatthew Auld static inline struct i915_page_table * 5402c86e55dSMatthew Auld i915_pt_entry(const struct i915_page_directory * const pd, 5412c86e55dSMatthew Auld const unsigned short n) 5422c86e55dSMatthew Auld { 5432c86e55dSMatthew Auld return pd->entry[n]; 5442c86e55dSMatthew Auld } 5452c86e55dSMatthew Auld 5462c86e55dSMatthew Auld static inline struct i915_page_directory * 5472c86e55dSMatthew Auld i915_pd_entry(const struct i915_page_directory * const pdp, 5482c86e55dSMatthew Auld const unsigned short n) 5492c86e55dSMatthew Auld { 5502c86e55dSMatthew Auld return pdp->entry[n]; 5512c86e55dSMatthew Auld } 5522c86e55dSMatthew Auld 5532c86e55dSMatthew Auld static inline dma_addr_t 5542c86e55dSMatthew Auld i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n) 5552c86e55dSMatthew Auld { 55689351925SChris Wilson struct i915_page_table *pt = ppgtt->pd->entry[n]; 5572c86e55dSMatthew Auld 55889351925SChris Wilson return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]); 5592c86e55dSMatthew Auld } 5602c86e55dSMatthew Auld 561a259cc14SThomas Hellström void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt, 562a259cc14SThomas Hellström unsigned long lmem_pt_obj_flags); 5637a5c9223SCasey Bowman void intel_ggtt_bind_vma(struct i915_address_space *vm, 5647a5c9223SCasey Bowman struct i915_vm_pt_stash *stash, 5657a5c9223SCasey Bowman struct i915_vma_resource *vma_res, 5667a5c9223SCasey Bowman enum i915_cache_level cache_level, 5677a5c9223SCasey Bowman u32 flags); 5687a5c9223SCasey Bowman void intel_ggtt_unbind_vma(struct i915_address_space *vm, 5697a5c9223SCasey Bowman struct i915_vma_resource *vma_res); 5707a5c9223SCasey Bowman 5712c86e55dSMatthew Auld int i915_ggtt_probe_hw(struct drm_i915_private *i915); 5722c86e55dSMatthew Auld int i915_ggtt_init_hw(struct drm_i915_private *i915); 5732c86e55dSMatthew Auld int i915_ggtt_enable_hw(struct drm_i915_private *i915); 5742c86e55dSMatthew Auld int i915_init_ggtt(struct drm_i915_private *i915); 5752c86e55dSMatthew Auld void i915_ggtt_driver_release(struct drm_i915_private *i915); 5764d8151aeSThomas Hellström void i915_ggtt_driver_late_release(struct drm_i915_private *i915); 5770f857158SAravind Iddamsetty struct i915_ggtt *i915_ggtt_create(struct drm_i915_private *i915); 5782c86e55dSMatthew Auld 5792c86e55dSMatthew Auld static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt) 5802c86e55dSMatthew Auld { 5812c86e55dSMatthew Auld return ggtt->mappable_end > 0; 5822c86e55dSMatthew Auld } 5832c86e55dSMatthew Auld 5842c86e55dSMatthew Auld int i915_ppgtt_init_hw(struct intel_gt *gt); 5852c86e55dSMatthew Auld 586a259cc14SThomas Hellström struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt, 587a259cc14SThomas Hellström unsigned long lmem_pt_obj_flags); 5882c86e55dSMatthew Auld 5898d2f683fSImre Deak void i915_ggtt_suspend_vm(struct i915_address_space *vm); 5908d2f683fSImre Deak bool i915_ggtt_resume_vm(struct i915_address_space *vm); 591e986209cSChris Wilson void i915_ggtt_suspend(struct i915_ggtt *gtt); 592e986209cSChris Wilson void i915_ggtt_resume(struct i915_ggtt *ggtt); 5932c86e55dSMatthew Auld 5942c86e55dSMatthew Auld void 59589351925SChris Wilson fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count); 5962c86e55dSMatthew Auld 5972c86e55dSMatthew Auld #define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64)) 5982c86e55dSMatthew Auld #define fill32_px(px, v) do { \ 5992c86e55dSMatthew Auld u64 v__ = lower_32_bits(v); \ 6002c86e55dSMatthew Auld fill_px((px), v__ << 32 | v__); \ 6012c86e55dSMatthew Auld } while (0) 6022c86e55dSMatthew Auld 60389351925SChris Wilson int setup_scratch_page(struct i915_address_space *vm); 6042c86e55dSMatthew Auld void free_scratch(struct i915_address_space *vm); 6052c86e55dSMatthew Auld 60689351925SChris Wilson struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz); 6076aed5673SMatthew Auld struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz); 6082cff4b9eSMatthew Auld struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz); 6092c86e55dSMatthew Auld struct i915_page_directory *alloc_pd(struct i915_address_space *vm); 61082adf901SChris Wilson struct i915_page_directory *__alloc_pd(int npde); 6112c86e55dSMatthew Auld 612529b9ec8SMatthew Auld int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj); 613529b9ec8SMatthew Auld int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj); 6142c86e55dSMatthew Auld 61582adf901SChris Wilson void free_px(struct i915_address_space *vm, 61682adf901SChris Wilson struct i915_page_table *pt, int lvl); 61782adf901SChris Wilson #define free_pt(vm, px) free_px(vm, px, 0) 61882adf901SChris Wilson #define free_pd(vm, px) free_px(vm, px_pt(px), 1) 6192c86e55dSMatthew Auld 6202c86e55dSMatthew Auld void 6212c86e55dSMatthew Auld __set_pd_entry(struct i915_page_directory * const pd, 6222c86e55dSMatthew Auld const unsigned short idx, 62389351925SChris Wilson struct i915_page_table *pt, 6242c86e55dSMatthew Auld u64 (*encode)(const dma_addr_t, const enum i915_cache_level)); 6252c86e55dSMatthew Auld 6262c86e55dSMatthew Auld #define set_pd_entry(pd, idx, to) \ 62789351925SChris Wilson __set_pd_entry((pd), (idx), px_pt(to), gen8_pde_encode) 6282c86e55dSMatthew Auld 6292c86e55dSMatthew Auld void 6302c86e55dSMatthew Auld clear_pd_entry(struct i915_page_directory * const pd, 6312c86e55dSMatthew Auld const unsigned short idx, 63289351925SChris Wilson const struct drm_i915_gem_object * const scratch); 6332c86e55dSMatthew Auld 6342c86e55dSMatthew Auld bool 6352c86e55dSMatthew Auld release_pd_entry(struct i915_page_directory * const pd, 6362c86e55dSMatthew Auld const unsigned short idx, 6372c86e55dSMatthew Auld struct i915_page_table * const pt, 63889351925SChris Wilson const struct drm_i915_gem_object * const scratch); 6392c86e55dSMatthew Auld void gen6_ggtt_invalidate(struct i915_ggtt *ggtt); 6402c86e55dSMatthew Auld 641cd0452aaSChris Wilson void ppgtt_bind_vma(struct i915_address_space *vm, 642cd0452aaSChris Wilson struct i915_vm_pt_stash *stash, 64339a2bd34SThomas Hellström struct i915_vma_resource *vma_res, 64412b07256SChris Wilson enum i915_cache_level cache_level, 64512b07256SChris Wilson u32 flags); 64612b07256SChris Wilson void ppgtt_unbind_vma(struct i915_address_space *vm, 64739a2bd34SThomas Hellström struct i915_vma_resource *vma_res); 64812b07256SChris Wilson 6492c86e55dSMatthew Auld void gtt_write_workarounds(struct intel_gt *gt); 6502c86e55dSMatthew Auld 65177fa9efcSMatt Roper void setup_private_pat(struct intel_gt *gt); 6522c86e55dSMatthew Auld 653cd0452aaSChris Wilson int i915_vm_alloc_pt_stash(struct i915_address_space *vm, 654cd0452aaSChris Wilson struct i915_vm_pt_stash *stash, 655cd0452aaSChris Wilson u64 size); 656529b9ec8SMatthew Auld int i915_vm_map_pt_stash(struct i915_address_space *vm, 65789351925SChris Wilson struct i915_vm_pt_stash *stash); 658cd0452aaSChris Wilson void i915_vm_free_pt_stash(struct i915_address_space *vm, 659cd0452aaSChris Wilson struct i915_vm_pt_stash *stash); 660cd0452aaSChris Wilson 661a4d86249SChris Wilson struct i915_vma * 662a4d86249SChris Wilson __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size); 663a4d86249SChris Wilson 6642a665968SMaarten Lankhorst struct i915_vma * 6652a665968SMaarten Lankhorst __vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size); 6662a665968SMaarten Lankhorst 6672c86e55dSMatthew Auld static inline struct sgt_dma { 6682c86e55dSMatthew Auld struct scatterlist *sg; 6692c86e55dSMatthew Auld dma_addr_t dma, max; 67039a2bd34SThomas Hellström } sgt_dma(struct i915_vma_resource *vma_res) { 67139a2bd34SThomas Hellström struct scatterlist *sg = vma_res->bi.pages->sgl; 6722c86e55dSMatthew Auld dma_addr_t addr = sg_dma_address(sg); 6732c86e55dSMatthew Auld 6748a473dbaSTvrtko Ursulin return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) }; 6752c86e55dSMatthew Auld } 6762c86e55dSMatthew Auld 6772c86e55dSMatthew Auld #endif 678