12c86e55dSMatthew Auld /* SPDX-License-Identifier: MIT */ 22c86e55dSMatthew Auld /* 32c86e55dSMatthew Auld * Copyright © 2020 Intel Corporation 42c86e55dSMatthew Auld * 52c86e55dSMatthew Auld * Please try to maintain the following order within this file unless it makes 62c86e55dSMatthew Auld * sense to do otherwise. From top to bottom: 72c86e55dSMatthew Auld * 1. typedefs 82c86e55dSMatthew Auld * 2. #defines, and macros 92c86e55dSMatthew Auld * 3. structure definitions 102c86e55dSMatthew Auld * 4. function prototypes 112c86e55dSMatthew Auld * 122c86e55dSMatthew Auld * Within each section, please try to order by generation in ascending order, 132c86e55dSMatthew Auld * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 142c86e55dSMatthew Auld */ 152c86e55dSMatthew Auld 162c86e55dSMatthew Auld #ifndef __INTEL_GTT_H__ 172c86e55dSMatthew Auld #define __INTEL_GTT_H__ 182c86e55dSMatthew Auld 192c86e55dSMatthew Auld #include <linux/io-mapping.h> 202c86e55dSMatthew Auld #include <linux/kref.h> 212c86e55dSMatthew Auld #include <linux/mm.h> 222c86e55dSMatthew Auld #include <linux/pagevec.h> 232c86e55dSMatthew Auld #include <linux/scatterlist.h> 242c86e55dSMatthew Auld #include <linux/workqueue.h> 252c86e55dSMatthew Auld 262c86e55dSMatthew Auld #include <drm/drm_mm.h> 272c86e55dSMatthew Auld 282c86e55dSMatthew Auld #include "gt/intel_reset.h" 292c86e55dSMatthew Auld #include "i915_selftest.h" 3039a2bd34SThomas Hellström #include "i915_vma_resource.h" 312c86e55dSMatthew Auld #include "i915_vma_types.h" 3287bd701eSMatthew Auld #include "i915_params.h" 3387bd701eSMatthew Auld #include "intel_memory_region.h" 342c86e55dSMatthew Auld 352c86e55dSMatthew Auld #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 362c86e55dSMatthew Auld 372c86e55dSMatthew Auld #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT) 382c86e55dSMatthew Auld #define DBG(...) trace_printk(__VA_ARGS__) 392c86e55dSMatthew Auld #else 402c86e55dSMatthew Auld #define DBG(...) 412c86e55dSMatthew Auld #endif 422c86e55dSMatthew Auld 432c86e55dSMatthew Auld #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */ 442c86e55dSMatthew Auld 452c86e55dSMatthew Auld #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) 462c86e55dSMatthew Auld #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) 472c86e55dSMatthew Auld #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) 482c86e55dSMatthew Auld 492c86e55dSMatthew Auld #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 502c86e55dSMatthew Auld #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 512c86e55dSMatthew Auld 522c86e55dSMatthew Auld #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE 532c86e55dSMatthew Auld 542c86e55dSMatthew Auld #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 552c86e55dSMatthew Auld 562c86e55dSMatthew Auld #define I915_FENCE_REG_NONE -1 572c86e55dSMatthew Auld #define I915_MAX_NUM_FENCES 32 582c86e55dSMatthew Auld /* 32 fences + sign bit for FENCE_REG_NONE */ 592c86e55dSMatthew Auld #define I915_MAX_NUM_FENCE_BITS 6 602c86e55dSMatthew Auld 612c86e55dSMatthew Auld typedef u32 gen6_pte_t; 622c86e55dSMatthew Auld typedef u64 gen8_pte_t; 632c86e55dSMatthew Auld 642c86e55dSMatthew Auld #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT) 652c86e55dSMatthew Auld 662c86e55dSMatthew Auld #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 672c86e55dSMatthew Auld #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 682c86e55dSMatthew Auld #define I915_PDES 512 692c86e55dSMatthew Auld #define I915_PDE_MASK (I915_PDES - 1) 702c86e55dSMatthew Auld 712c86e55dSMatthew Auld /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 722c86e55dSMatthew Auld #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 732c86e55dSMatthew Auld #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 742c86e55dSMatthew Auld #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 752c86e55dSMatthew Auld #define GEN6_PTE_CACHE_LLC (2 << 1) 762c86e55dSMatthew Auld #define GEN6_PTE_UNCACHED (1 << 1) 772c86e55dSMatthew Auld #define GEN6_PTE_VALID REG_BIT(0) 782c86e55dSMatthew Auld 792c86e55dSMatthew Auld #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 802c86e55dSMatthew Auld #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 812c86e55dSMatthew Auld #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 822c86e55dSMatthew Auld #define GEN6_PDE_SHIFT 22 832c86e55dSMatthew Auld #define GEN6_PDE_VALID REG_BIT(0) 842c86e55dSMatthew Auld #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 852c86e55dSMatthew Auld 862c86e55dSMatthew Auld #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 872c86e55dSMatthew Auld 882c86e55dSMatthew Auld #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2) 892c86e55dSMatthew Auld #define BYT_PTE_WRITEABLE REG_BIT(1) 902c86e55dSMatthew Auld 91*341ad0e8SFei Yang #define MTL_PPGTT_PTE_PAT3 BIT_ULL(62) 9211724eeaSMatthew Auld #define GEN12_PPGTT_PTE_LM BIT_ULL(11) 93*341ad0e8SFei Yang #define GEN12_PPGTT_PTE_PAT2 BIT_ULL(7) 94*341ad0e8SFei Yang #define GEN12_PPGTT_PTE_PAT1 BIT_ULL(4) 95*341ad0e8SFei Yang #define GEN12_PPGTT_PTE_PAT0 BIT_ULL(3) 96e762bdf5SMatthew Auld 97e762bdf5SMatthew Auld #define GEN12_GGTT_PTE_LM BIT_ULL(1) 98*341ad0e8SFei Yang #define MTL_GGTT_PTE_PAT0 BIT_ULL(52) 99*341ad0e8SFei Yang #define MTL_GGTT_PTE_PAT1 BIT_ULL(53) 100*341ad0e8SFei Yang #define GEN12_GGTT_PTE_ADDR_MASK GENMASK_ULL(45, 12) 101*341ad0e8SFei Yang #define MTL_GGTT_PTE_PAT_MASK GENMASK_ULL(53, 52) 10211724eeaSMatthew Auld 1035189e312SMatthew Auld #define GEN12_PDE_64K BIT(6) 1048133a6daSMatthew Auld #define GEN12_PTE_PS64 BIT(8) 1055189e312SMatthew Auld 1062c86e55dSMatthew Auld /* 1072c86e55dSMatthew Auld * Cacheability Control is a 4-bit value. The low three bits are stored in bits 1082c86e55dSMatthew Auld * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 1092c86e55dSMatthew Auld */ 1102c86e55dSMatthew Auld #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 1112c86e55dSMatthew Auld (((bits) & 0x8) << (11 - 3))) 1122c86e55dSMatthew Auld #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 1132c86e55dSMatthew Auld #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 1142c86e55dSMatthew Auld #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 1152c86e55dSMatthew Auld #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 1162c86e55dSMatthew Auld #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 1172c86e55dSMatthew Auld #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 1182c86e55dSMatthew Auld #define HSW_PTE_UNCACHED (0) 1192c86e55dSMatthew Auld #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 1202c86e55dSMatthew Auld #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 1212c86e55dSMatthew Auld 1222c86e55dSMatthew Auld /* 1232c86e55dSMatthew Auld * GEN8 32b style address is defined as a 3 level page table: 1242c86e55dSMatthew Auld * 31:30 | 29:21 | 20:12 | 11:0 1252c86e55dSMatthew Auld * PDPE | PDE | PTE | offset 1262c86e55dSMatthew Auld * The difference as compared to normal x86 3 level page table is the PDPEs are 1272c86e55dSMatthew Auld * programmed via register. 1282c86e55dSMatthew Auld * 1292c86e55dSMatthew Auld * GEN8 48b style address is defined as a 4 level page table: 1302c86e55dSMatthew Auld * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 1312c86e55dSMatthew Auld * PML4E | PDPE | PDE | PTE | offset 1322c86e55dSMatthew Auld */ 1332c86e55dSMatthew Auld #define GEN8_3LVL_PDPES 4 1342c86e55dSMatthew Auld 1352c86e55dSMatthew Auld #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 1362c86e55dSMatthew Auld #define PPAT_CACHED_PDE 0 /* WB LLC */ 1372c86e55dSMatthew Auld #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 1382c86e55dSMatthew Auld #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 1392c86e55dSMatthew Auld 1402c86e55dSMatthew Auld #define CHV_PPAT_SNOOP REG_BIT(6) 1412c86e55dSMatthew Auld #define GEN8_PPAT_AGE(x) ((x)<<4) 1422c86e55dSMatthew Auld #define GEN8_PPAT_LLCeLLC (3<<2) 1432c86e55dSMatthew Auld #define GEN8_PPAT_LLCELLC (2<<2) 1442c86e55dSMatthew Auld #define GEN8_PPAT_LLC (1<<2) 1452c86e55dSMatthew Auld #define GEN8_PPAT_WB (3<<0) 1462c86e55dSMatthew Auld #define GEN8_PPAT_WT (2<<0) 1472c86e55dSMatthew Auld #define GEN8_PPAT_WC (1<<0) 1482c86e55dSMatthew Auld #define GEN8_PPAT_UC (0<<0) 1492c86e55dSMatthew Auld #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 1502c86e55dSMatthew Auld #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 1512c86e55dSMatthew Auld 1525f978167SMichael Cheng #define GEN8_PAGE_PRESENT BIT_ULL(0) 1535f978167SMichael Cheng #define GEN8_PAGE_RW BIT_ULL(1) 1545f978167SMichael Cheng 1552c86e55dSMatthew Auld #define GEN8_PDE_IPS_64K BIT(11) 1562c86e55dSMatthew Auld #define GEN8_PDE_PS_2M BIT(7) 1572c86e55dSMatthew Auld 158b76c0deeSMadhumitha Tolakanahalli Pradeep #define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2) 159b76c0deeSMadhumitha Tolakanahalli Pradeep #define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0) 160b76c0deeSMadhumitha Tolakanahalli Pradeep #define MTL_PPAT_L4_3_UC REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3) 161b76c0deeSMadhumitha Tolakanahalli Pradeep #define MTL_PPAT_L4_1_WT REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1) 162b76c0deeSMadhumitha Tolakanahalli Pradeep #define MTL_PPAT_L4_0_WB REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0) 163b76c0deeSMadhumitha Tolakanahalli Pradeep #define MTL_3_COH_2W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3) 164b76c0deeSMadhumitha Tolakanahalli Pradeep #define MTL_2_COH_1W REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2) 165b76c0deeSMadhumitha Tolakanahalli Pradeep 16689351925SChris Wilson enum i915_cache_level; 16789351925SChris Wilson 16889351925SChris Wilson struct drm_i915_gem_object; 1690b6bc81dSChris Wilson struct i915_fence_reg; 17089351925SChris Wilson struct i915_vma; 17189351925SChris Wilson struct intel_gt; 1720b6bc81dSChris Wilson 1732c86e55dSMatthew Auld #define for_each_sgt_daddr(__dp, __iter, __sgt) \ 1742c86e55dSMatthew Auld __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE) 1752c86e55dSMatthew Auld 1762c86e55dSMatthew Auld struct i915_page_table { 17789351925SChris Wilson struct drm_i915_gem_object *base; 178cd0452aaSChris Wilson union { 1792c86e55dSMatthew Auld atomic_t used; 180cd0452aaSChris Wilson struct i915_page_table *stash; 181cd0452aaSChris Wilson }; 1825189e312SMatthew Auld bool is_compact; 1832c86e55dSMatthew Auld }; 1842c86e55dSMatthew Auld 1852c86e55dSMatthew Auld struct i915_page_directory { 1862c86e55dSMatthew Auld struct i915_page_table pt; 1872c86e55dSMatthew Auld spinlock_t lock; 18882adf901SChris Wilson void **entry; 1892c86e55dSMatthew Auld }; 1902c86e55dSMatthew Auld 1912c86e55dSMatthew Auld #define __px_choose_expr(x, type, expr, other) \ 1922c86e55dSMatthew Auld __builtin_choose_expr( \ 1932c86e55dSMatthew Auld __builtin_types_compatible_p(typeof(x), type) || \ 1942c86e55dSMatthew Auld __builtin_types_compatible_p(typeof(x), const type), \ 1952c86e55dSMatthew Auld ({ type __x = (type)(x); expr; }), \ 1962c86e55dSMatthew Auld other) 1972c86e55dSMatthew Auld 1982c86e55dSMatthew Auld #define px_base(px) \ 19989351925SChris Wilson __px_choose_expr(px, struct drm_i915_gem_object *, __x, \ 20089351925SChris Wilson __px_choose_expr(px, struct i915_page_table *, __x->base, \ 20189351925SChris Wilson __px_choose_expr(px, struct i915_page_directory *, __x->pt.base, \ 20289351925SChris Wilson (void)0))) 20389351925SChris Wilson 20489351925SChris Wilson struct page *__px_page(struct drm_i915_gem_object *p); 20589351925SChris Wilson dma_addr_t __px_dma(struct drm_i915_gem_object *p); 20689351925SChris Wilson #define px_dma(px) (__px_dma(px_base(px))) 2072c86e55dSMatthew Auld 208529b9ec8SMatthew Auld void *__px_vaddr(struct drm_i915_gem_object *p); 209529b9ec8SMatthew Auld #define px_vaddr(px) (__px_vaddr(px_base(px))) 210529b9ec8SMatthew Auld 2112c86e55dSMatthew Auld #define px_pt(px) \ 2122c86e55dSMatthew Auld __px_choose_expr(px, struct i915_page_table *, __x, \ 2132c86e55dSMatthew Auld __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \ 2142c86e55dSMatthew Auld (void)0)) 2152c86e55dSMatthew Auld #define px_used(px) (&px_pt(px)->used) 2162c86e55dSMatthew Auld 217cd0452aaSChris Wilson struct i915_vm_pt_stash { 218cd0452aaSChris Wilson /* preallocated chains of page tables/directories */ 219cd0452aaSChris Wilson struct i915_page_table *pt[2]; 2202cff4b9eSMatthew Auld /* 2212cff4b9eSMatthew Auld * Optionally override the alignment/size of the physical page that 2222cff4b9eSMatthew Auld * contains each PT. If not set defaults back to the usual 2232cff4b9eSMatthew Auld * I915_GTT_PAGE_SIZE_4K. This does not influence the other paging 2242cff4b9eSMatthew Auld * structures. MUST be a power-of-two. ONLY applicable on discrete 2252cff4b9eSMatthew Auld * platforms. 2262cff4b9eSMatthew Auld */ 2272cff4b9eSMatthew Auld int pt_sz; 228cd0452aaSChris Wilson }; 229cd0452aaSChris Wilson 2302c86e55dSMatthew Auld struct i915_vma_ops { 2312c86e55dSMatthew Auld /* Map an object into an address space with the given cache flags. */ 232cd0452aaSChris Wilson void (*bind_vma)(struct i915_address_space *vm, 233cd0452aaSChris Wilson struct i915_vm_pt_stash *stash, 23439a2bd34SThomas Hellström struct i915_vma_resource *vma_res, 2352c86e55dSMatthew Auld enum i915_cache_level cache_level, 2362c86e55dSMatthew Auld u32 flags); 2372c86e55dSMatthew Auld /* 2382c86e55dSMatthew Auld * Unmap an object from an address space. This usually consists of 2392c86e55dSMatthew Auld * setting the valid PTE entries to a reserved scratch page. 2402c86e55dSMatthew Auld */ 24112b07256SChris Wilson void (*unbind_vma)(struct i915_address_space *vm, 24239a2bd34SThomas Hellström struct i915_vma_resource *vma_res); 24339a2bd34SThomas Hellström 2442c86e55dSMatthew Auld }; 2452c86e55dSMatthew Auld 2462c86e55dSMatthew Auld struct i915_address_space { 2472c86e55dSMatthew Auld struct kref ref; 248dcc5d820SDaniel Vetter struct work_struct release_work; 2492c86e55dSMatthew Auld 2502c86e55dSMatthew Auld struct drm_mm mm; 2512c86e55dSMatthew Auld struct intel_gt *gt; 2522c86e55dSMatthew Auld struct drm_i915_private *i915; 2532c86e55dSMatthew Auld struct device *dma; 2542c86e55dSMatthew Auld u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 2552c86e55dSMatthew Auld u64 reserved; /* size addr space reserved */ 25687bd701eSMatthew Auld u64 min_alignment[INTEL_MEMORY_STOLEN_LOCAL + 1]; 2572c86e55dSMatthew Auld 2582c86e55dSMatthew Auld unsigned int bind_async_flags; 2592c86e55dSMatthew Auld 2602c86e55dSMatthew Auld struct mutex mutex; /* protects vma and our lists */ 2614d8151aeSThomas Hellström 2624d8151aeSThomas Hellström struct kref resv_ref; /* kref to keep the reservation lock alive. */ 2634d8151aeSThomas Hellström struct dma_resv _resv; /* reservation lock for all pd objects, and buffer pool */ 2642c86e55dSMatthew Auld #define VM_CLASS_GGTT 0 2652c86e55dSMatthew Auld #define VM_CLASS_PPGTT 1 26633e7a975SVille Syrjälä #define VM_CLASS_DPT 2 2672c86e55dSMatthew Auld 26889351925SChris Wilson struct drm_i915_gem_object *scratch[4]; 2692c86e55dSMatthew Auld /** 2702c86e55dSMatthew Auld * List of vma currently bound. 2712c86e55dSMatthew Auld */ 2722c86e55dSMatthew Auld struct list_head bound_list; 2732c86e55dSMatthew Auld 274e1a7ab4fSThomas Hellström /** 275e1a7ab4fSThomas Hellström * List of vmas not yet bound or evicted. 276e1a7ab4fSThomas Hellström */ 277e1a7ab4fSThomas Hellström struct list_head unbound_list; 278e1a7ab4fSThomas Hellström 2792c86e55dSMatthew Auld /* Global GTT */ 2802c86e55dSMatthew Auld bool is_ggtt:1; 2812c86e55dSMatthew Auld 28233e7a975SVille Syrjälä /* Display page table */ 28333e7a975SVille Syrjälä bool is_dpt:1; 28433e7a975SVille Syrjälä 2852c86e55dSMatthew Auld /* Some systems support read-only mappings for GGTT and/or PPGTT */ 2862c86e55dSMatthew Auld bool has_read_only:1; 2872c86e55dSMatthew Auld 288e1a7ab4fSThomas Hellström /* Skip pte rewrite on unbind for suspend. Protected by @mutex */ 289e1a7ab4fSThomas Hellström bool skip_pte_rewrite:1; 290e1a7ab4fSThomas Hellström 291cd0452aaSChris Wilson u8 top; 292cd0452aaSChris Wilson u8 pd_shift; 293cd0452aaSChris Wilson u8 scratch_order; 294cd0452aaSChris Wilson 295a259cc14SThomas Hellström /* Flags used when creating page-table objects for this vm */ 296a259cc14SThomas Hellström unsigned long lmem_pt_obj_flags; 297a259cc14SThomas Hellström 2982f6b90daSThomas Hellström /* Interval tree for pending unbind vma resources */ 2992f6b90daSThomas Hellström struct rb_root_cached pending_unbind; 3002f6b90daSThomas Hellström 30189351925SChris Wilson struct drm_i915_gem_object * 30289351925SChris Wilson (*alloc_pt_dma)(struct i915_address_space *vm, int sz); 303fef53be0SMatthew Auld struct drm_i915_gem_object * 304fef53be0SMatthew Auld (*alloc_scratch_dma)(struct i915_address_space *vm, int sz); 30589351925SChris Wilson 3062c86e55dSMatthew Auld u64 (*pte_encode)(dma_addr_t addr, 3072c86e55dSMatthew Auld enum i915_cache_level level, 3082c86e55dSMatthew Auld u32 flags); /* Create a valid PTE */ 3092c86e55dSMatthew Auld #define PTE_READ_ONLY BIT(0) 31011724eeaSMatthew Auld #define PTE_LM BIT(1) 3112c86e55dSMatthew Auld 312cd0452aaSChris Wilson void (*allocate_va_range)(struct i915_address_space *vm, 313cd0452aaSChris Wilson struct i915_vm_pt_stash *stash, 3142c86e55dSMatthew Auld u64 start, u64 length); 3152c86e55dSMatthew Auld void (*clear_range)(struct i915_address_space *vm, 3162c86e55dSMatthew Auld u64 start, u64 length); 317b288d740SAndrzej Hajda void (*scratch_range)(struct i915_address_space *vm, 318b288d740SAndrzej Hajda u64 start, u64 length); 3192c86e55dSMatthew Auld void (*insert_page)(struct i915_address_space *vm, 3202c86e55dSMatthew Auld dma_addr_t addr, 3212c86e55dSMatthew Auld u64 offset, 3222c86e55dSMatthew Auld enum i915_cache_level cache_level, 3232c86e55dSMatthew Auld u32 flags); 3242c86e55dSMatthew Auld void (*insert_entries)(struct i915_address_space *vm, 32539a2bd34SThomas Hellström struct i915_vma_resource *vma_res, 3262c86e55dSMatthew Auld enum i915_cache_level cache_level, 3272c86e55dSMatthew Auld u32 flags); 328a0696856SNirmoy Das void (*raw_insert_page)(struct i915_address_space *vm, 329a0696856SNirmoy Das dma_addr_t addr, 330a0696856SNirmoy Das u64 offset, 331a0696856SNirmoy Das enum i915_cache_level cache_level, 332a0696856SNirmoy Das u32 flags); 333a0696856SNirmoy Das void (*raw_insert_entries)(struct i915_address_space *vm, 334a0696856SNirmoy Das struct i915_vma_resource *vma_res, 335a0696856SNirmoy Das enum i915_cache_level cache_level, 336a0696856SNirmoy Das u32 flags); 3372c86e55dSMatthew Auld void (*cleanup)(struct i915_address_space *vm); 3382c86e55dSMatthew Auld 3393607e1e9SChris Wilson void (*foreach)(struct i915_address_space *vm, 3403607e1e9SChris Wilson u64 start, u64 length, 3413607e1e9SChris Wilson void (*fn)(struct i915_address_space *vm, 3423607e1e9SChris Wilson struct i915_page_table *pt, 3433607e1e9SChris Wilson void *data), 3443607e1e9SChris Wilson void *data); 3453607e1e9SChris Wilson 3462c86e55dSMatthew Auld struct i915_vma_ops vma_ops; 3472c86e55dSMatthew Auld 3482c86e55dSMatthew Auld I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 3492c86e55dSMatthew Auld I915_SELFTEST_DECLARE(bool scrub_64K); 3502c86e55dSMatthew Auld }; 3512c86e55dSMatthew Auld 3522c86e55dSMatthew Auld /* 3532c86e55dSMatthew Auld * The Graphics Translation Table is the way in which GEN hardware translates a 3542c86e55dSMatthew Auld * Graphics Virtual Address into a Physical Address. In addition to the normal 3552c86e55dSMatthew Auld * collateral associated with any va->pa translations GEN hardware also has a 3562c86e55dSMatthew Auld * portion of the GTT which can be mapped by the CPU and remain both coherent 3572c86e55dSMatthew Auld * and correct (in cases like swizzling). That region is referred to as GMADR in 3582c86e55dSMatthew Auld * the spec. 3592c86e55dSMatthew Auld */ 3602c86e55dSMatthew Auld struct i915_ggtt { 3612c86e55dSMatthew Auld struct i915_address_space vm; 3622c86e55dSMatthew Auld 3632c86e55dSMatthew Auld struct io_mapping iomap; /* Mapping to our CPU mappable region */ 3642c86e55dSMatthew Auld struct resource gmadr; /* GMADR resource */ 3652c86e55dSMatthew Auld resource_size_t mappable_end; /* End offset that we can CPU map */ 3662c86e55dSMatthew Auld 3672c86e55dSMatthew Auld /** "Graphics Stolen Memory" holds the global PTEs */ 3682c86e55dSMatthew Auld void __iomem *gsm; 3692c86e55dSMatthew Auld void (*invalidate)(struct i915_ggtt *ggtt); 3702c86e55dSMatthew Auld 3712c86e55dSMatthew Auld /** PPGTT used for aliasing the PPGTT with the GTT */ 3722c86e55dSMatthew Auld struct i915_ppgtt *alias; 3732c86e55dSMatthew Auld 3742c86e55dSMatthew Auld bool do_idle_maps; 3752c86e55dSMatthew Auld 3762c86e55dSMatthew Auld int mtrr; 3772c86e55dSMatthew Auld 3782c86e55dSMatthew Auld /** Bit 6 swizzling required for X tiling */ 3792c86e55dSMatthew Auld u32 bit_6_swizzle_x; 3802c86e55dSMatthew Auld /** Bit 6 swizzling required for Y tiling */ 3812c86e55dSMatthew Auld u32 bit_6_swizzle_y; 3822c86e55dSMatthew Auld 3832c86e55dSMatthew Auld u32 pin_bias; 3842c86e55dSMatthew Auld 3852c86e55dSMatthew Auld unsigned int num_fences; 3860b6bc81dSChris Wilson struct i915_fence_reg *fence_regs; 3872c86e55dSMatthew Auld struct list_head fence_list; 3882c86e55dSMatthew Auld 3892c86e55dSMatthew Auld /** 3902c86e55dSMatthew Auld * List of all objects in gtt_space, currently mmaped by userspace. 3912c86e55dSMatthew Auld * All objects within this list must also be on bound_list. 3922c86e55dSMatthew Auld */ 3932c86e55dSMatthew Auld struct list_head userfault_list; 3942c86e55dSMatthew Auld 395742379c0SChris Wilson struct mutex error_mutex; 3962c86e55dSMatthew Auld struct drm_mm_node error_capture; 3972c86e55dSMatthew Auld struct drm_mm_node uc_fw; 3980f857158SAravind Iddamsetty 3990f857158SAravind Iddamsetty /** List of GTs mapping this GGTT */ 4000f857158SAravind Iddamsetty struct list_head gt_list; 4012c86e55dSMatthew Auld }; 4022c86e55dSMatthew Auld 4032c86e55dSMatthew Auld struct i915_ppgtt { 4042c86e55dSMatthew Auld struct i915_address_space vm; 4052c86e55dSMatthew Auld 4062c86e55dSMatthew Auld struct i915_page_directory *pd; 4072c86e55dSMatthew Auld }; 4082c86e55dSMatthew Auld 4092c86e55dSMatthew Auld #define i915_is_ggtt(vm) ((vm)->is_ggtt) 41033e7a975SVille Syrjälä #define i915_is_dpt(vm) ((vm)->is_dpt) 41174862d4cSImre Deak #define i915_is_ggtt_or_dpt(vm) (i915_is_ggtt(vm) || i915_is_dpt(vm)) 4122c86e55dSMatthew Auld 413a7f46d5bSTvrtko Ursulin bool intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915); 414a7f46d5bSTvrtko Ursulin 41526ad4f8bSMaarten Lankhorst int __must_check 41626ad4f8bSMaarten Lankhorst i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww); 41726ad4f8bSMaarten Lankhorst 4182c86e55dSMatthew Auld static inline bool 4192c86e55dSMatthew Auld i915_vm_is_4lvl(const struct i915_address_space *vm) 4202c86e55dSMatthew Auld { 4212c86e55dSMatthew Auld return (vm->total - 1) >> 32; 4222c86e55dSMatthew Auld } 4232c86e55dSMatthew Auld 4242c86e55dSMatthew Auld static inline bool 4252c86e55dSMatthew Auld i915_vm_has_scratch_64K(struct i915_address_space *vm) 4262c86e55dSMatthew Auld { 4272c86e55dSMatthew Auld return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K); 4282c86e55dSMatthew Auld } 4292c86e55dSMatthew Auld 43087bd701eSMatthew Auld static inline u64 i915_vm_min_alignment(struct i915_address_space *vm, 43187bd701eSMatthew Auld enum intel_memory_type type) 43287bd701eSMatthew Auld { 43387bd701eSMatthew Auld /* avoid INTEL_MEMORY_MOCK overflow */ 43487bd701eSMatthew Auld if ((int)type >= ARRAY_SIZE(vm->min_alignment)) 43587bd701eSMatthew Auld type = INTEL_MEMORY_SYSTEM; 43687bd701eSMatthew Auld 43787bd701eSMatthew Auld return vm->min_alignment[type]; 43887bd701eSMatthew Auld } 43987bd701eSMatthew Auld 44087bd701eSMatthew Auld static inline u64 i915_vm_obj_min_alignment(struct i915_address_space *vm, 44187bd701eSMatthew Auld struct drm_i915_gem_object *obj) 44287bd701eSMatthew Auld { 44387bd701eSMatthew Auld struct intel_memory_region *mr = READ_ONCE(obj->mm.region); 44487bd701eSMatthew Auld enum intel_memory_type type = mr ? mr->type : INTEL_MEMORY_SYSTEM; 44587bd701eSMatthew Auld 44687bd701eSMatthew Auld return i915_vm_min_alignment(vm, type); 44787bd701eSMatthew Auld } 44887bd701eSMatthew Auld 4492c86e55dSMatthew Auld static inline bool 4502c86e55dSMatthew Auld i915_vm_has_cache_coloring(struct i915_address_space *vm) 4512c86e55dSMatthew Auld { 4522c86e55dSMatthew Auld return i915_is_ggtt(vm) && vm->mm.color_adjust; 4532c86e55dSMatthew Auld } 4542c86e55dSMatthew Auld 4552c86e55dSMatthew Auld static inline struct i915_ggtt * 4562c86e55dSMatthew Auld i915_vm_to_ggtt(struct i915_address_space *vm) 4572c86e55dSMatthew Auld { 4582c86e55dSMatthew Auld BUILD_BUG_ON(offsetof(struct i915_ggtt, vm)); 4592c86e55dSMatthew Auld GEM_BUG_ON(!i915_is_ggtt(vm)); 4602c86e55dSMatthew Auld return container_of(vm, struct i915_ggtt, vm); 4612c86e55dSMatthew Auld } 4622c86e55dSMatthew Auld 4632c86e55dSMatthew Auld static inline struct i915_ppgtt * 4642c86e55dSMatthew Auld i915_vm_to_ppgtt(struct i915_address_space *vm) 4652c86e55dSMatthew Auld { 4662c86e55dSMatthew Auld BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm)); 46774862d4cSImre Deak GEM_BUG_ON(i915_is_ggtt_or_dpt(vm)); 4682c86e55dSMatthew Auld return container_of(vm, struct i915_ppgtt, vm); 4692c86e55dSMatthew Auld } 4702c86e55dSMatthew Auld 4712c86e55dSMatthew Auld static inline struct i915_address_space * 4722c86e55dSMatthew Auld i915_vm_get(struct i915_address_space *vm) 4732c86e55dSMatthew Auld { 4742c86e55dSMatthew Auld kref_get(&vm->ref); 4752c86e55dSMatthew Auld return vm; 4762c86e55dSMatthew Auld } 4772c86e55dSMatthew Auld 478e1a7ab4fSThomas Hellström static inline struct i915_address_space * 479e1a7ab4fSThomas Hellström i915_vm_tryget(struct i915_address_space *vm) 480e1a7ab4fSThomas Hellström { 481e1a7ab4fSThomas Hellström return kref_get_unless_zero(&vm->ref) ? vm : NULL; 482e1a7ab4fSThomas Hellström } 483e1a7ab4fSThomas Hellström 484e1a7ab4fSThomas Hellström static inline void assert_vm_alive(struct i915_address_space *vm) 485e1a7ab4fSThomas Hellström { 486e1a7ab4fSThomas Hellström GEM_BUG_ON(!kref_read(&vm->ref)); 487e1a7ab4fSThomas Hellström } 488e1a7ab4fSThomas Hellström 4894d8151aeSThomas Hellström /** 4904d8151aeSThomas Hellström * i915_vm_resv_get - Obtain a reference on the vm's reservation lock 4914d8151aeSThomas Hellström * @vm: The vm whose reservation lock we want to share. 4924d8151aeSThomas Hellström * 4934d8151aeSThomas Hellström * Return: A pointer to the vm's reservation lock. 4944d8151aeSThomas Hellström */ 4954d8151aeSThomas Hellström static inline struct dma_resv *i915_vm_resv_get(struct i915_address_space *vm) 4964d8151aeSThomas Hellström { 4974d8151aeSThomas Hellström kref_get(&vm->resv_ref); 4984d8151aeSThomas Hellström return &vm->_resv; 4994d8151aeSThomas Hellström } 5004d8151aeSThomas Hellström 5012c86e55dSMatthew Auld void i915_vm_release(struct kref *kref); 5022c86e55dSMatthew Auld 5034d8151aeSThomas Hellström void i915_vm_resv_release(struct kref *kref); 5044d8151aeSThomas Hellström 5052c86e55dSMatthew Auld static inline void i915_vm_put(struct i915_address_space *vm) 5062c86e55dSMatthew Auld { 5072c86e55dSMatthew Auld kref_put(&vm->ref, i915_vm_release); 5082c86e55dSMatthew Auld } 5092c86e55dSMatthew Auld 5104d8151aeSThomas Hellström /** 5114d8151aeSThomas Hellström * i915_vm_resv_put - Release a reference on the vm's reservation lock 5124d8151aeSThomas Hellström * @resv: Pointer to a reservation lock obtained from i915_vm_resv_get() 5134d8151aeSThomas Hellström */ 5144d8151aeSThomas Hellström static inline void i915_vm_resv_put(struct i915_address_space *vm) 5154d8151aeSThomas Hellström { 5164d8151aeSThomas Hellström kref_put(&vm->resv_ref, i915_vm_resv_release); 5174d8151aeSThomas Hellström } 5184d8151aeSThomas Hellström 5192c86e55dSMatthew Auld void i915_address_space_init(struct i915_address_space *vm, int subclass); 5202c86e55dSMatthew Auld void i915_address_space_fini(struct i915_address_space *vm); 5212c86e55dSMatthew Auld 5222c86e55dSMatthew Auld static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 5232c86e55dSMatthew Auld { 5242c86e55dSMatthew Auld const u32 mask = NUM_PTE(pde_shift) - 1; 5252c86e55dSMatthew Auld 5262c86e55dSMatthew Auld return (address >> PAGE_SHIFT) & mask; 5272c86e55dSMatthew Auld } 5282c86e55dSMatthew Auld 5292c86e55dSMatthew Auld /* 5302c86e55dSMatthew Auld * Helper to counts the number of PTEs within the given length. This count 5312c86e55dSMatthew Auld * does not cross a page table boundary, so the max value would be 5322c86e55dSMatthew Auld * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 5332c86e55dSMatthew Auld */ 5342c86e55dSMatthew Auld static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 5352c86e55dSMatthew Auld { 5362c86e55dSMatthew Auld const u64 mask = ~((1ULL << pde_shift) - 1); 5372c86e55dSMatthew Auld u64 end; 5382c86e55dSMatthew Auld 5392c86e55dSMatthew Auld GEM_BUG_ON(length == 0); 5402c86e55dSMatthew Auld GEM_BUG_ON(offset_in_page(addr | length)); 5412c86e55dSMatthew Auld 5422c86e55dSMatthew Auld end = addr + length; 5432c86e55dSMatthew Auld 5442c86e55dSMatthew Auld if ((addr & mask) != (end & mask)) 5452c86e55dSMatthew Auld return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 5462c86e55dSMatthew Auld 5472c86e55dSMatthew Auld return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 5482c86e55dSMatthew Auld } 5492c86e55dSMatthew Auld 5502c86e55dSMatthew Auld static inline u32 i915_pde_index(u64 addr, u32 shift) 5512c86e55dSMatthew Auld { 5522c86e55dSMatthew Auld return (addr >> shift) & I915_PDE_MASK; 5532c86e55dSMatthew Auld } 5542c86e55dSMatthew Auld 5552c86e55dSMatthew Auld static inline struct i915_page_table * 5562c86e55dSMatthew Auld i915_pt_entry(const struct i915_page_directory * const pd, 5572c86e55dSMatthew Auld const unsigned short n) 5582c86e55dSMatthew Auld { 5592c86e55dSMatthew Auld return pd->entry[n]; 5602c86e55dSMatthew Auld } 5612c86e55dSMatthew Auld 5622c86e55dSMatthew Auld static inline struct i915_page_directory * 5632c86e55dSMatthew Auld i915_pd_entry(const struct i915_page_directory * const pdp, 5642c86e55dSMatthew Auld const unsigned short n) 5652c86e55dSMatthew Auld { 5662c86e55dSMatthew Auld return pdp->entry[n]; 5672c86e55dSMatthew Auld } 5682c86e55dSMatthew Auld 5692c86e55dSMatthew Auld static inline dma_addr_t 5702c86e55dSMatthew Auld i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n) 5712c86e55dSMatthew Auld { 57289351925SChris Wilson struct i915_page_table *pt = ppgtt->pd->entry[n]; 5732c86e55dSMatthew Auld 57489351925SChris Wilson return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]); 5752c86e55dSMatthew Auld } 5762c86e55dSMatthew Auld 577a259cc14SThomas Hellström void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt, 578a259cc14SThomas Hellström unsigned long lmem_pt_obj_flags); 5797a5c9223SCasey Bowman void intel_ggtt_bind_vma(struct i915_address_space *vm, 5807a5c9223SCasey Bowman struct i915_vm_pt_stash *stash, 5817a5c9223SCasey Bowman struct i915_vma_resource *vma_res, 5827a5c9223SCasey Bowman enum i915_cache_level cache_level, 5837a5c9223SCasey Bowman u32 flags); 5847a5c9223SCasey Bowman void intel_ggtt_unbind_vma(struct i915_address_space *vm, 5857a5c9223SCasey Bowman struct i915_vma_resource *vma_res); 5867a5c9223SCasey Bowman 5872c86e55dSMatthew Auld int i915_ggtt_probe_hw(struct drm_i915_private *i915); 5882c86e55dSMatthew Auld int i915_ggtt_init_hw(struct drm_i915_private *i915); 5892c86e55dSMatthew Auld int i915_ggtt_enable_hw(struct drm_i915_private *i915); 5902c86e55dSMatthew Auld int i915_init_ggtt(struct drm_i915_private *i915); 5912c86e55dSMatthew Auld void i915_ggtt_driver_release(struct drm_i915_private *i915); 5924d8151aeSThomas Hellström void i915_ggtt_driver_late_release(struct drm_i915_private *i915); 5930f857158SAravind Iddamsetty struct i915_ggtt *i915_ggtt_create(struct drm_i915_private *i915); 5942c86e55dSMatthew Auld 5952c86e55dSMatthew Auld static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt) 5962c86e55dSMatthew Auld { 5972c86e55dSMatthew Auld return ggtt->mappable_end > 0; 5982c86e55dSMatthew Auld } 5992c86e55dSMatthew Auld 6002c86e55dSMatthew Auld int i915_ppgtt_init_hw(struct intel_gt *gt); 6012c86e55dSMatthew Auld 602a259cc14SThomas Hellström struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt, 603a259cc14SThomas Hellström unsigned long lmem_pt_obj_flags); 6042c86e55dSMatthew Auld 6058d2f683fSImre Deak void i915_ggtt_suspend_vm(struct i915_address_space *vm); 6068d2f683fSImre Deak bool i915_ggtt_resume_vm(struct i915_address_space *vm); 607e986209cSChris Wilson void i915_ggtt_suspend(struct i915_ggtt *gtt); 608e986209cSChris Wilson void i915_ggtt_resume(struct i915_ggtt *ggtt); 6092c86e55dSMatthew Auld 6102c86e55dSMatthew Auld void 61189351925SChris Wilson fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count); 6122c86e55dSMatthew Auld 6132c86e55dSMatthew Auld #define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64)) 6142c86e55dSMatthew Auld #define fill32_px(px, v) do { \ 6152c86e55dSMatthew Auld u64 v__ = lower_32_bits(v); \ 6162c86e55dSMatthew Auld fill_px((px), v__ << 32 | v__); \ 6172c86e55dSMatthew Auld } while (0) 6182c86e55dSMatthew Auld 61989351925SChris Wilson int setup_scratch_page(struct i915_address_space *vm); 6202c86e55dSMatthew Auld void free_scratch(struct i915_address_space *vm); 6212c86e55dSMatthew Auld 62289351925SChris Wilson struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz); 6236aed5673SMatthew Auld struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz); 6242cff4b9eSMatthew Auld struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz); 6252c86e55dSMatthew Auld struct i915_page_directory *alloc_pd(struct i915_address_space *vm); 62682adf901SChris Wilson struct i915_page_directory *__alloc_pd(int npde); 6272c86e55dSMatthew Auld 628529b9ec8SMatthew Auld int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj); 629529b9ec8SMatthew Auld int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj); 6302c86e55dSMatthew Auld 63182adf901SChris Wilson void free_px(struct i915_address_space *vm, 63282adf901SChris Wilson struct i915_page_table *pt, int lvl); 63382adf901SChris Wilson #define free_pt(vm, px) free_px(vm, px, 0) 63482adf901SChris Wilson #define free_pd(vm, px) free_px(vm, px_pt(px), 1) 6352c86e55dSMatthew Auld 6362c86e55dSMatthew Auld void 6372c86e55dSMatthew Auld __set_pd_entry(struct i915_page_directory * const pd, 6382c86e55dSMatthew Auld const unsigned short idx, 63989351925SChris Wilson struct i915_page_table *pt, 6402c86e55dSMatthew Auld u64 (*encode)(const dma_addr_t, const enum i915_cache_level)); 6412c86e55dSMatthew Auld 6422c86e55dSMatthew Auld #define set_pd_entry(pd, idx, to) \ 64389351925SChris Wilson __set_pd_entry((pd), (idx), px_pt(to), gen8_pde_encode) 6442c86e55dSMatthew Auld 6452c86e55dSMatthew Auld void 6462c86e55dSMatthew Auld clear_pd_entry(struct i915_page_directory * const pd, 6472c86e55dSMatthew Auld const unsigned short idx, 64889351925SChris Wilson const struct drm_i915_gem_object * const scratch); 6492c86e55dSMatthew Auld 6502c86e55dSMatthew Auld bool 6512c86e55dSMatthew Auld release_pd_entry(struct i915_page_directory * const pd, 6522c86e55dSMatthew Auld const unsigned short idx, 6532c86e55dSMatthew Auld struct i915_page_table * const pt, 65489351925SChris Wilson const struct drm_i915_gem_object * const scratch); 6552c86e55dSMatthew Auld void gen6_ggtt_invalidate(struct i915_ggtt *ggtt); 6562c86e55dSMatthew Auld 657cd0452aaSChris Wilson void ppgtt_bind_vma(struct i915_address_space *vm, 658cd0452aaSChris Wilson struct i915_vm_pt_stash *stash, 65939a2bd34SThomas Hellström struct i915_vma_resource *vma_res, 66012b07256SChris Wilson enum i915_cache_level cache_level, 66112b07256SChris Wilson u32 flags); 66212b07256SChris Wilson void ppgtt_unbind_vma(struct i915_address_space *vm, 66339a2bd34SThomas Hellström struct i915_vma_resource *vma_res); 66412b07256SChris Wilson 6652c86e55dSMatthew Auld void gtt_write_workarounds(struct intel_gt *gt); 6662c86e55dSMatthew Auld 66777fa9efcSMatt Roper void setup_private_pat(struct intel_gt *gt); 6682c86e55dSMatthew Auld 669cd0452aaSChris Wilson int i915_vm_alloc_pt_stash(struct i915_address_space *vm, 670cd0452aaSChris Wilson struct i915_vm_pt_stash *stash, 671cd0452aaSChris Wilson u64 size); 672529b9ec8SMatthew Auld int i915_vm_map_pt_stash(struct i915_address_space *vm, 67389351925SChris Wilson struct i915_vm_pt_stash *stash); 674cd0452aaSChris Wilson void i915_vm_free_pt_stash(struct i915_address_space *vm, 675cd0452aaSChris Wilson struct i915_vm_pt_stash *stash); 676cd0452aaSChris Wilson 677a4d86249SChris Wilson struct i915_vma * 678a4d86249SChris Wilson __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size); 679a4d86249SChris Wilson 6802a665968SMaarten Lankhorst struct i915_vma * 6812a665968SMaarten Lankhorst __vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size); 6822a665968SMaarten Lankhorst 6832c86e55dSMatthew Auld static inline struct sgt_dma { 6842c86e55dSMatthew Auld struct scatterlist *sg; 6852c86e55dSMatthew Auld dma_addr_t dma, max; 68639a2bd34SThomas Hellström } sgt_dma(struct i915_vma_resource *vma_res) { 68739a2bd34SThomas Hellström struct scatterlist *sg = vma_res->bi.pages->sgl; 6882c86e55dSMatthew Auld dma_addr_t addr = sg_dma_address(sg); 6892c86e55dSMatthew Auld 6908a473dbaSTvrtko Ursulin return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) }; 6912c86e55dSMatthew Auld } 6922c86e55dSMatthew Auld 6932c86e55dSMatthew Auld #endif 694