12c86e55dSMatthew Auld /* SPDX-License-Identifier: MIT */ 22c86e55dSMatthew Auld /* 32c86e55dSMatthew Auld * Copyright © 2020 Intel Corporation 42c86e55dSMatthew Auld * 52c86e55dSMatthew Auld * Please try to maintain the following order within this file unless it makes 62c86e55dSMatthew Auld * sense to do otherwise. From top to bottom: 72c86e55dSMatthew Auld * 1. typedefs 82c86e55dSMatthew Auld * 2. #defines, and macros 92c86e55dSMatthew Auld * 3. structure definitions 102c86e55dSMatthew Auld * 4. function prototypes 112c86e55dSMatthew Auld * 122c86e55dSMatthew Auld * Within each section, please try to order by generation in ascending order, 132c86e55dSMatthew Auld * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 142c86e55dSMatthew Auld */ 152c86e55dSMatthew Auld 162c86e55dSMatthew Auld #ifndef __INTEL_GTT_H__ 172c86e55dSMatthew Auld #define __INTEL_GTT_H__ 182c86e55dSMatthew Auld 192c86e55dSMatthew Auld #include <linux/io-mapping.h> 202c86e55dSMatthew Auld #include <linux/kref.h> 212c86e55dSMatthew Auld #include <linux/mm.h> 222c86e55dSMatthew Auld #include <linux/pagevec.h> 232c86e55dSMatthew Auld #include <linux/scatterlist.h> 242c86e55dSMatthew Auld #include <linux/workqueue.h> 252c86e55dSMatthew Auld 262c86e55dSMatthew Auld #include <drm/drm_mm.h> 272c86e55dSMatthew Auld 282c86e55dSMatthew Auld #include "gt/intel_reset.h" 292c86e55dSMatthew Auld #include "i915_selftest.h" 302c86e55dSMatthew Auld #include "i915_vma_types.h" 312c86e55dSMatthew Auld 322c86e55dSMatthew Auld #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 332c86e55dSMatthew Auld 342c86e55dSMatthew Auld #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT) 352c86e55dSMatthew Auld #define DBG(...) trace_printk(__VA_ARGS__) 362c86e55dSMatthew Auld #else 372c86e55dSMatthew Auld #define DBG(...) 382c86e55dSMatthew Auld #endif 392c86e55dSMatthew Auld 402c86e55dSMatthew Auld #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */ 412c86e55dSMatthew Auld 422c86e55dSMatthew Auld #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12) 432c86e55dSMatthew Auld #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16) 442c86e55dSMatthew Auld #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21) 452c86e55dSMatthew Auld 462c86e55dSMatthew Auld #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 472c86e55dSMatthew Auld #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 482c86e55dSMatthew Auld 492c86e55dSMatthew Auld #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE 502c86e55dSMatthew Auld 512c86e55dSMatthew Auld #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 522c86e55dSMatthew Auld 532c86e55dSMatthew Auld #define I915_FENCE_REG_NONE -1 542c86e55dSMatthew Auld #define I915_MAX_NUM_FENCES 32 552c86e55dSMatthew Auld /* 32 fences + sign bit for FENCE_REG_NONE */ 562c86e55dSMatthew Auld #define I915_MAX_NUM_FENCE_BITS 6 572c86e55dSMatthew Auld 582c86e55dSMatthew Auld typedef u32 gen6_pte_t; 592c86e55dSMatthew Auld typedef u64 gen8_pte_t; 602c86e55dSMatthew Auld 612c86e55dSMatthew Auld #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT) 622c86e55dSMatthew Auld 632c86e55dSMatthew Auld #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len))) 642c86e55dSMatthew Auld #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 652c86e55dSMatthew Auld #define I915_PDES 512 662c86e55dSMatthew Auld #define I915_PDE_MASK (I915_PDES - 1) 672c86e55dSMatthew Auld 682c86e55dSMatthew Auld /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 692c86e55dSMatthew Auld #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 702c86e55dSMatthew Auld #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 712c86e55dSMatthew Auld #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 722c86e55dSMatthew Auld #define GEN6_PTE_CACHE_LLC (2 << 1) 732c86e55dSMatthew Auld #define GEN6_PTE_UNCACHED (1 << 1) 742c86e55dSMatthew Auld #define GEN6_PTE_VALID REG_BIT(0) 752c86e55dSMatthew Auld 762c86e55dSMatthew Auld #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 772c86e55dSMatthew Auld #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 782c86e55dSMatthew Auld #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 792c86e55dSMatthew Auld #define GEN6_PDE_SHIFT 22 802c86e55dSMatthew Auld #define GEN6_PDE_VALID REG_BIT(0) 812c86e55dSMatthew Auld #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 822c86e55dSMatthew Auld 832c86e55dSMatthew Auld #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 842c86e55dSMatthew Auld 852c86e55dSMatthew Auld #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2) 862c86e55dSMatthew Auld #define BYT_PTE_WRITEABLE REG_BIT(1) 872c86e55dSMatthew Auld 8811724eeaSMatthew Auld #define GEN12_PPGTT_PTE_LM BIT_ULL(11) 89e762bdf5SMatthew Auld 90e762bdf5SMatthew Auld #define GEN12_GGTT_PTE_LM BIT_ULL(1) 9111724eeaSMatthew Auld 922c86e55dSMatthew Auld /* 932c86e55dSMatthew Auld * Cacheability Control is a 4-bit value. The low three bits are stored in bits 942c86e55dSMatthew Auld * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 952c86e55dSMatthew Auld */ 962c86e55dSMatthew Auld #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 972c86e55dSMatthew Auld (((bits) & 0x8) << (11 - 3))) 982c86e55dSMatthew Auld #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 992c86e55dSMatthew Auld #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 1002c86e55dSMatthew Auld #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 1012c86e55dSMatthew Auld #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 1022c86e55dSMatthew Auld #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 1032c86e55dSMatthew Auld #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 1042c86e55dSMatthew Auld #define HSW_PTE_UNCACHED (0) 1052c86e55dSMatthew Auld #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 1062c86e55dSMatthew Auld #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 1072c86e55dSMatthew Auld 1082c86e55dSMatthew Auld /* 1092c86e55dSMatthew Auld * GEN8 32b style address is defined as a 3 level page table: 1102c86e55dSMatthew Auld * 31:30 | 29:21 | 20:12 | 11:0 1112c86e55dSMatthew Auld * PDPE | PDE | PTE | offset 1122c86e55dSMatthew Auld * The difference as compared to normal x86 3 level page table is the PDPEs are 1132c86e55dSMatthew Auld * programmed via register. 1142c86e55dSMatthew Auld * 1152c86e55dSMatthew Auld * GEN8 48b style address is defined as a 4 level page table: 1162c86e55dSMatthew Auld * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 1172c86e55dSMatthew Auld * PML4E | PDPE | PDE | PTE | offset 1182c86e55dSMatthew Auld */ 1192c86e55dSMatthew Auld #define GEN8_3LVL_PDPES 4 1202c86e55dSMatthew Auld 1212c86e55dSMatthew Auld #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD) 1222c86e55dSMatthew Auld #define PPAT_CACHED_PDE 0 /* WB LLC */ 1232c86e55dSMatthew Auld #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */ 1242c86e55dSMatthew Auld #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */ 1252c86e55dSMatthew Auld 1262c86e55dSMatthew Auld #define CHV_PPAT_SNOOP REG_BIT(6) 1272c86e55dSMatthew Auld #define GEN8_PPAT_AGE(x) ((x)<<4) 1282c86e55dSMatthew Auld #define GEN8_PPAT_LLCeLLC (3<<2) 1292c86e55dSMatthew Auld #define GEN8_PPAT_LLCELLC (2<<2) 1302c86e55dSMatthew Auld #define GEN8_PPAT_LLC (1<<2) 1312c86e55dSMatthew Auld #define GEN8_PPAT_WB (3<<0) 1322c86e55dSMatthew Auld #define GEN8_PPAT_WT (2<<0) 1332c86e55dSMatthew Auld #define GEN8_PPAT_WC (1<<0) 1342c86e55dSMatthew Auld #define GEN8_PPAT_UC (0<<0) 1352c86e55dSMatthew Auld #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 1362c86e55dSMatthew Auld #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) 1372c86e55dSMatthew Auld 1382c86e55dSMatthew Auld #define GEN8_PDE_IPS_64K BIT(11) 1392c86e55dSMatthew Auld #define GEN8_PDE_PS_2M BIT(7) 1402c86e55dSMatthew Auld 14189351925SChris Wilson enum i915_cache_level; 14289351925SChris Wilson 14389351925SChris Wilson struct drm_i915_file_private; 14489351925SChris Wilson struct drm_i915_gem_object; 1450b6bc81dSChris Wilson struct i915_fence_reg; 14689351925SChris Wilson struct i915_vma; 14789351925SChris Wilson struct intel_gt; 1480b6bc81dSChris Wilson 1492c86e55dSMatthew Auld #define for_each_sgt_daddr(__dp, __iter, __sgt) \ 1502c86e55dSMatthew Auld __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE) 1512c86e55dSMatthew Auld 1522c86e55dSMatthew Auld struct i915_page_table { 15389351925SChris Wilson struct drm_i915_gem_object *base; 154cd0452aaSChris Wilson union { 1552c86e55dSMatthew Auld atomic_t used; 156cd0452aaSChris Wilson struct i915_page_table *stash; 157cd0452aaSChris Wilson }; 1582c86e55dSMatthew Auld }; 1592c86e55dSMatthew Auld 1602c86e55dSMatthew Auld struct i915_page_directory { 1612c86e55dSMatthew Auld struct i915_page_table pt; 1622c86e55dSMatthew Auld spinlock_t lock; 16382adf901SChris Wilson void **entry; 1642c86e55dSMatthew Auld }; 1652c86e55dSMatthew Auld 1662c86e55dSMatthew Auld #define __px_choose_expr(x, type, expr, other) \ 1672c86e55dSMatthew Auld __builtin_choose_expr( \ 1682c86e55dSMatthew Auld __builtin_types_compatible_p(typeof(x), type) || \ 1692c86e55dSMatthew Auld __builtin_types_compatible_p(typeof(x), const type), \ 1702c86e55dSMatthew Auld ({ type __x = (type)(x); expr; }), \ 1712c86e55dSMatthew Auld other) 1722c86e55dSMatthew Auld 1732c86e55dSMatthew Auld #define px_base(px) \ 17489351925SChris Wilson __px_choose_expr(px, struct drm_i915_gem_object *, __x, \ 17589351925SChris Wilson __px_choose_expr(px, struct i915_page_table *, __x->base, \ 17689351925SChris Wilson __px_choose_expr(px, struct i915_page_directory *, __x->pt.base, \ 17789351925SChris Wilson (void)0))) 17889351925SChris Wilson 17989351925SChris Wilson struct page *__px_page(struct drm_i915_gem_object *p); 18089351925SChris Wilson dma_addr_t __px_dma(struct drm_i915_gem_object *p); 18189351925SChris Wilson #define px_dma(px) (__px_dma(px_base(px))) 1822c86e55dSMatthew Auld 1832c86e55dSMatthew Auld #define px_pt(px) \ 1842c86e55dSMatthew Auld __px_choose_expr(px, struct i915_page_table *, __x, \ 1852c86e55dSMatthew Auld __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \ 1862c86e55dSMatthew Auld (void)0)) 1872c86e55dSMatthew Auld #define px_used(px) (&px_pt(px)->used) 1882c86e55dSMatthew Auld 189cd0452aaSChris Wilson struct i915_vm_pt_stash { 190cd0452aaSChris Wilson /* preallocated chains of page tables/directories */ 191cd0452aaSChris Wilson struct i915_page_table *pt[2]; 192cd0452aaSChris Wilson }; 193cd0452aaSChris Wilson 1942c86e55dSMatthew Auld struct i915_vma_ops { 1952c86e55dSMatthew Auld /* Map an object into an address space with the given cache flags. */ 196cd0452aaSChris Wilson void (*bind_vma)(struct i915_address_space *vm, 197cd0452aaSChris Wilson struct i915_vm_pt_stash *stash, 19812b07256SChris Wilson struct i915_vma *vma, 1992c86e55dSMatthew Auld enum i915_cache_level cache_level, 2002c86e55dSMatthew Auld u32 flags); 2012c86e55dSMatthew Auld /* 2022c86e55dSMatthew Auld * Unmap an object from an address space. This usually consists of 2032c86e55dSMatthew Auld * setting the valid PTE entries to a reserved scratch page. 2042c86e55dSMatthew Auld */ 20512b07256SChris Wilson void (*unbind_vma)(struct i915_address_space *vm, 20612b07256SChris Wilson struct i915_vma *vma); 2072c86e55dSMatthew Auld 2082c86e55dSMatthew Auld int (*set_pages)(struct i915_vma *vma); 2092c86e55dSMatthew Auld void (*clear_pages)(struct i915_vma *vma); 2102c86e55dSMatthew Auld }; 2112c86e55dSMatthew Auld 2122c86e55dSMatthew Auld struct i915_address_space { 2132c86e55dSMatthew Auld struct kref ref; 2142c86e55dSMatthew Auld struct rcu_work rcu; 2152c86e55dSMatthew Auld 2162c86e55dSMatthew Auld struct drm_mm mm; 2172c86e55dSMatthew Auld struct intel_gt *gt; 2182c86e55dSMatthew Auld struct drm_i915_private *i915; 2192c86e55dSMatthew Auld struct device *dma; 2202c86e55dSMatthew Auld /* 2212c86e55dSMatthew Auld * Every address space belongs to a struct file - except for the global 2222c86e55dSMatthew Auld * GTT that is owned by the driver (and so @file is set to NULL). In 2232c86e55dSMatthew Auld * principle, no information should leak from one context to another 2242c86e55dSMatthew Auld * (or between files/processes etc) unless explicitly shared by the 2252c86e55dSMatthew Auld * owner. Tracking the owner is important in order to free up per-file 2262c86e55dSMatthew Auld * objects along with the file, to aide resource tracking, and to 2272c86e55dSMatthew Auld * assign blame. 2282c86e55dSMatthew Auld */ 2292c86e55dSMatthew Auld struct drm_i915_file_private *file; 2302c86e55dSMatthew Auld u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 2312c86e55dSMatthew Auld u64 reserved; /* size addr space reserved */ 2322c86e55dSMatthew Auld 2332c86e55dSMatthew Auld unsigned int bind_async_flags; 2342c86e55dSMatthew Auld 2352c86e55dSMatthew Auld /* 2362c86e55dSMatthew Auld * Each active user context has its own address space (in full-ppgtt). 2372c86e55dSMatthew Auld * Since the vm may be shared between multiple contexts, we count how 2382c86e55dSMatthew Auld * many contexts keep us "open". Once open hits zero, we are closed 2392c86e55dSMatthew Auld * and do not allow any new attachments, and proceed to shutdown our 2402c86e55dSMatthew Auld * vma and page directories. 2412c86e55dSMatthew Auld */ 2422c86e55dSMatthew Auld atomic_t open; 2432c86e55dSMatthew Auld 2442c86e55dSMatthew Auld struct mutex mutex; /* protects vma and our lists */ 24526ad4f8bSMaarten Lankhorst struct dma_resv resv; /* reservation lock for all pd objects, and buffer pool */ 2462c86e55dSMatthew Auld #define VM_CLASS_GGTT 0 2472c86e55dSMatthew Auld #define VM_CLASS_PPGTT 1 248*33e7a975SVille Syrjälä #define VM_CLASS_DPT 2 2492c86e55dSMatthew Auld 25089351925SChris Wilson struct drm_i915_gem_object *scratch[4]; 2512c86e55dSMatthew Auld /** 2522c86e55dSMatthew Auld * List of vma currently bound. 2532c86e55dSMatthew Auld */ 2542c86e55dSMatthew Auld struct list_head bound_list; 2552c86e55dSMatthew Auld 2562c86e55dSMatthew Auld /* Global GTT */ 2572c86e55dSMatthew Auld bool is_ggtt:1; 2582c86e55dSMatthew Auld 259*33e7a975SVille Syrjälä /* Display page table */ 260*33e7a975SVille Syrjälä bool is_dpt:1; 261*33e7a975SVille Syrjälä 2622c86e55dSMatthew Auld /* Some systems support read-only mappings for GGTT and/or PPGTT */ 2632c86e55dSMatthew Auld bool has_read_only:1; 2642c86e55dSMatthew Auld 265cd0452aaSChris Wilson u8 top; 266cd0452aaSChris Wilson u8 pd_shift; 267cd0452aaSChris Wilson u8 scratch_order; 268cd0452aaSChris Wilson 26989351925SChris Wilson struct drm_i915_gem_object * 27089351925SChris Wilson (*alloc_pt_dma)(struct i915_address_space *vm, int sz); 27189351925SChris Wilson 2722c86e55dSMatthew Auld u64 (*pte_encode)(dma_addr_t addr, 2732c86e55dSMatthew Auld enum i915_cache_level level, 2742c86e55dSMatthew Auld u32 flags); /* Create a valid PTE */ 2752c86e55dSMatthew Auld #define PTE_READ_ONLY BIT(0) 27611724eeaSMatthew Auld #define PTE_LM BIT(1) 2772c86e55dSMatthew Auld 278cd0452aaSChris Wilson void (*allocate_va_range)(struct i915_address_space *vm, 279cd0452aaSChris Wilson struct i915_vm_pt_stash *stash, 2802c86e55dSMatthew Auld u64 start, u64 length); 2812c86e55dSMatthew Auld void (*clear_range)(struct i915_address_space *vm, 2822c86e55dSMatthew Auld u64 start, u64 length); 2832c86e55dSMatthew Auld void (*insert_page)(struct i915_address_space *vm, 2842c86e55dSMatthew Auld dma_addr_t addr, 2852c86e55dSMatthew Auld u64 offset, 2862c86e55dSMatthew Auld enum i915_cache_level cache_level, 2872c86e55dSMatthew Auld u32 flags); 2882c86e55dSMatthew Auld void (*insert_entries)(struct i915_address_space *vm, 2892c86e55dSMatthew Auld struct i915_vma *vma, 2902c86e55dSMatthew Auld enum i915_cache_level cache_level, 2912c86e55dSMatthew Auld u32 flags); 2922c86e55dSMatthew Auld void (*cleanup)(struct i915_address_space *vm); 2932c86e55dSMatthew Auld 2942c86e55dSMatthew Auld struct i915_vma_ops vma_ops; 2952c86e55dSMatthew Auld 2962c86e55dSMatthew Auld I915_SELFTEST_DECLARE(struct fault_attr fault_attr); 2972c86e55dSMatthew Auld I915_SELFTEST_DECLARE(bool scrub_64K); 2982c86e55dSMatthew Auld }; 2992c86e55dSMatthew Auld 3002c86e55dSMatthew Auld /* 3012c86e55dSMatthew Auld * The Graphics Translation Table is the way in which GEN hardware translates a 3022c86e55dSMatthew Auld * Graphics Virtual Address into a Physical Address. In addition to the normal 3032c86e55dSMatthew Auld * collateral associated with any va->pa translations GEN hardware also has a 3042c86e55dSMatthew Auld * portion of the GTT which can be mapped by the CPU and remain both coherent 3052c86e55dSMatthew Auld * and correct (in cases like swizzling). That region is referred to as GMADR in 3062c86e55dSMatthew Auld * the spec. 3072c86e55dSMatthew Auld */ 3082c86e55dSMatthew Auld struct i915_ggtt { 3092c86e55dSMatthew Auld struct i915_address_space vm; 3102c86e55dSMatthew Auld 3112c86e55dSMatthew Auld struct io_mapping iomap; /* Mapping to our CPU mappable region */ 3122c86e55dSMatthew Auld struct resource gmadr; /* GMADR resource */ 3132c86e55dSMatthew Auld resource_size_t mappable_end; /* End offset that we can CPU map */ 3142c86e55dSMatthew Auld 3152c86e55dSMatthew Auld /** "Graphics Stolen Memory" holds the global PTEs */ 3162c86e55dSMatthew Auld void __iomem *gsm; 3172c86e55dSMatthew Auld void (*invalidate)(struct i915_ggtt *ggtt); 3182c86e55dSMatthew Auld 3192c86e55dSMatthew Auld /** PPGTT used for aliasing the PPGTT with the GTT */ 3202c86e55dSMatthew Auld struct i915_ppgtt *alias; 3212c86e55dSMatthew Auld 3222c86e55dSMatthew Auld bool do_idle_maps; 3232c86e55dSMatthew Auld 3242c86e55dSMatthew Auld int mtrr; 3252c86e55dSMatthew Auld 3262c86e55dSMatthew Auld /** Bit 6 swizzling required for X tiling */ 3272c86e55dSMatthew Auld u32 bit_6_swizzle_x; 3282c86e55dSMatthew Auld /** Bit 6 swizzling required for Y tiling */ 3292c86e55dSMatthew Auld u32 bit_6_swizzle_y; 3302c86e55dSMatthew Auld 3312c86e55dSMatthew Auld u32 pin_bias; 3322c86e55dSMatthew Auld 3332c86e55dSMatthew Auld unsigned int num_fences; 3340b6bc81dSChris Wilson struct i915_fence_reg *fence_regs; 3352c86e55dSMatthew Auld struct list_head fence_list; 3362c86e55dSMatthew Auld 3372c86e55dSMatthew Auld /** 3382c86e55dSMatthew Auld * List of all objects in gtt_space, currently mmaped by userspace. 3392c86e55dSMatthew Auld * All objects within this list must also be on bound_list. 3402c86e55dSMatthew Auld */ 3412c86e55dSMatthew Auld struct list_head userfault_list; 3422c86e55dSMatthew Auld 3432c86e55dSMatthew Auld /* Manual runtime pm autosuspend delay for user GGTT mmaps */ 3442c86e55dSMatthew Auld struct intel_wakeref_auto userfault_wakeref; 3452c86e55dSMatthew Auld 346742379c0SChris Wilson struct mutex error_mutex; 3472c86e55dSMatthew Auld struct drm_mm_node error_capture; 3482c86e55dSMatthew Auld struct drm_mm_node uc_fw; 3492c86e55dSMatthew Auld }; 3502c86e55dSMatthew Auld 3512c86e55dSMatthew Auld struct i915_ppgtt { 3522c86e55dSMatthew Auld struct i915_address_space vm; 3532c86e55dSMatthew Auld 3542c86e55dSMatthew Auld struct i915_page_directory *pd; 3552c86e55dSMatthew Auld }; 3562c86e55dSMatthew Auld 3572c86e55dSMatthew Auld #define i915_is_ggtt(vm) ((vm)->is_ggtt) 358*33e7a975SVille Syrjälä #define i915_is_dpt(vm) ((vm)->is_dpt) 3592c86e55dSMatthew Auld 36026ad4f8bSMaarten Lankhorst int __must_check 36126ad4f8bSMaarten Lankhorst i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww); 36226ad4f8bSMaarten Lankhorst 3632c86e55dSMatthew Auld static inline bool 3642c86e55dSMatthew Auld i915_vm_is_4lvl(const struct i915_address_space *vm) 3652c86e55dSMatthew Auld { 3662c86e55dSMatthew Auld return (vm->total - 1) >> 32; 3672c86e55dSMatthew Auld } 3682c86e55dSMatthew Auld 3692c86e55dSMatthew Auld static inline bool 3702c86e55dSMatthew Auld i915_vm_has_scratch_64K(struct i915_address_space *vm) 3712c86e55dSMatthew Auld { 3722c86e55dSMatthew Auld return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K); 3732c86e55dSMatthew Auld } 3742c86e55dSMatthew Auld 3752c86e55dSMatthew Auld static inline bool 3762c86e55dSMatthew Auld i915_vm_has_cache_coloring(struct i915_address_space *vm) 3772c86e55dSMatthew Auld { 3782c86e55dSMatthew Auld return i915_is_ggtt(vm) && vm->mm.color_adjust; 3792c86e55dSMatthew Auld } 3802c86e55dSMatthew Auld 3812c86e55dSMatthew Auld static inline struct i915_ggtt * 3822c86e55dSMatthew Auld i915_vm_to_ggtt(struct i915_address_space *vm) 3832c86e55dSMatthew Auld { 3842c86e55dSMatthew Auld BUILD_BUG_ON(offsetof(struct i915_ggtt, vm)); 3852c86e55dSMatthew Auld GEM_BUG_ON(!i915_is_ggtt(vm)); 3862c86e55dSMatthew Auld return container_of(vm, struct i915_ggtt, vm); 3872c86e55dSMatthew Auld } 3882c86e55dSMatthew Auld 3892c86e55dSMatthew Auld static inline struct i915_ppgtt * 3902c86e55dSMatthew Auld i915_vm_to_ppgtt(struct i915_address_space *vm) 3912c86e55dSMatthew Auld { 3922c86e55dSMatthew Auld BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm)); 3932c86e55dSMatthew Auld GEM_BUG_ON(i915_is_ggtt(vm)); 3942c86e55dSMatthew Auld return container_of(vm, struct i915_ppgtt, vm); 3952c86e55dSMatthew Auld } 3962c86e55dSMatthew Auld 3972c86e55dSMatthew Auld static inline struct i915_address_space * 3982c86e55dSMatthew Auld i915_vm_get(struct i915_address_space *vm) 3992c86e55dSMatthew Auld { 4002c86e55dSMatthew Auld kref_get(&vm->ref); 4012c86e55dSMatthew Auld return vm; 4022c86e55dSMatthew Auld } 4032c86e55dSMatthew Auld 4042c86e55dSMatthew Auld void i915_vm_release(struct kref *kref); 4052c86e55dSMatthew Auld 4062c86e55dSMatthew Auld static inline void i915_vm_put(struct i915_address_space *vm) 4072c86e55dSMatthew Auld { 4082c86e55dSMatthew Auld kref_put(&vm->ref, i915_vm_release); 4092c86e55dSMatthew Auld } 4102c86e55dSMatthew Auld 4112c86e55dSMatthew Auld static inline struct i915_address_space * 4122c86e55dSMatthew Auld i915_vm_open(struct i915_address_space *vm) 4132c86e55dSMatthew Auld { 4142c86e55dSMatthew Auld GEM_BUG_ON(!atomic_read(&vm->open)); 4152c86e55dSMatthew Auld atomic_inc(&vm->open); 4162c86e55dSMatthew Auld return i915_vm_get(vm); 4172c86e55dSMatthew Auld } 4182c86e55dSMatthew Auld 4192c86e55dSMatthew Auld static inline bool 4202c86e55dSMatthew Auld i915_vm_tryopen(struct i915_address_space *vm) 4212c86e55dSMatthew Auld { 4222c86e55dSMatthew Auld if (atomic_add_unless(&vm->open, 1, 0)) 4232c86e55dSMatthew Auld return i915_vm_get(vm); 4242c86e55dSMatthew Auld 4252c86e55dSMatthew Auld return false; 4262c86e55dSMatthew Auld } 4272c86e55dSMatthew Auld 4282c86e55dSMatthew Auld void __i915_vm_close(struct i915_address_space *vm); 4292c86e55dSMatthew Auld 4302c86e55dSMatthew Auld static inline void 4312c86e55dSMatthew Auld i915_vm_close(struct i915_address_space *vm) 4322c86e55dSMatthew Auld { 4332c86e55dSMatthew Auld GEM_BUG_ON(!atomic_read(&vm->open)); 4342c86e55dSMatthew Auld __i915_vm_close(vm); 4352c86e55dSMatthew Auld 4362c86e55dSMatthew Auld i915_vm_put(vm); 4372c86e55dSMatthew Auld } 4382c86e55dSMatthew Auld 4392c86e55dSMatthew Auld void i915_address_space_init(struct i915_address_space *vm, int subclass); 4402c86e55dSMatthew Auld void i915_address_space_fini(struct i915_address_space *vm); 4412c86e55dSMatthew Auld 4422c86e55dSMatthew Auld static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) 4432c86e55dSMatthew Auld { 4442c86e55dSMatthew Auld const u32 mask = NUM_PTE(pde_shift) - 1; 4452c86e55dSMatthew Auld 4462c86e55dSMatthew Auld return (address >> PAGE_SHIFT) & mask; 4472c86e55dSMatthew Auld } 4482c86e55dSMatthew Auld 4492c86e55dSMatthew Auld /* 4502c86e55dSMatthew Auld * Helper to counts the number of PTEs within the given length. This count 4512c86e55dSMatthew Auld * does not cross a page table boundary, so the max value would be 4522c86e55dSMatthew Auld * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 4532c86e55dSMatthew Auld */ 4542c86e55dSMatthew Auld static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift) 4552c86e55dSMatthew Auld { 4562c86e55dSMatthew Auld const u64 mask = ~((1ULL << pde_shift) - 1); 4572c86e55dSMatthew Auld u64 end; 4582c86e55dSMatthew Auld 4592c86e55dSMatthew Auld GEM_BUG_ON(length == 0); 4602c86e55dSMatthew Auld GEM_BUG_ON(offset_in_page(addr | length)); 4612c86e55dSMatthew Auld 4622c86e55dSMatthew Auld end = addr + length; 4632c86e55dSMatthew Auld 4642c86e55dSMatthew Auld if ((addr & mask) != (end & mask)) 4652c86e55dSMatthew Auld return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 4662c86e55dSMatthew Auld 4672c86e55dSMatthew Auld return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 4682c86e55dSMatthew Auld } 4692c86e55dSMatthew Auld 4702c86e55dSMatthew Auld static inline u32 i915_pde_index(u64 addr, u32 shift) 4712c86e55dSMatthew Auld { 4722c86e55dSMatthew Auld return (addr >> shift) & I915_PDE_MASK; 4732c86e55dSMatthew Auld } 4742c86e55dSMatthew Auld 4752c86e55dSMatthew Auld static inline struct i915_page_table * 4762c86e55dSMatthew Auld i915_pt_entry(const struct i915_page_directory * const pd, 4772c86e55dSMatthew Auld const unsigned short n) 4782c86e55dSMatthew Auld { 4792c86e55dSMatthew Auld return pd->entry[n]; 4802c86e55dSMatthew Auld } 4812c86e55dSMatthew Auld 4822c86e55dSMatthew Auld static inline struct i915_page_directory * 4832c86e55dSMatthew Auld i915_pd_entry(const struct i915_page_directory * const pdp, 4842c86e55dSMatthew Auld const unsigned short n) 4852c86e55dSMatthew Auld { 4862c86e55dSMatthew Auld return pdp->entry[n]; 4872c86e55dSMatthew Auld } 4882c86e55dSMatthew Auld 4892c86e55dSMatthew Auld static inline dma_addr_t 4902c86e55dSMatthew Auld i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n) 4912c86e55dSMatthew Auld { 49289351925SChris Wilson struct i915_page_table *pt = ppgtt->pd->entry[n]; 4932c86e55dSMatthew Auld 49489351925SChris Wilson return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]); 4952c86e55dSMatthew Auld } 4962c86e55dSMatthew Auld 4972c86e55dSMatthew Auld void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt); 4982c86e55dSMatthew Auld 4992c86e55dSMatthew Auld int i915_ggtt_probe_hw(struct drm_i915_private *i915); 5002c86e55dSMatthew Auld int i915_ggtt_init_hw(struct drm_i915_private *i915); 5012c86e55dSMatthew Auld int i915_ggtt_enable_hw(struct drm_i915_private *i915); 5022c86e55dSMatthew Auld void i915_ggtt_enable_guc(struct i915_ggtt *ggtt); 5032c86e55dSMatthew Auld void i915_ggtt_disable_guc(struct i915_ggtt *ggtt); 5042c86e55dSMatthew Auld int i915_init_ggtt(struct drm_i915_private *i915); 5052c86e55dSMatthew Auld void i915_ggtt_driver_release(struct drm_i915_private *i915); 5062c86e55dSMatthew Auld 5072c86e55dSMatthew Auld static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt) 5082c86e55dSMatthew Auld { 5092c86e55dSMatthew Auld return ggtt->mappable_end > 0; 5102c86e55dSMatthew Auld } 5112c86e55dSMatthew Auld 5122c86e55dSMatthew Auld int i915_ppgtt_init_hw(struct intel_gt *gt); 5132c86e55dSMatthew Auld 5142c86e55dSMatthew Auld struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt); 5152c86e55dSMatthew Auld 516e986209cSChris Wilson void i915_ggtt_suspend(struct i915_ggtt *gtt); 517e986209cSChris Wilson void i915_ggtt_resume(struct i915_ggtt *ggtt); 5182c86e55dSMatthew Auld 51989351925SChris Wilson #define kmap_atomic_px(px) kmap_atomic(__px_page(px_base(px))) 5202c86e55dSMatthew Auld 5212c86e55dSMatthew Auld void 52289351925SChris Wilson fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count); 5232c86e55dSMatthew Auld 5242c86e55dSMatthew Auld #define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64)) 5252c86e55dSMatthew Auld #define fill32_px(px, v) do { \ 5262c86e55dSMatthew Auld u64 v__ = lower_32_bits(v); \ 5272c86e55dSMatthew Auld fill_px((px), v__ << 32 | v__); \ 5282c86e55dSMatthew Auld } while (0) 5292c86e55dSMatthew Auld 53089351925SChris Wilson int setup_scratch_page(struct i915_address_space *vm); 5312c86e55dSMatthew Auld void free_scratch(struct i915_address_space *vm); 5322c86e55dSMatthew Auld 53389351925SChris Wilson struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz); 5342c86e55dSMatthew Auld struct i915_page_table *alloc_pt(struct i915_address_space *vm); 5352c86e55dSMatthew Auld struct i915_page_directory *alloc_pd(struct i915_address_space *vm); 53682adf901SChris Wilson struct i915_page_directory *__alloc_pd(int npde); 5372c86e55dSMatthew Auld 53889351925SChris Wilson int pin_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj); 53926ad4f8bSMaarten Lankhorst int pin_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj); 5402c86e55dSMatthew Auld 54182adf901SChris Wilson void free_px(struct i915_address_space *vm, 54282adf901SChris Wilson struct i915_page_table *pt, int lvl); 54382adf901SChris Wilson #define free_pt(vm, px) free_px(vm, px, 0) 54482adf901SChris Wilson #define free_pd(vm, px) free_px(vm, px_pt(px), 1) 5452c86e55dSMatthew Auld 5462c86e55dSMatthew Auld void 5472c86e55dSMatthew Auld __set_pd_entry(struct i915_page_directory * const pd, 5482c86e55dSMatthew Auld const unsigned short idx, 54989351925SChris Wilson struct i915_page_table *pt, 5502c86e55dSMatthew Auld u64 (*encode)(const dma_addr_t, const enum i915_cache_level)); 5512c86e55dSMatthew Auld 5522c86e55dSMatthew Auld #define set_pd_entry(pd, idx, to) \ 55389351925SChris Wilson __set_pd_entry((pd), (idx), px_pt(to), gen8_pde_encode) 5542c86e55dSMatthew Auld 5552c86e55dSMatthew Auld void 5562c86e55dSMatthew Auld clear_pd_entry(struct i915_page_directory * const pd, 5572c86e55dSMatthew Auld const unsigned short idx, 55889351925SChris Wilson const struct drm_i915_gem_object * const scratch); 5592c86e55dSMatthew Auld 5602c86e55dSMatthew Auld bool 5612c86e55dSMatthew Auld release_pd_entry(struct i915_page_directory * const pd, 5622c86e55dSMatthew Auld const unsigned short idx, 5632c86e55dSMatthew Auld struct i915_page_table * const pt, 56489351925SChris Wilson const struct drm_i915_gem_object * const scratch); 5652c86e55dSMatthew Auld void gen6_ggtt_invalidate(struct i915_ggtt *ggtt); 5662c86e55dSMatthew Auld 5672c86e55dSMatthew Auld int ggtt_set_pages(struct i915_vma *vma); 5682c86e55dSMatthew Auld int ppgtt_set_pages(struct i915_vma *vma); 5692c86e55dSMatthew Auld void clear_pages(struct i915_vma *vma); 5702c86e55dSMatthew Auld 571cd0452aaSChris Wilson void ppgtt_bind_vma(struct i915_address_space *vm, 572cd0452aaSChris Wilson struct i915_vm_pt_stash *stash, 57312b07256SChris Wilson struct i915_vma *vma, 57412b07256SChris Wilson enum i915_cache_level cache_level, 57512b07256SChris Wilson u32 flags); 57612b07256SChris Wilson void ppgtt_unbind_vma(struct i915_address_space *vm, 57712b07256SChris Wilson struct i915_vma *vma); 57812b07256SChris Wilson 5792c86e55dSMatthew Auld void gtt_write_workarounds(struct intel_gt *gt); 5802c86e55dSMatthew Auld 5812c86e55dSMatthew Auld void setup_private_pat(struct intel_uncore *uncore); 5822c86e55dSMatthew Auld 583cd0452aaSChris Wilson int i915_vm_alloc_pt_stash(struct i915_address_space *vm, 584cd0452aaSChris Wilson struct i915_vm_pt_stash *stash, 585cd0452aaSChris Wilson u64 size); 58689351925SChris Wilson int i915_vm_pin_pt_stash(struct i915_address_space *vm, 58789351925SChris Wilson struct i915_vm_pt_stash *stash); 588cd0452aaSChris Wilson void i915_vm_free_pt_stash(struct i915_address_space *vm, 589cd0452aaSChris Wilson struct i915_vm_pt_stash *stash); 590cd0452aaSChris Wilson 591a4d86249SChris Wilson struct i915_vma * 592a4d86249SChris Wilson __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size); 593a4d86249SChris Wilson 5942a665968SMaarten Lankhorst struct i915_vma * 5952a665968SMaarten Lankhorst __vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size); 5962a665968SMaarten Lankhorst 5972c86e55dSMatthew Auld static inline struct sgt_dma { 5982c86e55dSMatthew Auld struct scatterlist *sg; 5992c86e55dSMatthew Auld dma_addr_t dma, max; 6002c86e55dSMatthew Auld } sgt_dma(struct i915_vma *vma) { 6012c86e55dSMatthew Auld struct scatterlist *sg = vma->pages->sgl; 6022c86e55dSMatthew Auld dma_addr_t addr = sg_dma_address(sg); 6032c86e55dSMatthew Auld 6048a473dbaSTvrtko Ursulin return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) }; 6052c86e55dSMatthew Auld } 6062c86e55dSMatthew Auld 6072c86e55dSMatthew Auld #endif 608