1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_GT_TYPES__ 7 #define __INTEL_GT_TYPES__ 8 9 #include <linux/ktime.h> 10 #include <linux/list.h> 11 #include <linux/llist.h> 12 #include <linux/mutex.h> 13 #include <linux/notifier.h> 14 #include <linux/seqlock.h> 15 #include <linux/spinlock.h> 16 #include <linux/types.h> 17 #include <linux/workqueue.h> 18 19 #include "uc/intel_uc.h" 20 #include "intel_gsc.h" 21 22 #include "i915_vma.h" 23 #include "intel_engine_types.h" 24 #include "intel_gt_buffer_pool_types.h" 25 #include "intel_hwconfig.h" 26 #include "intel_llc_types.h" 27 #include "intel_reset_types.h" 28 #include "intel_rc6_types.h" 29 #include "intel_rps_types.h" 30 #include "intel_migrate_types.h" 31 #include "intel_wakeref.h" 32 #include "pxp/intel_pxp_types.h" 33 34 struct drm_i915_private; 35 struct i915_ggtt; 36 struct intel_engine_cs; 37 struct intel_uncore; 38 39 struct intel_mmio_range { 40 u32 start; 41 u32 end; 42 }; 43 44 /* 45 * The hardware has multiple kinds of multicast register ranges that need 46 * special register steering (and future platforms are expected to add 47 * additional types). 48 * 49 * During driver startup, we initialize the steering control register to 50 * direct reads to a slice/subslice that are valid for the 'subslice' class 51 * of multicast registers. If another type of steering does not have any 52 * overlap in valid steering targets with 'subslice' style registers, we will 53 * need to explicitly re-steer reads of registers of the other type. 54 * 55 * Only the replication types that may need additional non-default steering 56 * are listed here. 57 */ 58 enum intel_steering_type { 59 L3BANK, 60 MSLICE, 61 LNCF, 62 63 /* 64 * On some platforms there are multiple types of MCR registers that 65 * will always return a non-terminated value at instance (0, 0). We'll 66 * lump those all into a single category to keep things simple. 67 */ 68 INSTANCE0, 69 70 NUM_STEERING_TYPES 71 }; 72 73 enum intel_submission_method { 74 INTEL_SUBMISSION_RING, 75 INTEL_SUBMISSION_ELSP, 76 INTEL_SUBMISSION_GUC, 77 }; 78 79 struct intel_gt { 80 struct drm_i915_private *i915; 81 struct intel_uncore *uncore; 82 struct i915_ggtt *ggtt; 83 84 struct intel_uc uc; 85 struct intel_gsc gsc; 86 87 struct { 88 /* Serialize global tlb invalidations */ 89 struct mutex invalidate_lock; 90 91 /* 92 * Batch TLB invalidations 93 * 94 * After unbinding the PTE, we need to ensure the TLB 95 * are invalidated prior to releasing the physical pages. 96 * But we only need one such invalidation for all unbinds, 97 * so we track how many TLB invalidations have been 98 * performed since unbind the PTE and only emit an extra 99 * invalidate if no full barrier has been passed. 100 */ 101 seqcount_mutex_t seqno; 102 } tlb; 103 104 struct i915_wa_list wa_list; 105 106 struct intel_gt_timelines { 107 spinlock_t lock; /* protects active_list */ 108 struct list_head active_list; 109 } timelines; 110 111 struct intel_gt_requests { 112 /** 113 * We leave the user IRQ off as much as possible, 114 * but this means that requests will finish and never 115 * be retired once the system goes idle. Set a timer to 116 * fire periodically while the ring is running. When it 117 * fires, go retire requests. 118 */ 119 struct delayed_work retire_work; 120 } requests; 121 122 struct { 123 struct llist_head list; 124 struct work_struct work; 125 } watchdog; 126 127 struct intel_wakeref wakeref; 128 atomic_t user_wakeref; 129 130 struct list_head closed_vma; 131 spinlock_t closed_lock; /* guards the list of closed_vma */ 132 133 ktime_t last_init_time; 134 struct intel_reset reset; 135 136 /** 137 * Is the GPU currently considered idle, or busy executing 138 * userspace requests? Whilst idle, we allow runtime power 139 * management to power down the hardware and display clocks. 140 * In order to reduce the effect on performance, there 141 * is a slight delay before we do so. 142 */ 143 intel_wakeref_t awake; 144 145 u32 clock_frequency; 146 u32 clock_period_ns; 147 148 struct intel_llc llc; 149 struct intel_rc6 rc6; 150 struct intel_rps rps; 151 152 spinlock_t irq_lock; 153 u32 gt_imr; 154 u32 pm_ier; 155 u32 pm_imr; 156 157 u32 pm_guc_events; 158 159 struct { 160 bool active; 161 162 /** 163 * @lock: Lock protecting the below fields. 164 */ 165 seqcount_mutex_t lock; 166 167 /** 168 * @total: Total time this engine was busy. 169 * 170 * Accumulated time not counting the most recent block in cases 171 * where engine is currently busy (active > 0). 172 */ 173 ktime_t total; 174 175 /** 176 * @start: Timestamp of the last idle to active transition. 177 * 178 * Idle is defined as active == 0, active is active > 0. 179 */ 180 ktime_t start; 181 } stats; 182 183 struct intel_engine_cs *engine[I915_NUM_ENGINES]; 184 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1] 185 [MAX_ENGINE_INSTANCE + 1]; 186 enum intel_submission_method submission_method; 187 188 /* 189 * Default address space (either GGTT or ppGTT depending on arch). 190 * 191 * Reserved for exclusive use by the kernel. 192 */ 193 struct i915_address_space *vm; 194 195 /* 196 * A pool of objects to use as shadow copies of client batch buffers 197 * when the command parser is enabled. Prevents the client from 198 * modifying the batch contents after software parsing. 199 * 200 * Buffers older than 1s are periodically reaped from the pool, 201 * or may be reclaimed by the shrinker before then. 202 */ 203 struct intel_gt_buffer_pool buffer_pool; 204 205 struct i915_vma *scratch; 206 207 struct intel_migrate migrate; 208 209 const struct intel_mmio_range *steering_table[NUM_STEERING_TYPES]; 210 211 struct { 212 u8 groupid; 213 u8 instanceid; 214 } default_steering; 215 216 /* 217 * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT. 218 */ 219 phys_addr_t phys_addr; 220 221 struct intel_gt_info { 222 unsigned int id; 223 224 intel_engine_mask_t engine_mask; 225 226 u32 l3bank_mask; 227 228 u8 num_engines; 229 230 /* General presence of SFC units */ 231 u8 sfc_mask; 232 233 /* Media engine access to SFC per instance */ 234 u8 vdbox_sfc_access; 235 236 /* Slice/subslice/EU info */ 237 struct sseu_dev_info sseu; 238 239 unsigned long mslice_mask; 240 241 /** @hwconfig: hardware configuration data */ 242 struct intel_hwconfig hwconfig; 243 } info; 244 245 struct { 246 u8 uc_index; 247 u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */ 248 } mocs; 249 250 struct intel_pxp pxp; 251 252 /* gt/gtN sysfs */ 253 struct kobject sysfs_gt; 254 }; 255 256 enum intel_gt_scratch_field { 257 /* 8 bytes */ 258 INTEL_GT_SCRATCH_FIELD_DEFAULT = 0, 259 260 /* 8 bytes */ 261 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128, 262 263 /* 8 bytes */ 264 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256, 265 266 /* 6 * 8 bytes */ 267 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048, 268 269 /* 4 bytes */ 270 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096, 271 }; 272 273 #endif /* __INTEL_GT_TYPES_H__ */ 274