1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_GT_TYPES__ 7 #define __INTEL_GT_TYPES__ 8 9 #include <linux/ktime.h> 10 #include <linux/list.h> 11 #include <linux/llist.h> 12 #include <linux/mutex.h> 13 #include <linux/notifier.h> 14 #include <linux/seqlock.h> 15 #include <linux/spinlock.h> 16 #include <linux/types.h> 17 #include <linux/workqueue.h> 18 19 #include "uc/intel_uc.h" 20 #include "intel_gsc.h" 21 22 #include "i915_vma.h" 23 #include "intel_engine_types.h" 24 #include "intel_gt_buffer_pool_types.h" 25 #include "intel_hwconfig.h" 26 #include "intel_llc_types.h" 27 #include "intel_reset_types.h" 28 #include "intel_rc6_types.h" 29 #include "intel_rps_types.h" 30 #include "intel_migrate_types.h" 31 #include "intel_wakeref.h" 32 #include "pxp/intel_pxp_types.h" 33 34 struct drm_i915_private; 35 struct i915_ggtt; 36 struct intel_engine_cs; 37 struct intel_uncore; 38 39 struct intel_mmio_range { 40 u32 start; 41 u32 end; 42 }; 43 44 /* 45 * The hardware has multiple kinds of multicast register ranges that need 46 * special register steering (and future platforms are expected to add 47 * additional types). 48 * 49 * During driver startup, we initialize the steering control register to 50 * direct reads to a slice/subslice that are valid for the 'subslice' class 51 * of multicast registers. If another type of steering does not have any 52 * overlap in valid steering targets with 'subslice' style registers, we will 53 * need to explicitly re-steer reads of registers of the other type. 54 * 55 * Only the replication types that may need additional non-default steering 56 * are listed here. 57 */ 58 enum intel_steering_type { 59 L3BANK, 60 MSLICE, 61 LNCF, 62 63 /* 64 * On some platforms there are multiple types of MCR registers that 65 * will always return a non-terminated value at instance (0, 0). We'll 66 * lump those all into a single category to keep things simple. 67 */ 68 INSTANCE0, 69 70 NUM_STEERING_TYPES 71 }; 72 73 enum intel_submission_method { 74 INTEL_SUBMISSION_RING, 75 INTEL_SUBMISSION_ELSP, 76 INTEL_SUBMISSION_GUC, 77 }; 78 79 struct gt_defaults { 80 u32 min_freq; 81 u32 max_freq; 82 }; 83 84 struct intel_gt { 85 struct drm_i915_private *i915; 86 struct intel_uncore *uncore; 87 struct i915_ggtt *ggtt; 88 89 struct intel_uc uc; 90 struct intel_gsc gsc; 91 92 struct { 93 /* Serialize global tlb invalidations */ 94 struct mutex invalidate_lock; 95 96 /* 97 * Batch TLB invalidations 98 * 99 * After unbinding the PTE, we need to ensure the TLB 100 * are invalidated prior to releasing the physical pages. 101 * But we only need one such invalidation for all unbinds, 102 * so we track how many TLB invalidations have been 103 * performed since unbind the PTE and only emit an extra 104 * invalidate if no full barrier has been passed. 105 */ 106 seqcount_mutex_t seqno; 107 } tlb; 108 109 struct i915_wa_list wa_list; 110 111 struct intel_gt_timelines { 112 spinlock_t lock; /* protects active_list */ 113 struct list_head active_list; 114 } timelines; 115 116 struct intel_gt_requests { 117 /** 118 * We leave the user IRQ off as much as possible, 119 * but this means that requests will finish and never 120 * be retired once the system goes idle. Set a timer to 121 * fire periodically while the ring is running. When it 122 * fires, go retire requests. 123 */ 124 struct delayed_work retire_work; 125 } requests; 126 127 struct { 128 struct llist_head list; 129 struct work_struct work; 130 } watchdog; 131 132 struct intel_wakeref wakeref; 133 atomic_t user_wakeref; 134 135 struct list_head closed_vma; 136 spinlock_t closed_lock; /* guards the list of closed_vma */ 137 138 ktime_t last_init_time; 139 struct intel_reset reset; 140 141 /** 142 * Is the GPU currently considered idle, or busy executing 143 * userspace requests? Whilst idle, we allow runtime power 144 * management to power down the hardware and display clocks. 145 * In order to reduce the effect on performance, there 146 * is a slight delay before we do so. 147 */ 148 intel_wakeref_t awake; 149 150 u32 clock_frequency; 151 u32 clock_period_ns; 152 153 struct intel_llc llc; 154 struct intel_rc6 rc6; 155 struct intel_rps rps; 156 157 spinlock_t irq_lock; 158 u32 gt_imr; 159 u32 pm_ier; 160 u32 pm_imr; 161 162 u32 pm_guc_events; 163 164 struct { 165 bool active; 166 167 /** 168 * @lock: Lock protecting the below fields. 169 */ 170 seqcount_mutex_t lock; 171 172 /** 173 * @total: Total time this engine was busy. 174 * 175 * Accumulated time not counting the most recent block in cases 176 * where engine is currently busy (active > 0). 177 */ 178 ktime_t total; 179 180 /** 181 * @start: Timestamp of the last idle to active transition. 182 * 183 * Idle is defined as active == 0, active is active > 0. 184 */ 185 ktime_t start; 186 } stats; 187 188 struct intel_engine_cs *engine[I915_NUM_ENGINES]; 189 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1] 190 [MAX_ENGINE_INSTANCE + 1]; 191 enum intel_submission_method submission_method; 192 193 /* 194 * Default address space (either GGTT or ppGTT depending on arch). 195 * 196 * Reserved for exclusive use by the kernel. 197 */ 198 struct i915_address_space *vm; 199 200 /* 201 * A pool of objects to use as shadow copies of client batch buffers 202 * when the command parser is enabled. Prevents the client from 203 * modifying the batch contents after software parsing. 204 * 205 * Buffers older than 1s are periodically reaped from the pool, 206 * or may be reclaimed by the shrinker before then. 207 */ 208 struct intel_gt_buffer_pool buffer_pool; 209 210 struct i915_vma *scratch; 211 212 struct intel_migrate migrate; 213 214 const struct intel_mmio_range *steering_table[NUM_STEERING_TYPES]; 215 216 struct { 217 u8 groupid; 218 u8 instanceid; 219 } default_steering; 220 221 /* 222 * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT. 223 */ 224 phys_addr_t phys_addr; 225 226 struct intel_gt_info { 227 unsigned int id; 228 229 intel_engine_mask_t engine_mask; 230 231 u32 l3bank_mask; 232 233 u8 num_engines; 234 235 /* General presence of SFC units */ 236 u8 sfc_mask; 237 238 /* Media engine access to SFC per instance */ 239 u8 vdbox_sfc_access; 240 241 /* Slice/subslice/EU info */ 242 struct sseu_dev_info sseu; 243 244 unsigned long mslice_mask; 245 246 /** @hwconfig: hardware configuration data */ 247 struct intel_hwconfig hwconfig; 248 } info; 249 250 struct { 251 u8 uc_index; 252 u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */ 253 } mocs; 254 255 struct intel_pxp pxp; 256 257 /* gt/gtN sysfs */ 258 struct kobject sysfs_gt; 259 260 /* sysfs defaults per gt */ 261 struct gt_defaults defaults; 262 struct kobject *sysfs_defaults; 263 }; 264 265 enum intel_gt_scratch_field { 266 /* 8 bytes */ 267 INTEL_GT_SCRATCH_FIELD_DEFAULT = 0, 268 269 /* 8 bytes */ 270 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128, 271 272 /* 8 bytes */ 273 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256, 274 275 /* 6 * 8 bytes */ 276 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048, 277 278 /* 4 bytes */ 279 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096, 280 }; 281 282 #endif /* __INTEL_GT_TYPES_H__ */ 283