1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_GT_REGS__ 7 #define __INTEL_GT_REGS__ 8 9 #include "i915_reg_defs.h" 10 #include "display/intel_display_reg_defs.h" /* VLV_DISPLAY_BASE */ 11 12 /* 13 * The perf control registers are technically multicast registers, but the 14 * driver never needs to read/write them directly; we only use them to build 15 * lists of registers (where they're mixed in with other non-MCR registers) 16 * and then operate on the offset directly. For now we'll just define them 17 * as non-multicast so we can place them on the same list, but we may want 18 * to try to come up with a better way to handle heterogeneous lists of 19 * registers in the future. 20 */ 21 #define PERF_REG(offset) _MMIO(offset) 22 23 /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ 24 #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60) 25 #define MTL_CAGF_MASK REG_GENMASK(8, 0) 26 #define MTL_CC0 0x0 27 #define MTL_CC6 0x3 28 #define MTL_CC_MASK REG_GENMASK(12, 9) 29 30 /* RPM unit config (Gen8+) */ 31 #define RPM_CONFIG0 _MMIO(0xd00) 32 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 33 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 34 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0 35 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1 36 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 37 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 38 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 39 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 40 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 41 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 42 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1 43 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT) 44 45 #define RPM_CONFIG1 _MMIO(0xd04) 46 #define GEN10_GT_NOA_ENABLE (1 << 9) 47 48 /* RCP unit config (Gen8+) */ 49 #define RCP_CONFIG _MMIO(0xd08) 50 51 #define RC6_LOCATION _MMIO(0xd40) 52 #define RC6_CTX_IN_DRAM (1 << 0) 53 #define RC6_CTX_BASE _MMIO(0xd48) 54 #define RC6_CTX_BASE_MASK 0xFFFFFFF0 55 56 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4) 57 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4) 58 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84) 59 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88) 60 61 #define FORCEWAKE_ACK_GSC _MMIO(0xdf8) 62 #define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc) 63 64 #define GMD_ID_GRAPHICS _MMIO(0xd8c) 65 #define GMD_ID_MEDIA _MMIO(MTL_MEDIA_GSI_BASE + 0xd8c) 66 67 #define MCFG_MCR_SELECTOR _MMIO(0xfd0) 68 #define MTL_STEER_SEMAPHORE _MMIO(0xfd0) 69 #define MTL_MCR_SELECTOR _MMIO(0xfd4) 70 #define SF_MCR_SELECTOR _MMIO(0xfd8) 71 #define GEN8_MCR_SELECTOR _MMIO(0xfdc) 72 #define GAM_MCR_SELECTOR _MMIO(0xfe0) 73 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26) 74 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3) 75 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24) 76 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3) 77 #define GEN11_MCR_MULTICAST REG_BIT(31) 78 #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27) 79 #define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf) 80 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24) 81 #define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7) 82 #define MTL_MCR_GROUPID REG_GENMASK(11, 8) 83 #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0) 84 85 #define IPEIR_I965 _MMIO(0x2064) 86 #define IPEHR_I965 _MMIO(0x2068) 87 88 /* 89 * On GEN4, only the render ring INSTDONE exists and has a different 90 * layout than the GEN7+ version. 91 * The GEN2 counterpart of this register is GEN2_INSTDONE. 92 */ 93 #define INSTPS _MMIO(0x2070) /* 965+ only */ 94 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ 95 #define ACTHD_I965 _MMIO(0x2074) 96 #define HWS_PGA _MMIO(0x2080) 97 #define HWS_ADDRESS_MASK 0xfffff000 98 #define HWS_START_ADDRESS_SHIFT 4 99 100 #define _3D_CHICKEN _MMIO(0x2084) 101 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 102 103 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ 104 #define PWRCTX_EN (1 << 0) 105 106 #define FF_SLICE_CHICKEN _MMIO(0x2088) 107 #define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1) 108 109 /* GM45+ chicken bits -- debug workaround bits that may be required 110 * for various sorts of correct behavior. The top 16 bits of each are 111 * the enables for writing to the corresponding low bit. 112 */ 113 #define _3D_CHICKEN2 _MMIO(0x208c) 114 /* Disables pipelining of read flushes past the SF-WIZ interface. 115 * Required on all Ironlake steppings according to the B-Spec, but the 116 * particular danger of not doing so is not specified. 117 */ 118 #define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 119 120 #define _3D_CHICKEN3 _MMIO(0x2090) 121 #define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12) 122 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 123 #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5) 124 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 125 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */ 126 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 127 128 #define GEN2_INSTDONE _MMIO(0x2090) 129 #define NOPID _MMIO(0x2094) 130 #define HWSTAM _MMIO(0x2098) 131 132 #define WAIT_FOR_RC6_EXIT _MMIO(0x20cc) 133 /* HSW only */ 134 #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2 135 #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT) 136 #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4 137 #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT) 138 /* HSW+ */ 139 #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0) 140 #define HSW_RCS_CONTEXT_ENABLE (1 << 7) 141 #define HSW_RCS_INHIBIT (1 << 8) 142 /* Gen8 */ 143 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 144 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 145 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 146 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 147 #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6) 148 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9 149 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT) 150 #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11 151 #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT) 152 #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13) 153 154 #define GEN6_GT_MODE _MMIO(0x20d0) 155 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 156 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 157 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 158 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 159 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) 160 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 161 162 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ 163 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4) 164 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) 165 #define GEN11_ENABLE_32_PLANE_MODE (1 << 7) 166 167 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) 168 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14) 169 170 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) 171 #define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8) 172 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10) 173 #define GEN12_PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15) 174 175 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) 176 #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1) 177 #define GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON _MMIO(0x20ec) 178 #define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0) 179 180 /* WaClearTdlStateAckDirtyBits */ 181 #define GEN8_STATE_ACK _MMIO(0x20f0) 182 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20f8) 183 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100) 184 #define GEN9_STATE_ACK_TDL0 (1 << 12) 185 #define GEN9_STATE_ACK_TDL1 (1 << 13) 186 #define GEN9_STATE_ACK_TDL2 (1 << 14) 187 #define GEN9_STATE_ACK_TDL3 (1 << 15) 188 #define GEN9_SUBSLICE_TDL_ACK_BITS \ 189 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ 190 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) 191 192 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ 193 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8) 194 #define CM0_IZ_OPT_DISABLE (1 << 6) 195 #define CM0_ZR_OPT_DISABLE (1 << 5) 196 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5) 197 #define CM0_DEPTH_EVICT_DISABLE (1 << 4) 198 #define CM0_COLOR_EVICT_DISABLE (1 << 3) 199 #define CM0_DEPTH_WRITE_DISABLE (1 << 1) 200 #define CM0_RC_OP_FLUSH_DISABLE (1 << 0) 201 202 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ 203 204 /* 205 * Logical Context regs 206 */ 207 /* 208 * Notes on SNB/IVB/VLV context size: 209 * - Power context is saved elsewhere (LLC or stolen) 210 * - Ring/execlist context is saved on SNB, not on IVB 211 * - Extended context size already includes render context size 212 * - We always need to follow the extended context size. 213 * SNB BSpec has comments indicating that we should use the 214 * render context size instead if execlists are disabled, but 215 * based on empirical testing that's just nonsense. 216 * - Pipelined/VF state is saved on SNB/IVB respectively 217 * - GT1 size just indicates how much of render context 218 * doesn't need saving on GT1 219 */ 220 #define CXT_SIZE _MMIO(0x21a0) 221 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f) 222 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f) 223 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f) 224 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f) 225 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f) 226 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 227 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 228 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 229 #define GEN7_CXT_SIZE _MMIO(0x21a8) 230 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) 231 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) 232 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) 233 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) 234 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) 235 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) 236 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 237 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 238 239 #define HSW_MI_PREDICATE_RESULT_2 _MMIO(0x2214) 240 241 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) 242 #define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11) 243 244 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) 245 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) 246 247 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4) 248 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac) 249 250 #define HS_INVOCATION_COUNT _MMIO(0x2300) 251 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) 252 #define DS_INVOCATION_COUNT _MMIO(0x2308) 253 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) 254 #define IA_VERTICES_COUNT _MMIO(0x2310) 255 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) 256 #define IA_PRIMITIVES_COUNT _MMIO(0x2318) 257 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) 258 #define VS_INVOCATION_COUNT _MMIO(0x2320) 259 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) 260 #define GS_INVOCATION_COUNT _MMIO(0x2328) 261 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) 262 #define GS_PRIMITIVES_COUNT _MMIO(0x2330) 263 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) 264 #define CL_INVOCATION_COUNT _MMIO(0x2338) 265 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) 266 #define CL_PRIMITIVES_COUNT _MMIO(0x2340) 267 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) 268 #define PS_INVOCATION_COUNT _MMIO(0x2348) 269 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) 270 #define PS_DEPTH_COUNT _MMIO(0x2350) 271 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) 272 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) 273 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) 274 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) 275 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) 276 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243c) 277 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) 278 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) 279 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) 280 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) 281 282 #define GFX_MODE _MMIO(0x2520) 283 284 #define GEN8_CS_CHICKEN1 _MMIO(0x2580) 285 #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0) 286 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1)) 287 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0) 288 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1) 289 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0) 290 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1) 291 292 #define DRAW_WATERMARK _MMIO(0x26c0) 293 #define VERT_WM_VAL REG_GENMASK(9, 0) 294 295 #define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */ 296 297 #define RENDER_HWS_PGA_GEN7 _MMIO(0x4080) 298 299 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) 300 #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF 301 #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7) 302 303 #define GAM_ECOCHK _MMIO(0x4090) 304 #define BDW_DISABLE_HDC_INVALIDATION (1 << 25) 305 #define ECOCHK_SNB_BIT (1 << 10) 306 #define ECOCHK_DIS_TLB (1 << 8) 307 #define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6) 308 #define ECOCHK_PPGTT_CACHE64B (0x3 << 3) 309 #define ECOCHK_PPGTT_CACHE4B (0x0 << 3) 310 #define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4) 311 #define ECOCHK_PPGTT_LLC_IVB (0x1 << 3) 312 #define ECOCHK_PPGTT_UC_HSW (0x1 << 3) 313 #define ECOCHK_PPGTT_WT_HSW (0x2 << 3) 314 #define ECOCHK_PPGTT_WB_HSW (0x3 << 3) 315 316 #define GEN8_RING_FAULT_REG _MMIO(0x4094) 317 #define _RING_FAULT_REG_RCS 0x4094 318 #define _RING_FAULT_REG_VCS 0x4194 319 #define _RING_FAULT_REG_BCS 0x4294 320 #define _RING_FAULT_REG_VECS 0x4394 321 #define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \ 322 _RING_FAULT_REG_RCS, \ 323 _RING_FAULT_REG_VCS, \ 324 _RING_FAULT_REG_VECS, \ 325 _RING_FAULT_REG_BCS)) 326 327 #define ERROR_GEN6 _MMIO(0x40a0) 328 329 #define DONE_REG _MMIO(0x40b0) 330 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) 331 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) 332 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4) 333 #define BSD_HWS_PGA_GEN7 _MMIO(0x4180) 334 #define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208) 335 #define GEN12_VD0_AUX_NV _MMIO(0x4218) 336 #define GEN12_VD1_AUX_NV _MMIO(0x4228) 337 338 #define GEN8_RTCR _MMIO(0x4260) 339 #define GEN8_M1TCR _MMIO(0x4264) 340 #define GEN8_M2TCR _MMIO(0x4268) 341 #define GEN8_BTCR _MMIO(0x426c) 342 #define GEN8_VTCR _MMIO(0x4270) 343 344 #define GEN12_VD2_AUX_NV _MMIO(0x4298) 345 #define GEN12_VD3_AUX_NV _MMIO(0x42a8) 346 #define GEN12_VE0_AUX_NV _MMIO(0x4238) 347 348 #define BLT_HWS_PGA_GEN7 _MMIO(0x4280) 349 350 #define GEN12_VE1_AUX_NV _MMIO(0x42b8) 351 #define AUX_INV REG_BIT(0) 352 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x4380) 353 354 #define GEN12_AUX_ERR_DBG _MMIO(0x43f4) 355 356 #define GEN7_TLB_RD_ADDR _MMIO(0x4700) 357 358 #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4) 359 #define XEHP_PAT_INDEX(index) MCR_REG(0x4800 + (index) * 4) 360 361 #define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900) 362 #define XEHP_TILE_LMEM_RANGE_SHIFT 8 363 364 #define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910) 365 #define XEHP_CCS_BASE_SHIFT 8 366 367 #define GAMTARBMODE _MMIO(0x4a08) 368 #define ARB_MODE_BWGTLB_DISABLE (1 << 9) 369 #define ARB_MODE_SWIZZLE_BDW (1 << 1) 370 371 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0) 372 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18) 373 374 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) 375 #define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31) 376 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28) 377 #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24) 378 379 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) 380 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) 381 382 #define GEN11_GACB_PERF_CTRL _MMIO(0x4b80) 383 #define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0) 384 #define GEN11_HASH_CTRL_BIT0 (1 << 0) 385 #define GEN11_HASH_CTRL_BIT4 (1 << 12) 386 387 /* gamt regs */ 388 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) 389 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ 390 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ 391 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ 392 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ 393 394 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */ 395 #define MMCD_PCLA (1 << 31) 396 #define MMCD_HOTSPOT_EN (1 << 27) 397 398 /* There are the 4 64-bit counter registers, one for each stream output */ 399 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) 400 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) 401 402 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) 403 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) 404 405 #define GEN9_WM_CHICKEN3 _MMIO(0x5588) 406 #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9) 407 408 #define XEHP_CULLBIT1 MCR_REG(0x6100) 409 410 #define CHICKEN_RASTER_1 MCR_REG(0x6204) 411 #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8) 412 413 #define CHICKEN_RASTER_2 MCR_REG(0x6208) 414 #define TBIMR_FAST_CLIP REG_BIT(5) 415 416 #define VFLSKPD MCR_REG(0x62a8) 417 #define VF_PREFETCH_TLB_DIS REG_BIT(5) 418 #define DIS_OVER_FETCH_CACHE REG_BIT(1) 419 #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) 420 421 #define GEN12_FF_MODE2 _MMIO(0x6604) 422 #define XEHP_FF_MODE2 MCR_REG(0x6604) 423 #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) 424 #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) 425 #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) 426 #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) 427 428 #define XEHPG_INSTDONE_GEOM_SVG MCR_REG(0x666c) 429 430 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ 431 #define RC_OP_FLUSH_ENABLE (1 << 0) 432 #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) 433 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ 434 #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) 435 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6) 436 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6) 437 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1) 438 439 #define GEN7_GT_MODE _MMIO(0x7008) 440 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) 441 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) 442 443 /* GEN7 chicken */ 444 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) 445 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10) 446 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14) 447 448 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) 449 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13) 450 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12) 451 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8) 452 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0) 453 454 #define HIZ_CHICKEN _MMIO(0x7018) 455 #define CHV_HZ_8X8_MODE_IN_1X REG_BIT(15) 456 #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14) 457 #define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13) 458 #define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE REG_BIT(3) 459 460 #define XEHP_CULLBIT2 MCR_REG(0x7030) 461 462 #define GEN8_L3CNTLREG _MMIO(0x7034) 463 #define GEN8_ERRDETBCTRL (1 << 9) 464 465 #define XEHP_PSS_MODE2 MCR_REG(0x703c) 466 #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) 467 468 #define GEN7_SC_INSTDONE _MMIO(0x7100) 469 #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) 470 #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) 471 472 /* GEN8 chicken */ 473 #define HDC_CHICKEN0 _MMIO(0x7300) 474 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15) 475 #define HDC_FENCE_DEST_SLM_DISABLE (1 << 14) 476 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11) 477 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5) 478 #define HDC_FORCE_NON_COHERENT (1 << 4) 479 #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10) 480 481 #define COMMON_SLICE_CHICKEN4 _MMIO(0x7300) 482 #define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) 483 484 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) 485 486 #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) 487 #define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304) 488 #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) 489 #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12) 490 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) 491 #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) 492 493 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) 494 #define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c) 495 #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) 496 #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) 497 498 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) 499 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ 500 ((slice) % 3) * 0x4) 501 #define GEN9_PGCTL_SLICE_ACK (1 << 0) 502 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) 503 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) 504 505 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) 506 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ 507 ((slice) % 3) * 0x8) 508 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) 509 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ 510 ((slice) % 3) * 0x8) 511 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) 512 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) 513 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) 514 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) 515 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) 516 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) 517 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) 518 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) 519 520 #define VF_PREEMPTION _MMIO(0x83a4) 521 #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) 522 523 #define VFG_PREEMPTION_CHICKEN _MMIO(0x83b4) 524 #define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4) 525 526 #define GEN8_RC6_CTX_INFO _MMIO(0x8504) 527 528 #define XEHP_SQCM MCR_REG(0x8724) 529 #define EN_32B_ACCESS REG_BIT(30) 530 531 #define HSW_IDICR _MMIO(0x9008) 532 #define IDIHASHMSK(x) (((x) & 0x3f) << 16) 533 534 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ 535 #define GEN6_MBC_SNPCR_SHIFT 21 536 #define GEN6_MBC_SNPCR_MASK (3 << 21) 537 #define GEN6_MBC_SNPCR_MAX (0 << 21) 538 #define GEN6_MBC_SNPCR_MED (1 << 21) 539 #define GEN6_MBC_SNPCR_LOW (2 << 21) 540 #define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */ 541 542 #define VLV_G3DCTL _MMIO(0x9024) 543 #define VLV_GSCKGCTL _MMIO(0x9028) 544 545 /* WaCatErrorRejectionIssue */ 546 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) 547 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11) 548 549 #define FBC_LLC_READ_CTRL _MMIO(0x9044) 550 #define FBC_LLC_FULLY_OPEN REG_BIT(30) 551 552 #define GEN6_MBCTL _MMIO(0x907c) 553 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 554 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 555 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 556 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 557 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 558 559 /* Fuse readout registers for GT */ 560 #define XEHP_FUSE4 _MMIO(0x9114) 561 #define GT_L3_EXC_MASK REG_GENMASK(6, 4) 562 #define GEN10_MIRROR_FUSE3 _MMIO(0x9118) 563 #define GEN10_L3BANK_PAIR_COUNT 4 564 #define GEN10_L3BANK_MASK 0x0F 565 /* on Xe_HP the same fuses indicates mslices instead of L3 banks */ 566 #define GEN12_MAX_MSLICES 4 567 #define GEN12_MEML3_EN_MASK 0x0F 568 569 #define HSW_PAVP_FUSE1 _MMIO(0x911c) 570 #define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24) 571 #define HSW_F1_EU_DIS_MASK REG_GENMASK(17, 16) 572 #define HSW_F1_EU_DIS_10EUS 0 573 #define HSW_F1_EU_DIS_8EUS 1 574 #define HSW_F1_EU_DIS_6EUS 2 575 576 #define GEN8_FUSE2 _MMIO(0x9120) 577 #define GEN8_F2_SS_DIS_SHIFT 21 578 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) 579 #define GEN8_F2_S_ENA_SHIFT 25 580 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) 581 #define GEN9_F2_SS_DIS_SHIFT 20 582 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) 583 #define GEN10_F2_S_ENA_SHIFT 22 584 #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT) 585 #define GEN10_F2_SS_DIS_SHIFT 18 586 #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT) 587 588 #define GEN8_EU_DISABLE0 _MMIO(0x9134) 589 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4) 590 #define GEN11_EU_DISABLE _MMIO(0x9134) 591 #define GEN8_EU_DIS0_S0_MASK 0xffffff 592 #define GEN8_EU_DIS0_S1_SHIFT 24 593 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) 594 #define GEN11_EU_DIS_MASK 0xFF 595 #define XEHP_EU_ENABLE _MMIO(0x9134) 596 #define XEHP_EU_ENA_MASK 0xFF 597 598 #define GEN8_EU_DISABLE1 _MMIO(0x9138) 599 #define GEN8_EU_DIS1_S1_MASK 0xffff 600 #define GEN8_EU_DIS1_S2_SHIFT 16 601 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) 602 603 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138) 604 #define GEN11_GT_S_ENA_MASK 0xFF 605 606 #define GEN8_EU_DISABLE2 _MMIO(0x913c) 607 #define GEN8_EU_DIS2_S2_MASK 0xff 608 609 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913c) 610 #define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913c) 611 612 #define GEN10_EU_DISABLE3 _MMIO(0x9140) 613 #define GEN10_EU_DIS_SS_MASK 0xff 614 #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140) 615 #define GEN11_GT_VDBOX_DISABLE_MASK 0xff 616 #define GEN11_GT_VEBOX_DISABLE_SHIFT 16 617 #define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT) 618 619 #define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144) 620 #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148) 621 622 #define GEN6_UCGCTL1 _MMIO(0x9400) 623 #define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22) 624 #define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 625 #define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 626 #define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 627 628 #define GEN6_UCGCTL2 _MMIO(0x9404) 629 #define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) 630 #define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 631 #define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 632 #define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 633 #define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 634 #define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 635 636 #define GEN6_UCGCTL3 _MMIO(0x9408) 637 #define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20) 638 639 #define GEN7_UCGCTL4 _MMIO(0x940c) 640 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25) 641 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14) 642 643 #define GEN6_RCGCTL1 _MMIO(0x9410) 644 #define GEN6_RCGCTL2 _MMIO(0x9414) 645 646 #define GEN6_GDRST _MMIO(0x941c) 647 #define GEN6_GRDOM_FULL (1 << 0) 648 #define GEN6_GRDOM_RENDER (1 << 1) 649 #define GEN6_GRDOM_MEDIA (1 << 2) 650 #define GEN6_GRDOM_BLT (1 << 3) 651 #define GEN6_GRDOM_VECS (1 << 4) 652 #define GEN9_GRDOM_GUC (1 << 5) 653 #define GEN8_GRDOM_MEDIA2 (1 << 7) 654 /* GEN11 changed all bit defs except for FULL & RENDER */ 655 #define GEN11_GRDOM_FULL GEN6_GRDOM_FULL 656 #define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER 657 #define XEHPC_GRDOM_BLT8 REG_BIT(31) 658 #define XEHPC_GRDOM_BLT7 REG_BIT(30) 659 #define XEHPC_GRDOM_BLT6 REG_BIT(29) 660 #define XEHPC_GRDOM_BLT5 REG_BIT(28) 661 #define XEHPC_GRDOM_BLT4 REG_BIT(27) 662 #define XEHPC_GRDOM_BLT3 REG_BIT(26) 663 #define XEHPC_GRDOM_BLT2 REG_BIT(25) 664 #define XEHPC_GRDOM_BLT1 REG_BIT(24) 665 #define GEN12_GRDOM_GSC REG_BIT(21) 666 #define GEN11_GRDOM_SFC3 REG_BIT(20) 667 #define GEN11_GRDOM_SFC2 REG_BIT(19) 668 #define GEN11_GRDOM_SFC1 REG_BIT(18) 669 #define GEN11_GRDOM_SFC0 REG_BIT(17) 670 #define GEN11_GRDOM_VECS4 REG_BIT(16) 671 #define GEN11_GRDOM_VECS3 REG_BIT(15) 672 #define GEN11_GRDOM_VECS2 REG_BIT(14) 673 #define GEN11_GRDOM_VECS REG_BIT(13) 674 #define GEN11_GRDOM_MEDIA8 REG_BIT(12) 675 #define GEN11_GRDOM_MEDIA7 REG_BIT(11) 676 #define GEN11_GRDOM_MEDIA6 REG_BIT(10) 677 #define GEN11_GRDOM_MEDIA5 REG_BIT(9) 678 #define GEN11_GRDOM_MEDIA4 REG_BIT(8) 679 #define GEN11_GRDOM_MEDIA3 REG_BIT(7) 680 #define GEN11_GRDOM_MEDIA2 REG_BIT(6) 681 #define GEN11_GRDOM_MEDIA REG_BIT(5) 682 #define GEN11_GRDOM_GUC REG_BIT(3) 683 #define GEN11_GRDOM_BLT REG_BIT(2) 684 #define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1)) 685 #define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance)) 686 687 #define GEN6_RSTCTL _MMIO(0x9420) 688 689 #define GEN7_MISCCPCTL _MMIO(0x9424) 690 #define GEN7_DOP_CLOCK_GATE_ENABLE REG_BIT(0) 691 #define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) 692 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) 693 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4) 694 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6) 695 696 #define GEN8_UCGCTL6 _MMIO(0x9430) 697 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24) 698 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14) 699 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28) 700 701 #define UNSLCGCTL9430 _MMIO(0x9430) 702 #define MSQDUNIT_CLKGATE_DIS REG_BIT(3) 703 704 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) 705 #define VFUNIT_CLKGATE_DIS REG_BIT(20) 706 #define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */ 707 #define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */ 708 #define GAMEDIA_CLKGATE_DIS REG_BIT(11) 709 #define HSUNIT_CLKGATE_DIS REG_BIT(8) 710 #define VSUNIT_CLKGATE_DIS REG_BIT(3) 711 712 #define UNSLCGCTL9440 _MMIO(0x9440) 713 #define GAMTLBOACS_CLKGATE_DIS REG_BIT(28) 714 #define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27) 715 #define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26) 716 #define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24) 717 #define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23) 718 #define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22) 719 #define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21) 720 #define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17) 721 #define GAMTLBKCR_CLKGATE_DIS REG_BIT(16) 722 #define GAMTLBGUC_CLKGATE_DIS REG_BIT(15) 723 #define GAMTLBBLT_CLKGATE_DIS REG_BIT(14) 724 #define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6) 725 726 #define UNSLCGCTL9444 _MMIO(0x9444) 727 #define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30) 728 #define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29) 729 #define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28) 730 #define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27) 731 #define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26) 732 #define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25) 733 #define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24) 734 #define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23) 735 #define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22) 736 #define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21) 737 #define GAMTLBMERT_CLKGATE_DIS REG_BIT(20) 738 #define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19) 739 #define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18) 740 #define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17) 741 #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16) 742 #define LTCDD_CLKGATE_DIS REG_BIT(10) 743 744 #define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) 745 #define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4) 746 #define SARBUNIT_CLKGATE_DIS (1 << 5) 747 #define RCCUNIT_CLKGATE_DIS (1 << 7) 748 #define MSCUNIT_CLKGATE_DIS (1 << 10) 749 #define NODEDSS_CLKGATE_DIS REG_BIT(12) 750 #define L3_CLKGATE_DIS REG_BIT(16) 751 #define L3_CR2X_CLKGATE_DIS REG_BIT(17) 752 753 #define SCCGCTL94DC MCR_REG(0x94dc) 754 #define CG3DDISURB REG_BIT(14) 755 756 #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4) 757 #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19) 758 #define PSDUNIT_CLKGATE_DIS REG_BIT(5) 759 760 #define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524) 761 #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28) 762 #define GWUNIT_CLKGATE_DIS REG_BIT(16) 763 764 #define SUBSLICE_UNIT_LEVEL_CLKGATE2 MCR_REG(0x9528) 765 #define CPSSUNIT_CLKGATE_DIS REG_BIT(9) 766 767 #define SSMCGCTL9530 MCR_REG(0x9530) 768 #define RTFUNIT_CLKGATE_DIS REG_BIT(18) 769 770 #define GEN10_DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550) 771 #define DFR_DISABLE (1 << 9) 772 773 #define MICRO_BP0_0 _MMIO(0x9800) 774 #define MICRO_BP0_2 _MMIO(0x9804) 775 #define MICRO_BP0_1 _MMIO(0x9808) 776 #define MICRO_BP1_0 _MMIO(0x980c) 777 #define MICRO_BP1_2 _MMIO(0x9810) 778 #define MICRO_BP1_1 _MMIO(0x9814) 779 #define MICRO_BP2_0 _MMIO(0x9818) 780 #define MICRO_BP2_2 _MMIO(0x981c) 781 #define MICRO_BP2_1 _MMIO(0x9820) 782 #define MICRO_BP3_0 _MMIO(0x9824) 783 #define MICRO_BP3_2 _MMIO(0x9828) 784 #define MICRO_BP3_1 _MMIO(0x982c) 785 #define MICRO_BP_TRIGGER _MMIO(0x9830) 786 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834) 787 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838) 788 #define MICRO_BP_FIRED_ARMED _MMIO(0x983c) 789 790 #define GEN6_GFXPAUSE _MMIO(0xa000) 791 #define GEN6_RPNSWREQ _MMIO(0xa008) 792 #define GEN6_TURBO_DISABLE (1 << 31) 793 #define GEN6_FREQUENCY(x) ((x) << 25) 794 #define HSW_FREQUENCY(x) ((x) << 24) 795 #define GEN9_FREQUENCY(x) ((x) << 23) 796 #define GEN6_OFFSET(x) ((x) << 19) 797 #define GEN6_AGGRESSIVE_TURBO (0 << 15) 798 #define GEN9_SW_REQ_UNSLICE_RATIO_SHIFT 23 799 #define GEN9_IGNORE_SLICE_RATIO (0 << 0) 800 #define GEN12_MEDIA_FREQ_RATIO REG_BIT(13) 801 802 #define GEN6_RC_VIDEO_FREQ _MMIO(0xa00c) 803 #define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16) 804 #define GEN6_RC_CTL_RC6p_ENABLE (1 << 17) 805 #define GEN6_RC_CTL_RC6_ENABLE (1 << 18) 806 #define GEN6_RC_CTL_RC1e_ENABLE (1 << 20) 807 #define GEN6_RC_CTL_RC7_ENABLE (1 << 22) 808 #define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24) 809 #define GEN7_RC_CTL_TO_MODE (1 << 28) 810 #define GEN6_RC_CTL_EI_MODE(x) ((x) << 27) 811 #define GEN6_RC_CTL_HW_ENABLE (1 << 31) 812 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xa010) 813 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xa014) 814 #define GEN6_RPSTAT1 _MMIO(0xa01c) 815 #define GEN6_CAGF_MASK REG_GENMASK(14, 8) 816 #define HSW_CAGF_MASK REG_GENMASK(13, 7) 817 #define GEN9_CAGF_MASK REG_GENMASK(31, 23) 818 #define GEN6_RP_CONTROL _MMIO(0xa024) 819 #define GEN6_RP_MEDIA_TURBO (1 << 11) 820 #define GEN6_RP_MEDIA_MODE_MASK (3 << 9) 821 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9) 822 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9) 823 #define GEN6_RP_MEDIA_HW_MODE (1 << 9) 824 #define GEN6_RP_MEDIA_SW_MODE (0 << 9) 825 #define GEN6_RP_MEDIA_IS_GFX (1 << 8) 826 #define GEN6_RP_ENABLE (1 << 7) 827 #define GEN6_RP_UP_IDLE_MIN (0x1 << 3) 828 #define GEN6_RP_UP_BUSY_AVG (0x2 << 3) 829 #define GEN6_RP_UP_BUSY_CONT (0x4 << 3) 830 #define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0) 831 #define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0) 832 #define GEN6_RPSWCTL_SHIFT 9 833 #define GEN9_RPSWCTL_ENABLE (0x2 << GEN6_RPSWCTL_SHIFT) 834 #define GEN9_RPSWCTL_DISABLE (0x0 << GEN6_RPSWCTL_SHIFT) 835 #define GEN6_RP_UP_THRESHOLD _MMIO(0xa02c) 836 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xa030) 837 #define GEN6_RP_CUR_UP_EI _MMIO(0xa050) 838 #define GEN6_RP_EI_MASK 0xffffff 839 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK 840 #define GEN6_RP_CUR_UP _MMIO(0xa054) 841 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK 842 #define GEN6_RP_PREV_UP _MMIO(0xa058) 843 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xa05c) 844 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK 845 #define GEN6_RP_CUR_DOWN _MMIO(0xa060) 846 #define GEN6_RP_PREV_DOWN _MMIO(0xa064) 847 #define GEN6_RP_UP_EI _MMIO(0xa068) 848 #define GEN6_RP_DOWN_EI _MMIO(0xa06c) 849 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xa070) 850 #define GEN6_RPDEUHWTC _MMIO(0xa080) 851 #define GEN6_RPDEUC _MMIO(0xa084) 852 #define GEN6_RPDEUCSW _MMIO(0xa088) 853 #define GEN6_RC_CONTROL _MMIO(0xa090) 854 #define GEN6_RC_STATE _MMIO(0xa094) 855 #define RC_SW_TARGET_STATE_SHIFT 16 856 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT) 857 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xa098) 858 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xa09c) 859 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xa0a0) 860 #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xa0a0) 861 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xa0a8) 862 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xa0ac) 863 #define GEN6_RC_SLEEP _MMIO(0xa0b0) 864 #define GEN6_RCUBMABDTMR _MMIO(0xa0b0) 865 #define GEN6_RC1e_THRESHOLD _MMIO(0xa0b4) 866 #define GEN6_RC6_THRESHOLD _MMIO(0xa0b8) 867 #define GEN6_RC6p_THRESHOLD _MMIO(0xa0bc) 868 #define VLV_RCEDATA _MMIO(0xa0bc) 869 #define GEN6_RC6pp_THRESHOLD _MMIO(0xa0c0) 870 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xa0c4) 871 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xa0c8) 872 873 #define GEN6_PMINTRMSK _MMIO(0xa168) 874 #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31) 875 #define ARAT_EXPIRED_INTRMSK (1 << 9) 876 877 #define GEN8_MISC_CTRL0 _MMIO(0xa180) 878 879 #define ECOBUS _MMIO(0xa180) 880 #define FORCEWAKE_MT_ENABLE (1 << 5) 881 882 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */ 883 #define FORCEWAKE_GT_GEN9 _MMIO(0xa188) 884 #define FORCEWAKE _MMIO(0xa18c) 885 886 #define VLV_SPAREG2H _MMIO(0xa194) 887 888 #define GEN9_PG_ENABLE _MMIO(0xa210) 889 #define GEN9_RENDER_PG_ENABLE REG_BIT(0) 890 #define GEN9_MEDIA_PG_ENABLE REG_BIT(1) 891 #define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2) 892 #define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n)) 893 #define VDN_MFX_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n)) 894 895 #define GEN8_PUSHBUS_CONTROL _MMIO(0xa248) 896 #define GEN8_PUSHBUS_ENABLE _MMIO(0xa250) 897 #define GEN8_PUSHBUS_SHIFT _MMIO(0xa25c) 898 899 /* GPM unit config (Gen9+) */ 900 #define CTC_MODE _MMIO(0xa26c) 901 #define CTC_SOURCE_PARAMETER_MASK 1 902 #define CTC_SOURCE_CRYSTAL_CLOCK 0 903 #define CTC_SOURCE_DIVIDE_LOGIC 1 904 #define CTC_SHIFT_PARAMETER_SHIFT 1 905 #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT) 906 907 /* GPM MSG_IDLE */ 908 #define MSG_IDLE_CS _MMIO(0x8000) 909 #define MSG_IDLE_VCS0 _MMIO(0x8004) 910 #define MSG_IDLE_VCS1 _MMIO(0x8008) 911 #define MSG_IDLE_BCS _MMIO(0x800C) 912 #define MSG_IDLE_VECS0 _MMIO(0x8010) 913 #define MSG_IDLE_VCS2 _MMIO(0x80C0) 914 #define MSG_IDLE_VCS3 _MMIO(0x80C4) 915 #define MSG_IDLE_VCS4 _MMIO(0x80C8) 916 #define MSG_IDLE_VCS5 _MMIO(0x80CC) 917 #define MSG_IDLE_VCS6 _MMIO(0x80D0) 918 #define MSG_IDLE_VCS7 _MMIO(0x80D4) 919 #define MSG_IDLE_VECS1 _MMIO(0x80D8) 920 #define MSG_IDLE_VECS2 _MMIO(0x80DC) 921 #define MSG_IDLE_VECS3 _MMIO(0x80E0) 922 #define MSG_IDLE_FW_MASK REG_GENMASK(13, 9) 923 #define MSG_IDLE_FW_SHIFT 9 924 925 #define RC_PSMI_CTRL_GSCCS _MMIO(0x11a050) 926 #define IDLE_MSG_DISABLE REG_BIT(0) 927 #define PWRCTX_MAXCNT_GSCCS _MMIO(0x11a054) 928 929 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270) 930 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) 931 932 #define VLV_PWRDWNUPCTL _MMIO(0xa294) 933 934 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xa2a0) 935 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0) 936 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1) 937 938 #define MISC_STATUS0 _MMIO(0xa500) 939 #define MISC_STATUS1 _MMIO(0xa504) 940 941 #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4) 942 #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4) 943 944 #define FORCEWAKE_REQ_GSC _MMIO(0xa618) 945 946 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) 947 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) 948 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) 949 #define CHV_SS_PG_ENABLE (1 << 1) 950 #define CHV_EU08_PG_ENABLE (1 << 9) 951 #define CHV_EU19_PG_ENABLE (1 << 17) 952 #define CHV_EU210_PG_ENABLE (1 << 25) 953 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) 954 #define CHV_EU311_PG_ENABLE (1 << 1) 955 956 #define GEN7_SARCHKMD _MMIO(0xb000) 957 #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31) 958 #define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30) 959 960 #define GEN8_GARBCNTL _MMIO(0xb004) 961 #define GEN11_ARBITRATION_PRIO_ORDER_MASK REG_GENMASK(27, 22) 962 #define GEN12_BUS_HASH_CTL_BIT_EXC REG_BIT(7) 963 #define GEN9_GAPS_TSV_CREDIT_DISABLE REG_BIT(7) 964 #define GEN11_HASH_CTRL_EXCL_MASK REG_GENMASK(6, 0) 965 #define GEN11_HASH_CTRL_EXCL_BIT0 REG_FIELD_PREP(GEN11_HASH_CTRL_EXCL_MASK, 0x1) 966 967 #define GEN9_SCRATCH_LNCF1 _MMIO(0xb008) 968 #define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0) 969 970 #define GEN7_L3SQCREG1 _MMIO(0xb010) 971 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 972 973 #define GEN7_L3CNTLREG1 _MMIO(0xb01c) 974 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 975 #define GEN7_L3AGDIS (1 << 19) 976 977 #define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c) 978 #define XEHPC_HOSTCACHEEN REG_BIT(1) 979 #define XEHPC_OVRLSCCC REG_BIT(0) 980 981 #define GEN7_L3CNTLREG2 _MMIO(0xb020) 982 983 /* MOCS (Memory Object Control State) registers */ 984 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ 985 #define XEHP_LNCFCMOCS(i) MCR_REG(0xb020 + (i) * 4) 986 #define LNCFCMOCS_REG_COUNT 32 987 988 #define GEN7_L3CNTLREG3 _MMIO(0xb024) 989 990 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xb030) 991 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 992 993 #define GEN7_L3SQCREG4 _MMIO(0xb034) 994 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27) 995 996 #define HSW_SCRATCH1 _MMIO(0xb038) 997 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27) 998 999 #define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4) 1000 #define GEN7_L3LOG_SIZE 0x80 1001 1002 #define XEHP_L3NODEARBCFG MCR_REG(0xb0b4) 1003 #define XEHP_LNESPARE REG_BIT(19) 1004 1005 #define GEN8_L3SQCREG1 MCR_REG(0xb100) 1006 /* 1007 * Note that on CHV the following has an off-by-one error wrt. to BSpec. 1008 * Using the formula in BSpec leads to a hang, while the formula here works 1009 * fine and matches the formulas for all other platforms. A BSpec change 1010 * request has been filed to clarify this. 1011 */ 1012 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19) 1013 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14) 1014 #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14)) 1015 1016 #define GEN8_L3SQCREG4 MCR_REG(0xb118) 1017 #define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6) 1018 #define GEN8_LQSC_RO_PERF_DIS (1 << 27) 1019 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21) 1020 #define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22) 1021 1022 #define GEN9_SCRATCH1 MCR_REG(0xb11c) 1023 #define EVICTION_PERF_FIX_ENABLE REG_BIT(8) 1024 1025 #define BDW_SCRATCH1 MCR_REG(0xb11c) 1026 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) 1027 1028 #define GEN11_SCRATCH2 MCR_REG(0xb140) 1029 #define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19) 1030 1031 #define XEHP_L3SQCREG5 MCR_REG(0xb158) 1032 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) 1033 1034 #define MLTICTXCTL MCR_REG(0xb170) 1035 #define TDONRENDER REG_BIT(2) 1036 1037 #define XEHP_L3SCQREG7 MCR_REG(0xb188) 1038 #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3) 1039 1040 #define XEHPC_L3SCRUB MCR_REG(0xb18c) 1041 #define SCRUB_CL_DWNGRADE_SHARED REG_BIT(12) 1042 #define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0) 1043 #define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6) 1044 1045 #define L3SQCREG1_CCS0 MCR_REG(0xb200) 1046 #define FLUSHALLNONCOH REG_BIT(5) 1047 1048 #define GEN11_GLBLINVL _MMIO(0xb404) 1049 #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5) 1050 #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5) 1051 1052 #define GEN11_LSN_UNSLCVC _MMIO(0xb43c) 1053 #define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9) 1054 #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7) 1055 1056 #define GUCPMTIMESTAMP _MMIO(0xc3e8) 1057 1058 #define __GEN9_RCS0_MOCS0 0xc800 1059 #define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4) 1060 #define __GEN9_VCS0_MOCS0 0xc900 1061 #define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4) 1062 #define __GEN9_VCS1_MOCS0 0xca00 1063 #define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4) 1064 #define __GEN9_VECS0_MOCS0 0xcb00 1065 #define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4) 1066 #define __GEN9_BCS0_MOCS0 0xcc00 1067 #define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4) 1068 1069 #define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8) 1070 #define XEHP_FAULT_TLB_DATA0 MCR_REG(0xceb8) 1071 #define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc) 1072 #define XEHP_FAULT_TLB_DATA1 MCR_REG(0xcebc) 1073 #define FAULT_VA_HIGH_BITS (0xf << 0) 1074 #define FAULT_GTT_SEL (1 << 4) 1075 1076 #define GEN12_RING_FAULT_REG _MMIO(0xcec4) 1077 #define XEHP_RING_FAULT_REG MCR_REG(0xcec4) 1078 #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) 1079 #define RING_FAULT_GTTSEL_MASK (1 << 11) 1080 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) 1081 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) 1082 #define RING_FAULT_VALID (1 << 0) 1083 1084 #define GEN12_GFX_TLB_INV_CR _MMIO(0xced8) 1085 #define XEHP_GFX_TLB_INV_CR MCR_REG(0xced8) 1086 #define GEN12_VD_TLB_INV_CR _MMIO(0xcedc) 1087 #define XEHP_VD_TLB_INV_CR MCR_REG(0xcedc) 1088 #define GEN12_VE_TLB_INV_CR _MMIO(0xcee0) 1089 #define XEHP_VE_TLB_INV_CR MCR_REG(0xcee0) 1090 #define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4) 1091 #define XEHP_BLT_TLB_INV_CR MCR_REG(0xcee4) 1092 #define GEN12_COMPCTX_TLB_INV_CR _MMIO(0xcf04) 1093 #define XEHP_COMPCTX_TLB_INV_CR MCR_REG(0xcf04) 1094 #define XELPMP_GSC_TLB_INV_CR _MMIO(0xcf04) /* media GT only */ 1095 1096 #define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28) 1097 #define RENDER_MOD_CTRL MCR_REG(0xcf2c) 1098 #define COMP_MOD_CTRL MCR_REG(0xcf30) 1099 #define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /* media GT only */ 1100 #define XEHP_VDBX_MOD_CTRL MCR_REG(0xcf34) 1101 #define XELPMP_VDBX_MOD_CTRL _MMIO(0xcf34) 1102 #define XEHP_VEBX_MOD_CTRL MCR_REG(0xcf38) 1103 #define XELPMP_VEBX_MOD_CTRL _MMIO(0xcf38) 1104 #define FORCE_MISS_FTLB REG_BIT(3) 1105 1106 #define XEHP_GAMSTLB_CTRL MCR_REG(0xcf4c) 1107 #define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12) 1108 #define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11) 1109 #define TAG_BLOCK_CLKGATE_DIS REG_BIT(7) 1110 1111 #define XEHP_GAMCNTRL_CTRL MCR_REG(0xcf54) 1112 #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12) 1113 #define GLOBAL_INVALIDATION_MODE REG_BIT(2) 1114 1115 #define GEN12_GAM_DONE _MMIO(0xcf68) 1116 1117 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */ 1118 #define GEN8_HALF_SLICE_CHICKEN1 MCR_REG(0xe100) 1119 #define GEN7_MAX_PS_THREAD_DEP (8 << 12) 1120 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10) 1121 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4) 1122 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3) 1123 1124 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) 1125 #define GEN8_SAMPLER_INSTDONE MCR_REG(0xe160) 1126 #define GEN7_ROW_INSTDONE _MMIO(0xe164) 1127 #define GEN8_ROW_INSTDONE MCR_REG(0xe164) 1128 1129 #define HALF_SLICE_CHICKEN2 MCR_REG(0xe180) 1130 #define GEN8_ST_PO_DISABLE (1 << 13) 1131 1132 #define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184) 1133 #define GEN8_HALF_SLICE_CHICKEN3 MCR_REG(0xe184) 1134 #define HSW_SAMPLE_C_PERFORMANCE (1 << 9) 1135 #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8) 1136 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5) 1137 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1) 1138 1139 #define GEN9_HALF_SLICE_CHICKEN5 MCR_REG(0xe188) 1140 #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5) 1141 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3) 1142 1143 #define GEN10_SAMPLER_MODE MCR_REG(0xe18c) 1144 #define ENABLE_SMALLPL REG_BIT(15) 1145 #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) 1146 #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) 1147 #define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3) 1148 #define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0) 1149 1150 #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194) 1151 #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) 1152 #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR REG_BIT(8) 1153 #define GEN9_ENABLE_YV12_BUGFIX REG_BIT(4) 1154 #define GEN9_ENABLE_GPGPU_PREEMPTION REG_BIT(2) 1155 1156 #define GEN10_CACHE_MODE_SS MCR_REG(0xe420) 1157 #define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10) 1158 #define DISABLE_ECC REG_BIT(5) 1159 #define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4) 1160 /* 1161 * We have both ENABLE and DISABLE defines below using the same bit because the 1162 * meaning depends on the target platform. There are no platform prefix for them 1163 * because different steppings of DG2 pick one or the other semantics. 1164 */ 1165 #define ENABLE_PREFETCH_INTO_IC REG_BIT(3) 1166 #define DISABLE_PREFETCH_INTO_IC REG_BIT(3) 1167 1168 #define EU_PERF_CNTL0 PERF_REG(0xe458) 1169 #define EU_PERF_CNTL4 PERF_REG(0xe45c) 1170 1171 #define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c) 1172 #define GEN12_DISABLE_GRF_CLEAR REG_BIT(13) 1173 #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11) 1174 #define GEN12_DISABLE_TDL_PUSH REG_BIT(9) 1175 #define GEN11_DIS_PICK_2ND_EU REG_BIT(7) 1176 #define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4) 1177 #define THREAD_EX_ARB_MODE REG_GENMASK(3, 2) 1178 #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) 1179 1180 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) 1181 #define GEN9_ROW_CHICKEN3 MCR_REG(0xe49c) 1182 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 1183 #define MTL_DISABLE_FIX_FOR_EOT_FLUSH REG_BIT(9) 1184 1185 #define GEN8_ROW_CHICKEN MCR_REG(0xe4f0) 1186 #define FLOW_CONTROL_ENABLE REG_BIT(15) 1187 #define UGM_BACKUP_MODE REG_BIT(13) 1188 #define MDQ_ARBITRATION_MODE REG_BIT(12) 1189 #define SYSTOLIC_DOP_CLOCK_GATING_DIS REG_BIT(10) 1190 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8) 1191 #define STALL_DOP_GATING_DISABLE REG_BIT(5) 1192 #define THROTTLE_12_5 REG_GENMASK(4, 2) 1193 #define DISABLE_EARLY_EOT REG_BIT(1) 1194 1195 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) 1196 1197 #define GEN8_ROW_CHICKEN2 MCR_REG(0xe4f4) 1198 #define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15) 1199 #define GEN12_DISABLE_EARLY_READ REG_BIT(14) 1200 #define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12) 1201 #define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) 1202 #define GEN12_DISABLE_DOP_GATING REG_BIT(0) 1203 1204 #define RT_CTRL MCR_REG(0xe530) 1205 #define DIS_NULL_QUERY REG_BIT(10) 1206 #define STACKID_CTRL REG_GENMASK(6, 5) 1207 #define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL, 0x2) 1208 1209 #define EU_PERF_CNTL1 PERF_REG(0xe558) 1210 #define EU_PERF_CNTL5 PERF_REG(0xe55c) 1211 1212 #define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0) 1213 #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) 1214 #define ICL_HDC_MODE MCR_REG(0xe5f4) 1215 1216 #define EU_PERF_CNTL2 PERF_REG(0xe658) 1217 #define EU_PERF_CNTL6 PERF_REG(0xe65c) 1218 #define EU_PERF_CNTL3 PERF_REG(0xe758) 1219 1220 #define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8) 1221 #define DISABLE_D8_D16_COASLESCE REG_BIT(30) 1222 #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) 1223 #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) 1224 #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) 1225 #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) 1226 #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) 1227 #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32) 1228 #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) 1229 1230 #define SARB_CHICKEN1 MCR_REG(0xe90c) 1231 #define COMP_CKN_IN REG_GENMASK(30, 29) 1232 1233 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) 1234 #define DOP_CLOCK_GATING_DISABLE (1 << 0) 1235 #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) 1236 #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) 1237 1238 #define __GEN11_VCS2_MOCS0 0x10000 1239 #define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4) 1240 1241 #define CRSTANDVID _MMIO(0x11100) 1242 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 1243 #define PXVFREQ_PX_MASK 0x7f000000 1244 #define PXVFREQ_PX_SHIFT 24 1245 #define VIDFREQ_BASE _MMIO(0x11110) 1246 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 1247 #define VIDFREQ2 _MMIO(0x11114) 1248 #define VIDFREQ3 _MMIO(0x11118) 1249 #define VIDFREQ4 _MMIO(0x1111c) 1250 #define VIDFREQ_P0_MASK 0x1f000000 1251 #define VIDFREQ_P0_SHIFT 24 1252 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 1253 #define VIDFREQ_P0_CSCLK_SHIFT 20 1254 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 1255 #define VIDFREQ_P0_CRCLK_SHIFT 16 1256 #define VIDFREQ_P1_MASK 0x00001f00 1257 #define VIDFREQ_P1_SHIFT 8 1258 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 1259 #define VIDFREQ_P1_CSCLK_SHIFT 4 1260 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 1261 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */ 1262 #define INTTOEXT_MAP3_SHIFT 24 1263 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 1264 #define INTTOEXT_MAP2_SHIFT 16 1265 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 1266 #define INTTOEXT_MAP1_SHIFT 8 1267 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 1268 #define INTTOEXT_MAP0_SHIFT 0 1269 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 1270 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ 1271 #define MEMCTL_CMD_MASK 0xe000 1272 #define MEMCTL_CMD_SHIFT 13 1273 #define MEMCTL_CMD_RCLK_OFF 0 1274 #define MEMCTL_CMD_RCLK_ON 1 1275 #define MEMCTL_CMD_CHFREQ 2 1276 #define MEMCTL_CMD_CHVID 3 1277 #define MEMCTL_CMD_VMMOFF 4 1278 #define MEMCTL_CMD_VMMON 5 1279 #define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears 1280 when command complete */ 1281 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 1282 #define MEMCTL_FREQ_SHIFT 8 1283 #define MEMCTL_SFCAVM (1 << 7) 1284 #define MEMCTL_TGT_VID_MASK 0x007f 1285 #define MEMIHYST _MMIO(0x1117c) 1286 #define MEMINTREN _MMIO(0x11180) /* 16 bits */ 1287 #define MEMINT_RSEXIT_EN (1 << 8) 1288 #define MEMINT_CX_SUPR_EN (1 << 7) 1289 #define MEMINT_CONT_BUSY_EN (1 << 6) 1290 #define MEMINT_AVG_BUSY_EN (1 << 5) 1291 #define MEMINT_EVAL_CHG_EN (1 << 4) 1292 #define MEMINT_MON_IDLE_EN (1 << 3) 1293 #define MEMINT_UP_EVAL_EN (1 << 2) 1294 #define MEMINT_DOWN_EVAL_EN (1 << 1) 1295 #define MEMINT_SW_CMD_EN (1 << 0) 1296 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */ 1297 #define MEM_RSEXIT_MASK 0xc000 1298 #define MEM_RSEXIT_SHIFT 14 1299 #define MEM_CONT_BUSY_MASK 0x3000 1300 #define MEM_CONT_BUSY_SHIFT 12 1301 #define MEM_AVG_BUSY_MASK 0x0c00 1302 #define MEM_AVG_BUSY_SHIFT 10 1303 #define MEM_EVAL_CHG_MASK 0x0300 1304 #define MEM_EVAL_BUSY_SHIFT 8 1305 #define MEM_MON_IDLE_MASK 0x00c0 1306 #define MEM_MON_IDLE_SHIFT 6 1307 #define MEM_UP_EVAL_MASK 0x0030 1308 #define MEM_UP_EVAL_SHIFT 4 1309 #define MEM_DOWN_EVAL_MASK 0x000c 1310 #define MEM_DOWN_EVAL_SHIFT 2 1311 #define MEM_SW_CMD_MASK 0x0003 1312 #define MEM_INT_STEER_GFX 0 1313 #define MEM_INT_STEER_CMR 1 1314 #define MEM_INT_STEER_SMI 2 1315 #define MEM_INT_STEER_SCI 3 1316 #define MEMINTRSTS _MMIO(0x11184) 1317 #define MEMINT_RSEXIT (1 << 7) 1318 #define MEMINT_CONT_BUSY (1 << 6) 1319 #define MEMINT_AVG_BUSY (1 << 5) 1320 #define MEMINT_EVAL_CHG (1 << 4) 1321 #define MEMINT_MON_IDLE (1 << 3) 1322 #define MEMINT_UP_EVAL (1 << 2) 1323 #define MEMINT_DOWN_EVAL (1 << 1) 1324 #define MEMINT_SW_CMD (1 << 0) 1325 #define MEMMODECTL _MMIO(0x11190) 1326 #define MEMMODE_BOOST_EN (1 << 31) 1327 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 1328 #define MEMMODE_BOOST_FREQ_SHIFT 24 1329 #define MEMMODE_IDLE_MODE_MASK 0x00030000 1330 #define MEMMODE_IDLE_MODE_SHIFT 16 1331 #define MEMMODE_IDLE_MODE_EVAL 0 1332 #define MEMMODE_IDLE_MODE_CONT 1 1333 #define MEMMODE_HWIDLE_EN (1 << 15) 1334 #define MEMMODE_SWMODE_EN (1 << 14) 1335 #define MEMMODE_RCLK_GATE (1 << 13) 1336 #define MEMMODE_HW_UPDATE (1 << 12) 1337 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 1338 #define MEMMODE_FSTART_SHIFT 8 1339 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 1340 #define MEMMODE_FMAX_SHIFT 4 1341 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 1342 #define RCBMAXAVG _MMIO(0x1119c) 1343 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */ 1344 #define SWMEMCMD_RENDER_OFF (0 << 13) 1345 #define SWMEMCMD_RENDER_ON (1 << 13) 1346 #define SWMEMCMD_SWFREQ (2 << 13) 1347 #define SWMEMCMD_TARVID (3 << 13) 1348 #define SWMEMCMD_VRM_OFF (4 << 13) 1349 #define SWMEMCMD_VRM_ON (5 << 13) 1350 #define CMDSTS (1 << 12) 1351 #define SFCAVM (1 << 11) 1352 #define SWFREQ_MASK 0x0380 /* P0-7 */ 1353 #define SWFREQ_SHIFT 7 1354 #define TARVID_MASK 0x001f 1355 #define MEMSTAT_CTG _MMIO(0x111a0) 1356 #define RCBMINAVG _MMIO(0x111a0) 1357 #define RCUPEI _MMIO(0x111b0) 1358 #define RCDNEI _MMIO(0x111b4) 1359 #define RSTDBYCTL _MMIO(0x111b8) 1360 #define RS1EN (1 << 31) 1361 #define RS2EN (1 << 30) 1362 #define RS3EN (1 << 29) 1363 #define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */ 1364 #define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */ 1365 #define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */ 1366 #define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */ 1367 #define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */ 1368 #define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */ 1369 #define RSX_STATUS_MASK (7 << 20) 1370 #define RSX_STATUS_ON (0 << 20) 1371 #define RSX_STATUS_RC1 (1 << 20) 1372 #define RSX_STATUS_RC1E (2 << 20) 1373 #define RSX_STATUS_RS1 (3 << 20) 1374 #define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */ 1375 #define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */ 1376 #define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */ 1377 #define RSX_STATUS_RSVD2 (7 << 20) 1378 #define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */ 1379 #define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */ 1380 #define JRSC (1 << 17) /* rsx coupled to cpu c-state */ 1381 #define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */ 1382 #define RS1CONTSAV_MASK (3 << 14) 1383 #define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */ 1384 #define RS1CONTSAV_RSVD (1 << 14) 1385 #define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */ 1386 #define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */ 1387 #define NORMSLEXLAT_MASK (3 << 12) 1388 #define SLOW_RS123 (0 << 12) 1389 #define SLOW_RS23 (1 << 12) 1390 #define SLOW_RS3 (2 << 12) 1391 #define NORMAL_RS123 (3 << 12) 1392 #define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */ 1393 #define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 1394 #define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */ 1395 #define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */ 1396 #define RS_CSTATE_MASK (3 << 4) 1397 #define RS_CSTATE_C367_RS1 (0 << 4) 1398 #define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4) 1399 #define RS_CSTATE_RSVD (2 << 4) 1400 #define RS_CSTATE_C367_RS2 (3 << 4) 1401 #define REDSAVES (1 << 3) /* no context save if was idle during rs0 */ 1402 #define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */ 1403 #define VIDCTL _MMIO(0x111c0) 1404 #define VIDSTS _MMIO(0x111c8) 1405 #define VIDSTART _MMIO(0x111cc) /* 8 bits */ 1406 #define MEMSTAT_ILK _MMIO(0x111f8) 1407 #define MEMSTAT_VID_MASK 0x7f00 1408 #define MEMSTAT_VID_SHIFT 8 1409 #define MEMSTAT_PSTATE_MASK REG_GENMASK(7, 3) 1410 #define MEMSTAT_MON_ACTV (1 << 2) 1411 #define MEMSTAT_SRC_CTL_MASK 0x0003 1412 #define MEMSTAT_SRC_CTL_CORE 0 1413 #define MEMSTAT_SRC_CTL_TRB 1 1414 #define MEMSTAT_SRC_CTL_THM 2 1415 #define MEMSTAT_SRC_CTL_STDBY 3 1416 #define PMMISC _MMIO(0x11214) 1417 #define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */ 1418 #define SDEW _MMIO(0x1124c) 1419 #define CSIEW0 _MMIO(0x11250) 1420 #define CSIEW1 _MMIO(0x11254) 1421 #define CSIEW2 _MMIO(0x11258) 1422 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ 1423 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ 1424 #define MCHAFE _MMIO(0x112c0) 1425 #define CSIEC _MMIO(0x112e0) 1426 #define DMIEC _MMIO(0x112e4) 1427 #define DDREC _MMIO(0x112e8) 1428 #define PEG0EC _MMIO(0x112ec) 1429 #define PEG1EC _MMIO(0x112f0) 1430 #define GFXEC _MMIO(0x112f4) 1431 #define INTTOEXT_BASE_ILK _MMIO(0x11300) 1432 #define RPPREVBSYTUPAVG _MMIO(0x113b8) 1433 #define RCPREVBSYTUPAVG _MMIO(0x113b8) 1434 #define RCPREVBSYTDNAVG _MMIO(0x113bc) 1435 #define RPPREVBSYTDNAVG _MMIO(0x113bc) 1436 #define ECR _MMIO(0x11600) 1437 #define ECR_GPFE (1 << 31) 1438 #define ECR_IMONE (1 << 30) 1439 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 1440 #define OGW0 _MMIO(0x11608) 1441 #define OGW1 _MMIO(0x1160c) 1442 #define EG0 _MMIO(0x11610) 1443 #define EG1 _MMIO(0x11614) 1444 #define EG2 _MMIO(0x11618) 1445 #define EG3 _MMIO(0x1161c) 1446 #define EG4 _MMIO(0x11620) 1447 #define EG5 _MMIO(0x11624) 1448 #define EG6 _MMIO(0x11628) 1449 #define EG7 _MMIO(0x1162c) 1450 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ 1451 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ 1452 #define LCFUSE02 _MMIO(0x116c0) 1453 #define LCFUSE_HIV_MASK 0x000000ff 1454 1455 #define GAC_ECO_BITS _MMIO(0x14090) 1456 #define ECOBITS_SNB_BIT (1 << 13) 1457 #define ECOBITS_PPGTT_CACHE64B (3 << 8) 1458 #define ECOBITS_PPGTT_CACHE4B (0 << 8) 1459 1460 #define GEN12_RCU_MODE _MMIO(0x14800) 1461 #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) 1462 1463 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) 1464 #define CHV_FGT_DISABLE_SS0 (1 << 10) 1465 #define CHV_FGT_DISABLE_SS1 (1 << 11) 1466 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 1467 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) 1468 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 1469 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) 1470 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 1471 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) 1472 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 1473 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) 1474 1475 #define BCS_SWCTRL _MMIO(0x22200) 1476 #define BCS_SRC_Y REG_BIT(0) 1477 #define BCS_DST_Y REG_BIT(1) 1478 1479 #define GAB_CTL _MMIO(0x24000) 1480 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8) 1481 1482 #define GEN6_PMISR _MMIO(0x44020) 1483 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */ 1484 #define GEN6_PMIIR _MMIO(0x44028) 1485 #define GEN6_PMIER _MMIO(0x4402c) 1486 #define GEN6_PM_MBOX_EVENT (1 << 25) 1487 #define GEN6_PM_THERMAL_EVENT (1 << 24) 1488 /* 1489 * For Gen11 these are in the upper word of the GPM_WGBOXPERF 1490 * registers. Shifting is handled on accessing the imr and ier. 1491 */ 1492 #define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6) 1493 #define GEN6_PM_RP_UP_THRESHOLD (1 << 5) 1494 #define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4) 1495 #define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2) 1496 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1) 1497 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \ 1498 GEN6_PM_RP_UP_THRESHOLD | \ 1499 GEN6_PM_RP_DOWN_EI_EXPIRED | \ 1500 GEN6_PM_RP_DOWN_THRESHOLD | \ 1501 GEN6_PM_RP_DOWN_TIMEOUT) 1502 1503 #define GEN7_GT_SCRATCH(i) _MMIO(0x4f100 + (i) * 4) 1504 #define GEN7_GT_SCRATCH_REG_NUM 8 1505 1506 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) 1507 #define GFX_FLSH_CNTL_EN (1 << 0) 1508 1509 #define GTFIFODBG _MMIO(0x120000) 1510 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20) 1511 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13) 1512 #define GT_FIFO_SBDROPERR (1 << 6) 1513 #define GT_FIFO_BLOBDROPERR (1 << 5) 1514 #define GT_FIFO_SB_READ_ABORTERR (1 << 4) 1515 #define GT_FIFO_DROPERR (1 << 3) 1516 #define GT_FIFO_OVFERR (1 << 2) 1517 #define GT_FIFO_IAWRERR (1 << 1) 1518 #define GT_FIFO_IARDERR (1 << 0) 1519 1520 #define GTFIFOCTL _MMIO(0x120008) 1521 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f 1522 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 1523 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) 1524 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) 1525 1526 #define FORCEWAKE_MT_ACK _MMIO(0x130040) 1527 #define FORCEWAKE_ACK_HSW _MMIO(0x130044) 1528 #define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044) 1529 #define FORCEWAKE_KERNEL BIT(0) 1530 #define FORCEWAKE_USER BIT(1) 1531 #define FORCEWAKE_KERNEL_FALLBACK BIT(15) 1532 #define FORCEWAKE_ACK _MMIO(0x130090) 1533 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) 1534 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 1535 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 1536 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 1537 #define VLV_GTLC_PW_STATUS _MMIO(0x130094) 1538 #define VLV_GTLC_ALLOWWAKEACK (1 << 0) 1539 #define VLV_GTLC_ALLOWWAKEERR (1 << 1) 1540 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 1541 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 1542 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098) 1543 #define VLV_GFX_CLK_STATUS_BIT (1 << 3) 1544 #define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2) 1545 #define FORCEWAKE_VLV _MMIO(0x1300b0) 1546 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) 1547 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) 1548 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) 1549 1550 #define MTL_MEDIA_MC6 _MMIO(0x138048) 1551 1552 #define MTL_GT_ACTIVITY_FACTOR _MMIO(0x138010) 1553 #define MTL_GT_L3_EXC_MASK REG_GENMASK(5, 3) 1554 1555 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) 1556 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 1557 1558 #define GEN6_GT_CORE_STATUS _MMIO(0x138060) 1559 #define GEN6_CORE_CPD_STATE_MASK (7 << 4) 1560 #define GEN6_RCn_MASK 7 1561 #define GEN6_RC0 0 1562 #define GEN6_RC3 2 1563 #define GEN6_RC6 3 1564 #define GEN6_RC7 4 1565 1566 #define GEN8_GT_SLICE_INFO _MMIO(0x138064) 1567 #define GEN8_LSLICESTAT_MASK 0x7 1568 1569 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) 1570 #define VLV_COUNTER_CONTROL _MMIO(0x138104) 1571 #define VLV_COUNT_RANGE_HIGH (1 << 15) 1572 #define VLV_MEDIA_RC0_COUNT_EN (1 << 5) 1573 #define VLV_RENDER_RC0_COUNT_EN (1 << 4) 1574 #define VLV_MEDIA_RC6_COUNT_EN (1 << 1) 1575 #define VLV_RENDER_RC6_COUNT_EN (1 << 0) 1576 #define GEN6_GT_GFX_RC6 _MMIO(0x138108) 1577 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810c) 1578 1579 #define GEN6_GT_GFX_RC6p _MMIO(0x13810c) 1580 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110) 1581 #define VLV_RENDER_C0_COUNT _MMIO(0x138118) 1582 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c) 1583 1584 #define GEN12_RPSTAT1 _MMIO(0x1381b4) 1585 #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) 1586 #define GEN12_CAGF_MASK REG_GENMASK(19, 11) 1587 1588 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) 1589 #define GEN11_CSME (31) 1590 #define GEN11_GUNIT (28) 1591 #define GEN11_GUC (25) 1592 #define MTL_MGUC (24) 1593 #define GEN11_WDPERF (20) 1594 #define GEN11_KCR (19) 1595 #define GEN11_GTPM (16) 1596 #define GEN11_BCS (15) 1597 #define XEHPC_BCS1 (14) 1598 #define XEHPC_BCS2 (13) 1599 #define XEHPC_BCS3 (12) 1600 #define XEHPC_BCS4 (11) 1601 #define XEHPC_BCS5 (10) 1602 #define XEHPC_BCS6 (9) 1603 #define XEHPC_BCS7 (8) 1604 #define XEHPC_BCS8 (23) 1605 #define GEN12_CCS3 (7) 1606 #define GEN12_CCS2 (6) 1607 #define GEN12_CCS1 (5) 1608 #define GEN12_CCS0 (4) 1609 #define GEN11_RCS0 (0) 1610 #define GEN11_VECS(x) (31 - (x)) 1611 #define GEN11_VCS(x) (x) 1612 1613 #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030) 1614 #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034) 1615 #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038) 1616 #define ENGINE1_MASK REG_GENMASK(31, 16) 1617 #define ENGINE0_MASK REG_GENMASK(15, 0) 1618 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c) 1619 #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040) 1620 #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044) 1621 #define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048) 1622 1623 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) 1624 #define GEN11_INTR_DATA_VALID (1 << 31) 1625 #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16) 1626 #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20) 1627 #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff) 1628 /* irq instances for OTHER_CLASS */ 1629 #define OTHER_GUC_INSTANCE 0 1630 #define OTHER_GTPM_INSTANCE 1 1631 #define OTHER_KCR_INSTANCE 4 1632 #define OTHER_GSC_INSTANCE 6 1633 #define OTHER_MEDIA_GUC_INSTANCE 16 1634 #define OTHER_MEDIA_GTPM_INSTANCE 17 1635 1636 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4)) 1637 1638 #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090) 1639 #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0) 1640 #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8) 1641 #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac) 1642 #define GEN12_VCS4_VCS5_INTR_MASK _MMIO(0x1900b0) 1643 #define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4) 1644 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0) 1645 #define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4) 1646 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8) 1647 #define MTL_GUC_MGUC_INTR_MASK _MMIO(0x1900e8) /* MTL+ */ 1648 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) 1649 #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0) 1650 #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) 1651 #define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100) 1652 #define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104) 1653 #define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110) 1654 #define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114) 1655 #define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118) 1656 #define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c) 1657 1658 #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000) 1659 1660 #define GT0_PACKAGE_ENERGY_STATUS _MMIO(0x250004) 1661 #define GT0_PACKAGE_RAPL_LIMIT _MMIO(0x250008) 1662 #define GT0_PACKAGE_POWER_SKU_UNIT _MMIO(0x250068) 1663 #define GT0_PLATFORM_ENERGY_STATUS _MMIO(0x25006c) 1664 1665 /* 1666 * Standalone Media's non-engine GT registers are located at their regular GT 1667 * offsets plus 0x380000. This extra offset is stored inside the intel_uncore 1668 * structure so that the existing code can be used for both GTs without 1669 * modification. 1670 */ 1671 #define MTL_MEDIA_GSI_BASE 0x380000 1672 1673 #endif /* __INTEL_GT_REGS__ */ 1674