1 // SPDX-License-Identifier: MIT 2 3 /* 4 * Copyright © 2019 Intel Corporation 5 */ 6 7 #include <linux/seq_file.h> 8 9 #include "i915_drv.h" 10 #include "intel_gt.h" 11 #include "intel_gt_clock_utils.h" 12 #include "intel_gt_debugfs.h" 13 #include "intel_gt_pm.h" 14 #include "intel_gt_pm_debugfs.h" 15 #include "intel_llc.h" 16 #include "intel_pcode.h" 17 #include "intel_rc6.h" 18 #include "intel_rps.h" 19 #include "intel_runtime_pm.h" 20 #include "intel_uncore.h" 21 #include "vlv_sideband.h" 22 23 int intel_gt_pm_debugfs_forcewake_user_open(struct intel_gt *gt) 24 { 25 atomic_inc(>->user_wakeref); 26 intel_gt_pm_get(gt); 27 if (GRAPHICS_VER(gt->i915) >= 6) 28 intel_uncore_forcewake_user_get(gt->uncore); 29 30 return 0; 31 } 32 33 int intel_gt_pm_debugfs_forcewake_user_release(struct intel_gt *gt) 34 { 35 if (GRAPHICS_VER(gt->i915) >= 6) 36 intel_uncore_forcewake_user_put(gt->uncore); 37 intel_gt_pm_put(gt); 38 atomic_dec(>->user_wakeref); 39 40 return 0; 41 } 42 43 static int forcewake_user_open(struct inode *inode, struct file *file) 44 { 45 struct intel_gt *gt = inode->i_private; 46 47 return intel_gt_pm_debugfs_forcewake_user_open(gt); 48 } 49 50 static int forcewake_user_release(struct inode *inode, struct file *file) 51 { 52 struct intel_gt *gt = inode->i_private; 53 54 return intel_gt_pm_debugfs_forcewake_user_release(gt); 55 } 56 57 static const struct file_operations forcewake_user_fops = { 58 .owner = THIS_MODULE, 59 .open = forcewake_user_open, 60 .release = forcewake_user_release, 61 }; 62 63 static int fw_domains_show(struct seq_file *m, void *data) 64 { 65 struct intel_gt *gt = m->private; 66 struct intel_uncore *uncore = gt->uncore; 67 struct intel_uncore_forcewake_domain *fw_domain; 68 unsigned int tmp; 69 70 seq_printf(m, "user.bypass_count = %u\n", 71 uncore->user_forcewake_count); 72 73 for_each_fw_domain(fw_domain, uncore, tmp) 74 seq_printf(m, "%s.wake_count = %u\n", 75 intel_uncore_forcewake_domain_to_str(fw_domain->id), 76 READ_ONCE(fw_domain->wake_count)); 77 78 return 0; 79 } 80 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains); 81 82 static void print_rc6_res(struct seq_file *m, 83 const char *title, 84 const i915_reg_t reg) 85 { 86 struct intel_gt *gt = m->private; 87 intel_wakeref_t wakeref; 88 89 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 90 seq_printf(m, "%s %u (%llu us)\n", title, 91 intel_uncore_read(gt->uncore, reg), 92 intel_rc6_residency_us(>->rc6, reg)); 93 } 94 95 static int vlv_drpc(struct seq_file *m) 96 { 97 struct intel_gt *gt = m->private; 98 struct intel_uncore *uncore = gt->uncore; 99 u32 rcctl1, pw_status; 100 101 pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS); 102 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); 103 104 seq_printf(m, "RC6 Enabled: %s\n", 105 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | 106 GEN6_RC_CTL_EI_MODE(1)))); 107 seq_printf(m, "Render Power Well: %s\n", 108 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); 109 seq_printf(m, "Media Power Well: %s\n", 110 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); 111 112 print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6); 113 print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); 114 115 return fw_domains_show(m, NULL); 116 } 117 118 static int gen6_drpc(struct seq_file *m) 119 { 120 struct intel_gt *gt = m->private; 121 struct drm_i915_private *i915 = gt->i915; 122 struct intel_uncore *uncore = gt->uncore; 123 u32 gt_core_status, rcctl1, rc6vids = 0; 124 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; 125 126 gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS); 127 128 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); 129 if (GRAPHICS_VER(i915) >= 9) { 130 gen9_powergate_enable = 131 intel_uncore_read(uncore, GEN9_PG_ENABLE); 132 gen9_powergate_status = 133 intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS); 134 } 135 136 if (GRAPHICS_VER(i915) <= 7) 137 sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, 138 &rc6vids, NULL); 139 140 seq_printf(m, "RC1e Enabled: %s\n", 141 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); 142 seq_printf(m, "RC6 Enabled: %s\n", 143 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 144 if (GRAPHICS_VER(i915) >= 9) { 145 seq_printf(m, "Render Well Gating Enabled: %s\n", 146 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); 147 seq_printf(m, "Media Well Gating Enabled: %s\n", 148 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); 149 } 150 seq_printf(m, "Deep RC6 Enabled: %s\n", 151 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); 152 seq_printf(m, "Deepest RC6 Enabled: %s\n", 153 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); 154 seq_puts(m, "Current RC state: "); 155 switch (gt_core_status & GEN6_RCn_MASK) { 156 case GEN6_RC0: 157 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) 158 seq_puts(m, "Core Power Down\n"); 159 else 160 seq_puts(m, "on\n"); 161 break; 162 case GEN6_RC3: 163 seq_puts(m, "RC3\n"); 164 break; 165 case GEN6_RC6: 166 seq_puts(m, "RC6\n"); 167 break; 168 case GEN6_RC7: 169 seq_puts(m, "RC7\n"); 170 break; 171 default: 172 seq_puts(m, "Unknown\n"); 173 break; 174 } 175 176 seq_printf(m, "Core Power Down: %s\n", 177 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); 178 if (GRAPHICS_VER(i915) >= 9) { 179 seq_printf(m, "Render Power Well: %s\n", 180 (gen9_powergate_status & 181 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); 182 seq_printf(m, "Media Power Well: %s\n", 183 (gen9_powergate_status & 184 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); 185 } 186 187 /* Not exactly sure what this is */ 188 print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", 189 GEN6_GT_GFX_RC6_LOCKED); 190 print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); 191 print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); 192 print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); 193 194 if (GRAPHICS_VER(i915) <= 7) { 195 seq_printf(m, "RC6 voltage: %dmV\n", 196 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); 197 seq_printf(m, "RC6+ voltage: %dmV\n", 198 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); 199 seq_printf(m, "RC6++ voltage: %dmV\n", 200 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); 201 } 202 203 return fw_domains_show(m, NULL); 204 } 205 206 static int ilk_drpc(struct seq_file *m) 207 { 208 struct intel_gt *gt = m->private; 209 struct intel_uncore *uncore = gt->uncore; 210 u32 rgvmodectl, rstdbyctl; 211 u16 crstandvid; 212 213 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); 214 rstdbyctl = intel_uncore_read(uncore, RSTDBYCTL); 215 crstandvid = intel_uncore_read16(uncore, CRSTANDVID); 216 217 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); 218 seq_printf(m, "Boost freq: %d\n", 219 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> 220 MEMMODE_BOOST_FREQ_SHIFT); 221 seq_printf(m, "HW control enabled: %s\n", 222 yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); 223 seq_printf(m, "SW control enabled: %s\n", 224 yesno(rgvmodectl & MEMMODE_SWMODE_EN)); 225 seq_printf(m, "Gated voltage change: %s\n", 226 yesno(rgvmodectl & MEMMODE_RCLK_GATE)); 227 seq_printf(m, "Starting frequency: P%d\n", 228 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); 229 seq_printf(m, "Max P-state: P%d\n", 230 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); 231 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); 232 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); 233 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); 234 seq_printf(m, "Render standby enabled: %s\n", 235 yesno(!(rstdbyctl & RCX_SW_EXIT))); 236 seq_puts(m, "Current RS state: "); 237 switch (rstdbyctl & RSX_STATUS_MASK) { 238 case RSX_STATUS_ON: 239 seq_puts(m, "on\n"); 240 break; 241 case RSX_STATUS_RC1: 242 seq_puts(m, "RC1\n"); 243 break; 244 case RSX_STATUS_RC1E: 245 seq_puts(m, "RC1E\n"); 246 break; 247 case RSX_STATUS_RS1: 248 seq_puts(m, "RS1\n"); 249 break; 250 case RSX_STATUS_RS2: 251 seq_puts(m, "RS2 (RC6)\n"); 252 break; 253 case RSX_STATUS_RS3: 254 seq_puts(m, "RC3 (RC6+)\n"); 255 break; 256 default: 257 seq_puts(m, "unknown\n"); 258 break; 259 } 260 261 return 0; 262 } 263 264 static int drpc_show(struct seq_file *m, void *unused) 265 { 266 struct intel_gt *gt = m->private; 267 struct drm_i915_private *i915 = gt->i915; 268 intel_wakeref_t wakeref; 269 int err = -ENODEV; 270 271 with_intel_runtime_pm(gt->uncore->rpm, wakeref) { 272 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 273 err = vlv_drpc(m); 274 else if (GRAPHICS_VER(i915) >= 6) 275 err = gen6_drpc(m); 276 else 277 err = ilk_drpc(m); 278 } 279 280 return err; 281 } 282 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(drpc); 283 284 void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) 285 { 286 struct drm_i915_private *i915 = gt->i915; 287 struct intel_uncore *uncore = gt->uncore; 288 struct intel_rps *rps = >->rps; 289 intel_wakeref_t wakeref; 290 291 wakeref = intel_runtime_pm_get(uncore->rpm); 292 293 if (GRAPHICS_VER(i915) == 5) { 294 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); 295 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK); 296 297 drm_printf(p, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 298 drm_printf(p, "Requested VID: %d\n", rgvswctl & 0x3f); 299 drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 300 MEMSTAT_VID_SHIFT); 301 drm_printf(p, "Current P-state: %d\n", 302 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); 303 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 304 u32 rpmodectl, freq_sts; 305 306 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL); 307 drm_printf(p, "Video Turbo Mode: %s\n", 308 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); 309 drm_printf(p, "HW control enabled: %s\n", 310 yesno(rpmodectl & GEN6_RP_ENABLE)); 311 drm_printf(p, "SW control enabled: %s\n", 312 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == 313 GEN6_RP_MEDIA_SW_MODE)); 314 315 vlv_punit_get(i915); 316 freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 317 vlv_punit_put(i915); 318 319 drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); 320 drm_printf(p, "DDR freq: %d MHz\n", i915->mem_freq); 321 322 drm_printf(p, "actual GPU freq: %d MHz\n", 323 intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); 324 325 drm_printf(p, "current GPU freq: %d MHz\n", 326 intel_gpu_freq(rps, rps->cur_freq)); 327 328 drm_printf(p, "max GPU freq: %d MHz\n", 329 intel_gpu_freq(rps, rps->max_freq)); 330 331 drm_printf(p, "min GPU freq: %d MHz\n", 332 intel_gpu_freq(rps, rps->min_freq)); 333 334 drm_printf(p, "idle GPU freq: %d MHz\n", 335 intel_gpu_freq(rps, rps->idle_freq)); 336 337 drm_printf(p, "efficient (RPe) frequency: %d MHz\n", 338 intel_gpu_freq(rps, rps->efficient_freq)); 339 } else if (GRAPHICS_VER(i915) >= 6) { 340 u32 rp_state_limits; 341 u32 gt_perf_status; 342 u32 rp_state_cap; 343 u32 rpmodectl, rpinclimit, rpdeclimit; 344 u32 rpstat, cagf, reqf; 345 u32 rpcurupei, rpcurup, rpprevup; 346 u32 rpcurdownei, rpcurdown, rpprevdown; 347 u32 rpupei, rpupt, rpdownei, rpdownt; 348 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; 349 int max_freq; 350 351 rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS); 352 rp_state_cap = intel_rps_read_state_cap(rps); 353 if (IS_GEN9_LP(i915)) 354 gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS); 355 else 356 gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS); 357 358 /* RPSTAT1 is in the GT power well */ 359 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 360 361 reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ); 362 if (GRAPHICS_VER(i915) >= 9) { 363 reqf >>= 23; 364 } else { 365 reqf &= ~GEN6_TURBO_DISABLE; 366 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 367 reqf >>= 24; 368 else 369 reqf >>= 25; 370 } 371 reqf = intel_gpu_freq(rps, reqf); 372 373 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL); 374 rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); 375 rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); 376 377 rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1); 378 rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; 379 rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; 380 rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; 381 rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; 382 rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; 383 rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; 384 385 rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI); 386 rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); 387 388 rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI); 389 rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); 390 391 cagf = intel_rps_read_actual_frequency(rps); 392 393 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 394 395 if (GRAPHICS_VER(i915) >= 11) { 396 pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE); 397 pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK); 398 /* 399 * The equivalent to the PM ISR & IIR cannot be read 400 * without affecting the current state of the system 401 */ 402 pm_isr = 0; 403 pm_iir = 0; 404 } else if (GRAPHICS_VER(i915) >= 8) { 405 pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2)); 406 pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2)); 407 pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2)); 408 pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2)); 409 } else { 410 pm_ier = intel_uncore_read(uncore, GEN6_PMIER); 411 pm_imr = intel_uncore_read(uncore, GEN6_PMIMR); 412 pm_isr = intel_uncore_read(uncore, GEN6_PMISR); 413 pm_iir = intel_uncore_read(uncore, GEN6_PMIIR); 414 } 415 pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK); 416 417 drm_printf(p, "Video Turbo Mode: %s\n", 418 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); 419 drm_printf(p, "HW control enabled: %s\n", 420 yesno(rpmodectl & GEN6_RP_ENABLE)); 421 drm_printf(p, "SW control enabled: %s\n", 422 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == 423 GEN6_RP_MEDIA_SW_MODE)); 424 425 drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", 426 pm_ier, pm_imr, pm_mask); 427 if (GRAPHICS_VER(i915) <= 10) 428 drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n", 429 pm_isr, pm_iir); 430 drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", 431 rps->pm_intrmsk_mbz); 432 drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 433 drm_printf(p, "Render p-state ratio: %d\n", 434 (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8); 435 drm_printf(p, "Render p-state VID: %d\n", 436 gt_perf_status & 0xff); 437 drm_printf(p, "Render p-state limit: %d\n", 438 rp_state_limits & 0xff); 439 drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat); 440 drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl); 441 drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit); 442 drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit); 443 drm_printf(p, "RPNSWREQ: %dMHz\n", reqf); 444 drm_printf(p, "CAGF: %dMHz\n", cagf); 445 drm_printf(p, "RP CUR UP EI: %d (%lldns)\n", 446 rpcurupei, 447 intel_gt_pm_interval_to_ns(gt, rpcurupei)); 448 drm_printf(p, "RP CUR UP: %d (%lldns)\n", 449 rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup)); 450 drm_printf(p, "RP PREV UP: %d (%lldns)\n", 451 rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup)); 452 drm_printf(p, "Up threshold: %d%%\n", 453 rps->power.up_threshold); 454 drm_printf(p, "RP UP EI: %d (%lldns)\n", 455 rpupei, intel_gt_pm_interval_to_ns(gt, rpupei)); 456 drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n", 457 rpupt, intel_gt_pm_interval_to_ns(gt, rpupt)); 458 459 drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n", 460 rpcurdownei, 461 intel_gt_pm_interval_to_ns(gt, rpcurdownei)); 462 drm_printf(p, "RP CUR DOWN: %d (%lldns)\n", 463 rpcurdown, 464 intel_gt_pm_interval_to_ns(gt, rpcurdown)); 465 drm_printf(p, "RP PREV DOWN: %d (%lldns)\n", 466 rpprevdown, 467 intel_gt_pm_interval_to_ns(gt, rpprevdown)); 468 drm_printf(p, "Down threshold: %d%%\n", 469 rps->power.down_threshold); 470 drm_printf(p, "RP DOWN EI: %d (%lldns)\n", 471 rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei)); 472 drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n", 473 rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt)); 474 475 max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 : 476 rp_state_cap >> 16) & 0xff; 477 max_freq *= (IS_GEN9_BC(i915) || 478 GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); 479 drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", 480 intel_gpu_freq(rps, max_freq)); 481 482 max_freq = (rp_state_cap & 0xff00) >> 8; 483 max_freq *= (IS_GEN9_BC(i915) || 484 GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); 485 drm_printf(p, "Nominal (RP1) frequency: %dMHz\n", 486 intel_gpu_freq(rps, max_freq)); 487 488 max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 : 489 rp_state_cap >> 0) & 0xff; 490 max_freq *= (IS_GEN9_BC(i915) || 491 GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); 492 drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n", 493 intel_gpu_freq(rps, max_freq)); 494 drm_printf(p, "Max overclocked frequency: %dMHz\n", 495 intel_gpu_freq(rps, rps->max_freq)); 496 497 drm_printf(p, "Current freq: %d MHz\n", 498 intel_gpu_freq(rps, rps->cur_freq)); 499 drm_printf(p, "Actual freq: %d MHz\n", cagf); 500 drm_printf(p, "Idle freq: %d MHz\n", 501 intel_gpu_freq(rps, rps->idle_freq)); 502 drm_printf(p, "Min freq: %d MHz\n", 503 intel_gpu_freq(rps, rps->min_freq)); 504 drm_printf(p, "Boost freq: %d MHz\n", 505 intel_gpu_freq(rps, rps->boost_freq)); 506 drm_printf(p, "Max freq: %d MHz\n", 507 intel_gpu_freq(rps, rps->max_freq)); 508 drm_printf(p, 509 "efficient (RPe) frequency: %d MHz\n", 510 intel_gpu_freq(rps, rps->efficient_freq)); 511 } else { 512 drm_puts(p, "no P-state info available\n"); 513 } 514 515 drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk); 516 drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq); 517 drm_printf(p, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); 518 519 intel_runtime_pm_put(uncore->rpm, wakeref); 520 } 521 522 static int frequency_show(struct seq_file *m, void *unused) 523 { 524 struct intel_gt *gt = m->private; 525 struct drm_printer p = drm_seq_file_printer(m); 526 527 intel_gt_pm_frequency_dump(gt, &p); 528 529 return 0; 530 } 531 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(frequency); 532 533 static int llc_show(struct seq_file *m, void *data) 534 { 535 struct intel_gt *gt = m->private; 536 struct drm_i915_private *i915 = gt->i915; 537 const bool edram = GRAPHICS_VER(i915) > 8; 538 struct intel_rps *rps = >->rps; 539 unsigned int max_gpu_freq, min_gpu_freq; 540 intel_wakeref_t wakeref; 541 int gpu_freq, ia_freq; 542 543 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(i915))); 544 seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC", 545 i915->edram_size_mb); 546 547 min_gpu_freq = rps->min_freq; 548 max_gpu_freq = rps->max_freq; 549 if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { 550 /* Convert GT frequency to 50 HZ units */ 551 min_gpu_freq /= GEN9_FREQ_SCALER; 552 max_gpu_freq /= GEN9_FREQ_SCALER; 553 } 554 555 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); 556 557 wakeref = intel_runtime_pm_get(gt->uncore->rpm); 558 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { 559 ia_freq = gpu_freq; 560 sandybridge_pcode_read(i915, 561 GEN6_PCODE_READ_MIN_FREQ_TABLE, 562 &ia_freq, NULL); 563 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", 564 intel_gpu_freq(rps, 565 (gpu_freq * 566 (IS_GEN9_BC(i915) || 567 GRAPHICS_VER(i915) >= 11 ? 568 GEN9_FREQ_SCALER : 1))), 569 ((ia_freq >> 0) & 0xff) * 100, 570 ((ia_freq >> 8) & 0xff) * 100); 571 } 572 intel_runtime_pm_put(gt->uncore->rpm, wakeref); 573 574 return 0; 575 } 576 577 static bool llc_eval(void *data) 578 { 579 struct intel_gt *gt = data; 580 581 return HAS_LLC(gt->i915); 582 } 583 584 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(llc); 585 586 static const char *rps_power_to_str(unsigned int power) 587 { 588 static const char * const strings[] = { 589 [LOW_POWER] = "low power", 590 [BETWEEN] = "mixed", 591 [HIGH_POWER] = "high power", 592 }; 593 594 if (power >= ARRAY_SIZE(strings) || !strings[power]) 595 return "unknown"; 596 597 return strings[power]; 598 } 599 600 static int rps_boost_show(struct seq_file *m, void *data) 601 { 602 struct intel_gt *gt = m->private; 603 struct drm_i915_private *i915 = gt->i915; 604 struct intel_rps *rps = >->rps; 605 606 seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps))); 607 seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps))); 608 seq_printf(m, "GPU busy? %s, %llums\n", 609 yesno(gt->awake), 610 ktime_to_ms(intel_gt_get_awake_time(gt))); 611 seq_printf(m, "Boosts outstanding? %d\n", 612 atomic_read(&rps->num_waiters)); 613 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 614 seq_printf(m, "Frequency requested %d, actual %d\n", 615 intel_gpu_freq(rps, rps->cur_freq), 616 intel_rps_read_actual_frequency(rps)); 617 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 618 intel_gpu_freq(rps, rps->min_freq), 619 intel_gpu_freq(rps, rps->min_freq_softlimit), 620 intel_gpu_freq(rps, rps->max_freq_softlimit), 621 intel_gpu_freq(rps, rps->max_freq)); 622 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 623 intel_gpu_freq(rps, rps->idle_freq), 624 intel_gpu_freq(rps, rps->efficient_freq), 625 intel_gpu_freq(rps, rps->boost_freq)); 626 627 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 628 629 if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) { 630 struct intel_uncore *uncore = gt->uncore; 631 u32 rpup, rpupei; 632 u32 rpdown, rpdownei; 633 634 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 635 rpup = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; 636 rpupei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; 637 rpdown = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; 638 rpdownei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; 639 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 640 641 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", 642 rps_power_to_str(rps->power.mode)); 643 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", 644 rpup && rpupei ? 100 * rpup / rpupei : 0, 645 rps->power.up_threshold); 646 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", 647 rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, 648 rps->power.down_threshold); 649 } else { 650 seq_puts(m, "\nRPS Autotuning inactive\n"); 651 } 652 653 return 0; 654 } 655 656 static bool rps_eval(void *data) 657 { 658 struct intel_gt *gt = data; 659 660 return HAS_RPS(gt->i915); 661 } 662 663 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost); 664 665 void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root) 666 { 667 static const struct intel_gt_debugfs_file files[] = { 668 { "drpc", &drpc_fops, NULL }, 669 { "frequency", &frequency_fops, NULL }, 670 { "forcewake", &fw_domains_fops, NULL }, 671 { "forcewake_user", &forcewake_user_fops, NULL}, 672 { "llc", &llc_fops, llc_eval }, 673 { "rps_boost", &rps_boost_fops, rps_eval }, 674 }; 675 676 intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); 677 } 678