1 // SPDX-License-Identifier: MIT 2 3 /* 4 * Copyright © 2019 Intel Corporation 5 */ 6 7 #include <linux/seq_file.h> 8 9 #include "i915_drv.h" 10 #include "i915_reg.h" 11 #include "intel_gt.h" 12 #include "intel_gt_clock_utils.h" 13 #include "intel_gt_debugfs.h" 14 #include "intel_gt_pm.h" 15 #include "intel_gt_pm_debugfs.h" 16 #include "intel_gt_regs.h" 17 #include "intel_llc.h" 18 #include "intel_pcode.h" 19 #include "intel_rc6.h" 20 #include "intel_rps.h" 21 #include "intel_runtime_pm.h" 22 #include "intel_uncore.h" 23 #include "vlv_sideband.h" 24 25 int intel_gt_pm_debugfs_forcewake_user_open(struct intel_gt *gt) 26 { 27 atomic_inc(>->user_wakeref); 28 intel_gt_pm_get(gt); 29 if (GRAPHICS_VER(gt->i915) >= 6) 30 intel_uncore_forcewake_user_get(gt->uncore); 31 32 return 0; 33 } 34 35 int intel_gt_pm_debugfs_forcewake_user_release(struct intel_gt *gt) 36 { 37 if (GRAPHICS_VER(gt->i915) >= 6) 38 intel_uncore_forcewake_user_put(gt->uncore); 39 intel_gt_pm_put(gt); 40 atomic_dec(>->user_wakeref); 41 42 return 0; 43 } 44 45 static int forcewake_user_open(struct inode *inode, struct file *file) 46 { 47 struct intel_gt *gt = inode->i_private; 48 49 return intel_gt_pm_debugfs_forcewake_user_open(gt); 50 } 51 52 static int forcewake_user_release(struct inode *inode, struct file *file) 53 { 54 struct intel_gt *gt = inode->i_private; 55 56 return intel_gt_pm_debugfs_forcewake_user_release(gt); 57 } 58 59 static const struct file_operations forcewake_user_fops = { 60 .owner = THIS_MODULE, 61 .open = forcewake_user_open, 62 .release = forcewake_user_release, 63 }; 64 65 static int fw_domains_show(struct seq_file *m, void *data) 66 { 67 struct intel_gt *gt = m->private; 68 struct intel_uncore *uncore = gt->uncore; 69 struct intel_uncore_forcewake_domain *fw_domain; 70 unsigned int tmp; 71 72 seq_printf(m, "user.bypass_count = %u\n", 73 uncore->user_forcewake_count); 74 75 for_each_fw_domain(fw_domain, uncore, tmp) 76 seq_printf(m, "%s.wake_count = %u\n", 77 intel_uncore_forcewake_domain_to_str(fw_domain->id), 78 READ_ONCE(fw_domain->wake_count)); 79 80 return 0; 81 } 82 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains); 83 84 static void print_rc6_res(struct seq_file *m, 85 const char *title, 86 const i915_reg_t reg) 87 { 88 struct intel_gt *gt = m->private; 89 intel_wakeref_t wakeref; 90 91 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 92 seq_printf(m, "%s %u (%llu us)\n", title, 93 intel_uncore_read(gt->uncore, reg), 94 intel_rc6_residency_us(>->rc6, reg)); 95 } 96 97 static int vlv_drpc(struct seq_file *m) 98 { 99 struct intel_gt *gt = m->private; 100 struct intel_uncore *uncore = gt->uncore; 101 u32 rcctl1, pw_status; 102 103 pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS); 104 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); 105 106 seq_printf(m, "RC6 Enabled: %s\n", 107 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | 108 GEN6_RC_CTL_EI_MODE(1)))); 109 seq_printf(m, "Render Power Well: %s\n", 110 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); 111 seq_printf(m, "Media Power Well: %s\n", 112 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); 113 114 print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6); 115 print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); 116 117 return fw_domains_show(m, NULL); 118 } 119 120 static int gen6_drpc(struct seq_file *m) 121 { 122 struct intel_gt *gt = m->private; 123 struct drm_i915_private *i915 = gt->i915; 124 struct intel_uncore *uncore = gt->uncore; 125 u32 gt_core_status, rcctl1, rc6vids = 0; 126 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; 127 128 gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS); 129 130 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); 131 if (GRAPHICS_VER(i915) >= 9) { 132 gen9_powergate_enable = 133 intel_uncore_read(uncore, GEN9_PG_ENABLE); 134 gen9_powergate_status = 135 intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS); 136 } 137 138 if (GRAPHICS_VER(i915) <= 7) 139 snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL); 140 141 seq_printf(m, "RC1e Enabled: %s\n", 142 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); 143 seq_printf(m, "RC6 Enabled: %s\n", 144 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 145 if (GRAPHICS_VER(i915) >= 9) { 146 seq_printf(m, "Render Well Gating Enabled: %s\n", 147 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); 148 seq_printf(m, "Media Well Gating Enabled: %s\n", 149 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); 150 } 151 seq_printf(m, "Deep RC6 Enabled: %s\n", 152 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); 153 seq_printf(m, "Deepest RC6 Enabled: %s\n", 154 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); 155 seq_puts(m, "Current RC state: "); 156 switch (gt_core_status & GEN6_RCn_MASK) { 157 case GEN6_RC0: 158 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) 159 seq_puts(m, "Core Power Down\n"); 160 else 161 seq_puts(m, "on\n"); 162 break; 163 case GEN6_RC3: 164 seq_puts(m, "RC3\n"); 165 break; 166 case GEN6_RC6: 167 seq_puts(m, "RC6\n"); 168 break; 169 case GEN6_RC7: 170 seq_puts(m, "RC7\n"); 171 break; 172 default: 173 seq_puts(m, "Unknown\n"); 174 break; 175 } 176 177 seq_printf(m, "Core Power Down: %s\n", 178 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); 179 if (GRAPHICS_VER(i915) >= 9) { 180 seq_printf(m, "Render Power Well: %s\n", 181 (gen9_powergate_status & 182 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); 183 seq_printf(m, "Media Power Well: %s\n", 184 (gen9_powergate_status & 185 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); 186 } 187 188 /* Not exactly sure what this is */ 189 print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", 190 GEN6_GT_GFX_RC6_LOCKED); 191 print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); 192 print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); 193 print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); 194 195 if (GRAPHICS_VER(i915) <= 7) { 196 seq_printf(m, "RC6 voltage: %dmV\n", 197 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); 198 seq_printf(m, "RC6+ voltage: %dmV\n", 199 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); 200 seq_printf(m, "RC6++ voltage: %dmV\n", 201 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); 202 } 203 204 return fw_domains_show(m, NULL); 205 } 206 207 static int ilk_drpc(struct seq_file *m) 208 { 209 struct intel_gt *gt = m->private; 210 struct intel_uncore *uncore = gt->uncore; 211 u32 rgvmodectl, rstdbyctl; 212 u16 crstandvid; 213 214 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); 215 rstdbyctl = intel_uncore_read(uncore, RSTDBYCTL); 216 crstandvid = intel_uncore_read16(uncore, CRSTANDVID); 217 218 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); 219 seq_printf(m, "Boost freq: %d\n", 220 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> 221 MEMMODE_BOOST_FREQ_SHIFT); 222 seq_printf(m, "HW control enabled: %s\n", 223 yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); 224 seq_printf(m, "SW control enabled: %s\n", 225 yesno(rgvmodectl & MEMMODE_SWMODE_EN)); 226 seq_printf(m, "Gated voltage change: %s\n", 227 yesno(rgvmodectl & MEMMODE_RCLK_GATE)); 228 seq_printf(m, "Starting frequency: P%d\n", 229 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); 230 seq_printf(m, "Max P-state: P%d\n", 231 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); 232 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); 233 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); 234 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); 235 seq_printf(m, "Render standby enabled: %s\n", 236 yesno(!(rstdbyctl & RCX_SW_EXIT))); 237 seq_puts(m, "Current RS state: "); 238 switch (rstdbyctl & RSX_STATUS_MASK) { 239 case RSX_STATUS_ON: 240 seq_puts(m, "on\n"); 241 break; 242 case RSX_STATUS_RC1: 243 seq_puts(m, "RC1\n"); 244 break; 245 case RSX_STATUS_RC1E: 246 seq_puts(m, "RC1E\n"); 247 break; 248 case RSX_STATUS_RS1: 249 seq_puts(m, "RS1\n"); 250 break; 251 case RSX_STATUS_RS2: 252 seq_puts(m, "RS2 (RC6)\n"); 253 break; 254 case RSX_STATUS_RS3: 255 seq_puts(m, "RC3 (RC6+)\n"); 256 break; 257 default: 258 seq_puts(m, "unknown\n"); 259 break; 260 } 261 262 return 0; 263 } 264 265 static int drpc_show(struct seq_file *m, void *unused) 266 { 267 struct intel_gt *gt = m->private; 268 struct drm_i915_private *i915 = gt->i915; 269 intel_wakeref_t wakeref; 270 int err = -ENODEV; 271 272 with_intel_runtime_pm(gt->uncore->rpm, wakeref) { 273 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 274 err = vlv_drpc(m); 275 else if (GRAPHICS_VER(i915) >= 6) 276 err = gen6_drpc(m); 277 else 278 err = ilk_drpc(m); 279 } 280 281 return err; 282 } 283 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(drpc); 284 285 void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) 286 { 287 struct drm_i915_private *i915 = gt->i915; 288 struct intel_uncore *uncore = gt->uncore; 289 struct intel_rps *rps = >->rps; 290 intel_wakeref_t wakeref; 291 292 wakeref = intel_runtime_pm_get(uncore->rpm); 293 294 if (GRAPHICS_VER(i915) == 5) { 295 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); 296 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK); 297 298 drm_printf(p, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 299 drm_printf(p, "Requested VID: %d\n", rgvswctl & 0x3f); 300 drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 301 MEMSTAT_VID_SHIFT); 302 drm_printf(p, "Current P-state: %d\n", 303 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); 304 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 305 u32 rpmodectl, freq_sts; 306 307 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL); 308 drm_printf(p, "Video Turbo Mode: %s\n", 309 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); 310 drm_printf(p, "HW control enabled: %s\n", 311 yesno(rpmodectl & GEN6_RP_ENABLE)); 312 drm_printf(p, "SW control enabled: %s\n", 313 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == 314 GEN6_RP_MEDIA_SW_MODE)); 315 316 vlv_punit_get(i915); 317 freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 318 vlv_punit_put(i915); 319 320 drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); 321 drm_printf(p, "DDR freq: %d MHz\n", i915->mem_freq); 322 323 drm_printf(p, "actual GPU freq: %d MHz\n", 324 intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); 325 326 drm_printf(p, "current GPU freq: %d MHz\n", 327 intel_gpu_freq(rps, rps->cur_freq)); 328 329 drm_printf(p, "max GPU freq: %d MHz\n", 330 intel_gpu_freq(rps, rps->max_freq)); 331 332 drm_printf(p, "min GPU freq: %d MHz\n", 333 intel_gpu_freq(rps, rps->min_freq)); 334 335 drm_printf(p, "idle GPU freq: %d MHz\n", 336 intel_gpu_freq(rps, rps->idle_freq)); 337 338 drm_printf(p, "efficient (RPe) frequency: %d MHz\n", 339 intel_gpu_freq(rps, rps->efficient_freq)); 340 } else if (GRAPHICS_VER(i915) >= 6) { 341 u32 rp_state_limits; 342 u32 gt_perf_status; 343 u32 rp_state_cap; 344 u32 rpmodectl, rpinclimit, rpdeclimit; 345 u32 rpstat, cagf, reqf; 346 u32 rpcurupei, rpcurup, rpprevup; 347 u32 rpcurdownei, rpcurdown, rpprevdown; 348 u32 rpupei, rpupt, rpdownei, rpdownt; 349 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; 350 int max_freq; 351 352 rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS); 353 rp_state_cap = intel_rps_read_state_cap(rps); 354 if (IS_GEN9_LP(i915)) 355 gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS); 356 else 357 gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS); 358 359 /* RPSTAT1 is in the GT power well */ 360 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 361 362 reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ); 363 if (GRAPHICS_VER(i915) >= 9) { 364 reqf >>= 23; 365 } else { 366 reqf &= ~GEN6_TURBO_DISABLE; 367 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 368 reqf >>= 24; 369 else 370 reqf >>= 25; 371 } 372 reqf = intel_gpu_freq(rps, reqf); 373 374 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL); 375 rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); 376 rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); 377 378 rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1); 379 rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; 380 rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; 381 rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; 382 rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; 383 rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; 384 rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; 385 386 rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI); 387 rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); 388 389 rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI); 390 rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); 391 392 cagf = intel_rps_read_actual_frequency(rps); 393 394 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 395 396 if (GRAPHICS_VER(i915) >= 11) { 397 pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE); 398 pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK); 399 /* 400 * The equivalent to the PM ISR & IIR cannot be read 401 * without affecting the current state of the system 402 */ 403 pm_isr = 0; 404 pm_iir = 0; 405 } else if (GRAPHICS_VER(i915) >= 8) { 406 pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2)); 407 pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2)); 408 pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2)); 409 pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2)); 410 } else { 411 pm_ier = intel_uncore_read(uncore, GEN6_PMIER); 412 pm_imr = intel_uncore_read(uncore, GEN6_PMIMR); 413 pm_isr = intel_uncore_read(uncore, GEN6_PMISR); 414 pm_iir = intel_uncore_read(uncore, GEN6_PMIIR); 415 } 416 pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK); 417 418 drm_printf(p, "Video Turbo Mode: %s\n", 419 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); 420 drm_printf(p, "HW control enabled: %s\n", 421 yesno(rpmodectl & GEN6_RP_ENABLE)); 422 drm_printf(p, "SW control enabled: %s\n", 423 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == 424 GEN6_RP_MEDIA_SW_MODE)); 425 426 drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", 427 pm_ier, pm_imr, pm_mask); 428 if (GRAPHICS_VER(i915) <= 10) 429 drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n", 430 pm_isr, pm_iir); 431 drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", 432 rps->pm_intrmsk_mbz); 433 drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 434 drm_printf(p, "Render p-state ratio: %d\n", 435 (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8); 436 drm_printf(p, "Render p-state VID: %d\n", 437 gt_perf_status & 0xff); 438 drm_printf(p, "Render p-state limit: %d\n", 439 rp_state_limits & 0xff); 440 drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat); 441 drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl); 442 drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit); 443 drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit); 444 drm_printf(p, "RPNSWREQ: %dMHz\n", reqf); 445 drm_printf(p, "CAGF: %dMHz\n", cagf); 446 drm_printf(p, "RP CUR UP EI: %d (%lldns)\n", 447 rpcurupei, 448 intel_gt_pm_interval_to_ns(gt, rpcurupei)); 449 drm_printf(p, "RP CUR UP: %d (%lldns)\n", 450 rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup)); 451 drm_printf(p, "RP PREV UP: %d (%lldns)\n", 452 rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup)); 453 drm_printf(p, "Up threshold: %d%%\n", 454 rps->power.up_threshold); 455 drm_printf(p, "RP UP EI: %d (%lldns)\n", 456 rpupei, intel_gt_pm_interval_to_ns(gt, rpupei)); 457 drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n", 458 rpupt, intel_gt_pm_interval_to_ns(gt, rpupt)); 459 460 drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n", 461 rpcurdownei, 462 intel_gt_pm_interval_to_ns(gt, rpcurdownei)); 463 drm_printf(p, "RP CUR DOWN: %d (%lldns)\n", 464 rpcurdown, 465 intel_gt_pm_interval_to_ns(gt, rpcurdown)); 466 drm_printf(p, "RP PREV DOWN: %d (%lldns)\n", 467 rpprevdown, 468 intel_gt_pm_interval_to_ns(gt, rpprevdown)); 469 drm_printf(p, "Down threshold: %d%%\n", 470 rps->power.down_threshold); 471 drm_printf(p, "RP DOWN EI: %d (%lldns)\n", 472 rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei)); 473 drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n", 474 rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt)); 475 476 max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 : 477 rp_state_cap >> 16) & 0xff; 478 max_freq *= (IS_GEN9_BC(i915) || 479 GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); 480 drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", 481 intel_gpu_freq(rps, max_freq)); 482 483 max_freq = (rp_state_cap & 0xff00) >> 8; 484 max_freq *= (IS_GEN9_BC(i915) || 485 GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); 486 drm_printf(p, "Nominal (RP1) frequency: %dMHz\n", 487 intel_gpu_freq(rps, max_freq)); 488 489 max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 : 490 rp_state_cap >> 0) & 0xff; 491 max_freq *= (IS_GEN9_BC(i915) || 492 GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); 493 drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n", 494 intel_gpu_freq(rps, max_freq)); 495 drm_printf(p, "Max overclocked frequency: %dMHz\n", 496 intel_gpu_freq(rps, rps->max_freq)); 497 498 drm_printf(p, "Current freq: %d MHz\n", 499 intel_gpu_freq(rps, rps->cur_freq)); 500 drm_printf(p, "Actual freq: %d MHz\n", cagf); 501 drm_printf(p, "Idle freq: %d MHz\n", 502 intel_gpu_freq(rps, rps->idle_freq)); 503 drm_printf(p, "Min freq: %d MHz\n", 504 intel_gpu_freq(rps, rps->min_freq)); 505 drm_printf(p, "Boost freq: %d MHz\n", 506 intel_gpu_freq(rps, rps->boost_freq)); 507 drm_printf(p, "Max freq: %d MHz\n", 508 intel_gpu_freq(rps, rps->max_freq)); 509 drm_printf(p, 510 "efficient (RPe) frequency: %d MHz\n", 511 intel_gpu_freq(rps, rps->efficient_freq)); 512 } else { 513 drm_puts(p, "no P-state info available\n"); 514 } 515 516 drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk); 517 drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq); 518 drm_printf(p, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); 519 520 intel_runtime_pm_put(uncore->rpm, wakeref); 521 } 522 523 static int frequency_show(struct seq_file *m, void *unused) 524 { 525 struct intel_gt *gt = m->private; 526 struct drm_printer p = drm_seq_file_printer(m); 527 528 intel_gt_pm_frequency_dump(gt, &p); 529 530 return 0; 531 } 532 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(frequency); 533 534 static int llc_show(struct seq_file *m, void *data) 535 { 536 struct intel_gt *gt = m->private; 537 struct drm_i915_private *i915 = gt->i915; 538 const bool edram = GRAPHICS_VER(i915) > 8; 539 struct intel_rps *rps = >->rps; 540 unsigned int max_gpu_freq, min_gpu_freq; 541 intel_wakeref_t wakeref; 542 int gpu_freq, ia_freq; 543 544 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(i915))); 545 seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC", 546 i915->edram_size_mb); 547 548 min_gpu_freq = rps->min_freq; 549 max_gpu_freq = rps->max_freq; 550 if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { 551 /* Convert GT frequency to 50 HZ units */ 552 min_gpu_freq /= GEN9_FREQ_SCALER; 553 max_gpu_freq /= GEN9_FREQ_SCALER; 554 } 555 556 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); 557 558 wakeref = intel_runtime_pm_get(gt->uncore->rpm); 559 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { 560 ia_freq = gpu_freq; 561 snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE, 562 &ia_freq, NULL); 563 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", 564 intel_gpu_freq(rps, 565 (gpu_freq * 566 (IS_GEN9_BC(i915) || 567 GRAPHICS_VER(i915) >= 11 ? 568 GEN9_FREQ_SCALER : 1))), 569 ((ia_freq >> 0) & 0xff) * 100, 570 ((ia_freq >> 8) & 0xff) * 100); 571 } 572 intel_runtime_pm_put(gt->uncore->rpm, wakeref); 573 574 return 0; 575 } 576 577 static bool llc_eval(void *data) 578 { 579 struct intel_gt *gt = data; 580 581 return HAS_LLC(gt->i915); 582 } 583 584 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(llc); 585 586 static const char *rps_power_to_str(unsigned int power) 587 { 588 static const char * const strings[] = { 589 [LOW_POWER] = "low power", 590 [BETWEEN] = "mixed", 591 [HIGH_POWER] = "high power", 592 }; 593 594 if (power >= ARRAY_SIZE(strings) || !strings[power]) 595 return "unknown"; 596 597 return strings[power]; 598 } 599 600 static int rps_boost_show(struct seq_file *m, void *data) 601 { 602 struct intel_gt *gt = m->private; 603 struct drm_i915_private *i915 = gt->i915; 604 struct intel_rps *rps = >->rps; 605 606 seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps))); 607 seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps))); 608 seq_printf(m, "GPU busy? %s, %llums\n", 609 yesno(gt->awake), 610 ktime_to_ms(intel_gt_get_awake_time(gt))); 611 seq_printf(m, "Boosts outstanding? %d\n", 612 atomic_read(&rps->num_waiters)); 613 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 614 seq_printf(m, "Frequency requested %d, actual %d\n", 615 intel_gpu_freq(rps, rps->cur_freq), 616 intel_rps_read_actual_frequency(rps)); 617 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 618 intel_gpu_freq(rps, rps->min_freq), 619 intel_gpu_freq(rps, rps->min_freq_softlimit), 620 intel_gpu_freq(rps, rps->max_freq_softlimit), 621 intel_gpu_freq(rps, rps->max_freq)); 622 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 623 intel_gpu_freq(rps, rps->idle_freq), 624 intel_gpu_freq(rps, rps->efficient_freq), 625 intel_gpu_freq(rps, rps->boost_freq)); 626 627 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 628 629 if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) { 630 struct intel_uncore *uncore = gt->uncore; 631 u32 rpup, rpupei; 632 u32 rpdown, rpdownei; 633 634 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 635 rpup = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; 636 rpupei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; 637 rpdown = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; 638 rpdownei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; 639 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 640 641 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", 642 rps_power_to_str(rps->power.mode)); 643 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", 644 rpup && rpupei ? 100 * rpup / rpupei : 0, 645 rps->power.up_threshold); 646 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", 647 rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, 648 rps->power.down_threshold); 649 } else { 650 seq_puts(m, "\nRPS Autotuning inactive\n"); 651 } 652 653 return 0; 654 } 655 656 static bool rps_eval(void *data) 657 { 658 struct intel_gt *gt = data; 659 660 return HAS_RPS(gt->i915); 661 } 662 663 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost); 664 665 void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root) 666 { 667 static const struct intel_gt_debugfs_file files[] = { 668 { "drpc", &drpc_fops, NULL }, 669 { "frequency", &frequency_fops, NULL }, 670 { "forcewake", &fw_domains_fops, NULL }, 671 { "forcewake_user", &forcewake_user_fops, NULL}, 672 { "llc", &llc_fops, llc_eval }, 673 { "rps_boost", &rps_boost_fops, rps_eval }, 674 }; 675 676 intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); 677 } 678