1 // SPDX-License-Identifier: MIT 2 3 /* 4 * Copyright © 2019 Intel Corporation 5 */ 6 7 #include <linux/seq_file.h> 8 9 #include "i915_drv.h" 10 #include "i915_reg.h" 11 #include "intel_gt.h" 12 #include "intel_gt_clock_utils.h" 13 #include "intel_gt_debugfs.h" 14 #include "intel_gt_pm.h" 15 #include "intel_gt_pm_debugfs.h" 16 #include "intel_gt_regs.h" 17 #include "intel_llc.h" 18 #include "intel_mchbar_regs.h" 19 #include "intel_pcode.h" 20 #include "intel_rc6.h" 21 #include "intel_rps.h" 22 #include "intel_runtime_pm.h" 23 #include "intel_uncore.h" 24 #include "vlv_sideband.h" 25 26 int intel_gt_pm_debugfs_forcewake_user_open(struct intel_gt *gt) 27 { 28 atomic_inc(>->user_wakeref); 29 intel_gt_pm_get(gt); 30 if (GRAPHICS_VER(gt->i915) >= 6) 31 intel_uncore_forcewake_user_get(gt->uncore); 32 33 return 0; 34 } 35 36 int intel_gt_pm_debugfs_forcewake_user_release(struct intel_gt *gt) 37 { 38 if (GRAPHICS_VER(gt->i915) >= 6) 39 intel_uncore_forcewake_user_put(gt->uncore); 40 intel_gt_pm_put(gt); 41 atomic_dec(>->user_wakeref); 42 43 return 0; 44 } 45 46 static int forcewake_user_open(struct inode *inode, struct file *file) 47 { 48 struct intel_gt *gt = inode->i_private; 49 50 return intel_gt_pm_debugfs_forcewake_user_open(gt); 51 } 52 53 static int forcewake_user_release(struct inode *inode, struct file *file) 54 { 55 struct intel_gt *gt = inode->i_private; 56 57 return intel_gt_pm_debugfs_forcewake_user_release(gt); 58 } 59 60 static const struct file_operations forcewake_user_fops = { 61 .owner = THIS_MODULE, 62 .open = forcewake_user_open, 63 .release = forcewake_user_release, 64 }; 65 66 static int fw_domains_show(struct seq_file *m, void *data) 67 { 68 struct intel_gt *gt = m->private; 69 struct intel_uncore *uncore = gt->uncore; 70 struct intel_uncore_forcewake_domain *fw_domain; 71 unsigned int tmp; 72 73 seq_printf(m, "user.bypass_count = %u\n", 74 uncore->user_forcewake_count); 75 76 for_each_fw_domain(fw_domain, uncore, tmp) 77 seq_printf(m, "%s.wake_count = %u\n", 78 intel_uncore_forcewake_domain_to_str(fw_domain->id), 79 READ_ONCE(fw_domain->wake_count)); 80 81 return 0; 82 } 83 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains); 84 85 static void print_rc6_res(struct seq_file *m, 86 const char *title, 87 const i915_reg_t reg) 88 { 89 struct intel_gt *gt = m->private; 90 intel_wakeref_t wakeref; 91 92 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 93 seq_printf(m, "%s %u (%llu us)\n", title, 94 intel_uncore_read(gt->uncore, reg), 95 intel_rc6_residency_us(>->rc6, reg)); 96 } 97 98 static int vlv_drpc(struct seq_file *m) 99 { 100 struct intel_gt *gt = m->private; 101 struct intel_uncore *uncore = gt->uncore; 102 u32 rcctl1, pw_status; 103 104 pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS); 105 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); 106 107 seq_printf(m, "RC6 Enabled: %s\n", 108 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | 109 GEN6_RC_CTL_EI_MODE(1)))); 110 seq_printf(m, "Render Power Well: %s\n", 111 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); 112 seq_printf(m, "Media Power Well: %s\n", 113 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); 114 115 print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6); 116 print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); 117 118 return fw_domains_show(m, NULL); 119 } 120 121 static int gen6_drpc(struct seq_file *m) 122 { 123 struct intel_gt *gt = m->private; 124 struct drm_i915_private *i915 = gt->i915; 125 struct intel_uncore *uncore = gt->uncore; 126 u32 gt_core_status, rcctl1, rc6vids = 0; 127 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; 128 129 gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS); 130 131 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); 132 if (GRAPHICS_VER(i915) >= 9) { 133 gen9_powergate_enable = 134 intel_uncore_read(uncore, GEN9_PG_ENABLE); 135 gen9_powergate_status = 136 intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS); 137 } 138 139 if (GRAPHICS_VER(i915) <= 7) 140 snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL); 141 142 seq_printf(m, "RC1e Enabled: %s\n", 143 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); 144 seq_printf(m, "RC6 Enabled: %s\n", 145 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 146 if (GRAPHICS_VER(i915) >= 9) { 147 seq_printf(m, "Render Well Gating Enabled: %s\n", 148 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); 149 seq_printf(m, "Media Well Gating Enabled: %s\n", 150 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); 151 } 152 seq_printf(m, "Deep RC6 Enabled: %s\n", 153 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); 154 seq_printf(m, "Deepest RC6 Enabled: %s\n", 155 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); 156 seq_puts(m, "Current RC state: "); 157 switch (gt_core_status & GEN6_RCn_MASK) { 158 case GEN6_RC0: 159 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) 160 seq_puts(m, "Core Power Down\n"); 161 else 162 seq_puts(m, "on\n"); 163 break; 164 case GEN6_RC3: 165 seq_puts(m, "RC3\n"); 166 break; 167 case GEN6_RC6: 168 seq_puts(m, "RC6\n"); 169 break; 170 case GEN6_RC7: 171 seq_puts(m, "RC7\n"); 172 break; 173 default: 174 seq_puts(m, "Unknown\n"); 175 break; 176 } 177 178 seq_printf(m, "Core Power Down: %s\n", 179 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); 180 if (GRAPHICS_VER(i915) >= 9) { 181 seq_printf(m, "Render Power Well: %s\n", 182 (gen9_powergate_status & 183 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); 184 seq_printf(m, "Media Power Well: %s\n", 185 (gen9_powergate_status & 186 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); 187 } 188 189 /* Not exactly sure what this is */ 190 print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", 191 GEN6_GT_GFX_RC6_LOCKED); 192 print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); 193 print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); 194 print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); 195 196 if (GRAPHICS_VER(i915) <= 7) { 197 seq_printf(m, "RC6 voltage: %dmV\n", 198 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); 199 seq_printf(m, "RC6+ voltage: %dmV\n", 200 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); 201 seq_printf(m, "RC6++ voltage: %dmV\n", 202 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); 203 } 204 205 return fw_domains_show(m, NULL); 206 } 207 208 static int ilk_drpc(struct seq_file *m) 209 { 210 struct intel_gt *gt = m->private; 211 struct intel_uncore *uncore = gt->uncore; 212 u32 rgvmodectl, rstdbyctl; 213 u16 crstandvid; 214 215 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); 216 rstdbyctl = intel_uncore_read(uncore, RSTDBYCTL); 217 crstandvid = intel_uncore_read16(uncore, CRSTANDVID); 218 219 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); 220 seq_printf(m, "Boost freq: %d\n", 221 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> 222 MEMMODE_BOOST_FREQ_SHIFT); 223 seq_printf(m, "HW control enabled: %s\n", 224 yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); 225 seq_printf(m, "SW control enabled: %s\n", 226 yesno(rgvmodectl & MEMMODE_SWMODE_EN)); 227 seq_printf(m, "Gated voltage change: %s\n", 228 yesno(rgvmodectl & MEMMODE_RCLK_GATE)); 229 seq_printf(m, "Starting frequency: P%d\n", 230 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); 231 seq_printf(m, "Max P-state: P%d\n", 232 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); 233 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); 234 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); 235 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); 236 seq_printf(m, "Render standby enabled: %s\n", 237 yesno(!(rstdbyctl & RCX_SW_EXIT))); 238 seq_puts(m, "Current RS state: "); 239 switch (rstdbyctl & RSX_STATUS_MASK) { 240 case RSX_STATUS_ON: 241 seq_puts(m, "on\n"); 242 break; 243 case RSX_STATUS_RC1: 244 seq_puts(m, "RC1\n"); 245 break; 246 case RSX_STATUS_RC1E: 247 seq_puts(m, "RC1E\n"); 248 break; 249 case RSX_STATUS_RS1: 250 seq_puts(m, "RS1\n"); 251 break; 252 case RSX_STATUS_RS2: 253 seq_puts(m, "RS2 (RC6)\n"); 254 break; 255 case RSX_STATUS_RS3: 256 seq_puts(m, "RC3 (RC6+)\n"); 257 break; 258 default: 259 seq_puts(m, "unknown\n"); 260 break; 261 } 262 263 return 0; 264 } 265 266 static int drpc_show(struct seq_file *m, void *unused) 267 { 268 struct intel_gt *gt = m->private; 269 struct drm_i915_private *i915 = gt->i915; 270 intel_wakeref_t wakeref; 271 int err = -ENODEV; 272 273 with_intel_runtime_pm(gt->uncore->rpm, wakeref) { 274 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 275 err = vlv_drpc(m); 276 else if (GRAPHICS_VER(i915) >= 6) 277 err = gen6_drpc(m); 278 else 279 err = ilk_drpc(m); 280 } 281 282 return err; 283 } 284 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(drpc); 285 286 void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) 287 { 288 struct drm_i915_private *i915 = gt->i915; 289 struct intel_uncore *uncore = gt->uncore; 290 struct intel_rps *rps = >->rps; 291 intel_wakeref_t wakeref; 292 293 wakeref = intel_runtime_pm_get(uncore->rpm); 294 295 if (GRAPHICS_VER(i915) == 5) { 296 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); 297 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK); 298 299 drm_printf(p, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 300 drm_printf(p, "Requested VID: %d\n", rgvswctl & 0x3f); 301 drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 302 MEMSTAT_VID_SHIFT); 303 drm_printf(p, "Current P-state: %d\n", 304 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); 305 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 306 u32 rpmodectl, freq_sts; 307 308 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL); 309 drm_printf(p, "Video Turbo Mode: %s\n", 310 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); 311 drm_printf(p, "HW control enabled: %s\n", 312 yesno(rpmodectl & GEN6_RP_ENABLE)); 313 drm_printf(p, "SW control enabled: %s\n", 314 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == 315 GEN6_RP_MEDIA_SW_MODE)); 316 317 vlv_punit_get(i915); 318 freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 319 vlv_punit_put(i915); 320 321 drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); 322 drm_printf(p, "DDR freq: %d MHz\n", i915->mem_freq); 323 324 drm_printf(p, "actual GPU freq: %d MHz\n", 325 intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); 326 327 drm_printf(p, "current GPU freq: %d MHz\n", 328 intel_gpu_freq(rps, rps->cur_freq)); 329 330 drm_printf(p, "max GPU freq: %d MHz\n", 331 intel_gpu_freq(rps, rps->max_freq)); 332 333 drm_printf(p, "min GPU freq: %d MHz\n", 334 intel_gpu_freq(rps, rps->min_freq)); 335 336 drm_printf(p, "idle GPU freq: %d MHz\n", 337 intel_gpu_freq(rps, rps->idle_freq)); 338 339 drm_printf(p, "efficient (RPe) frequency: %d MHz\n", 340 intel_gpu_freq(rps, rps->efficient_freq)); 341 } else if (GRAPHICS_VER(i915) >= 6) { 342 u32 rp_state_limits; 343 u32 gt_perf_status; 344 u32 rp_state_cap; 345 u32 rpmodectl, rpinclimit, rpdeclimit; 346 u32 rpstat, cagf, reqf; 347 u32 rpcurupei, rpcurup, rpprevup; 348 u32 rpcurdownei, rpcurdown, rpprevdown; 349 u32 rpupei, rpupt, rpdownei, rpdownt; 350 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; 351 int max_freq; 352 353 rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS); 354 rp_state_cap = intel_rps_read_state_cap(rps); 355 if (IS_GEN9_LP(i915)) 356 gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS); 357 else 358 gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS); 359 360 /* RPSTAT1 is in the GT power well */ 361 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 362 363 reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ); 364 if (GRAPHICS_VER(i915) >= 9) { 365 reqf >>= 23; 366 } else { 367 reqf &= ~GEN6_TURBO_DISABLE; 368 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 369 reqf >>= 24; 370 else 371 reqf >>= 25; 372 } 373 reqf = intel_gpu_freq(rps, reqf); 374 375 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL); 376 rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); 377 rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); 378 379 rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1); 380 rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; 381 rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; 382 rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; 383 rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; 384 rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; 385 rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; 386 387 rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI); 388 rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); 389 390 rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI); 391 rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); 392 393 cagf = intel_rps_read_actual_frequency(rps); 394 395 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 396 397 if (GRAPHICS_VER(i915) >= 11) { 398 pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE); 399 pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK); 400 /* 401 * The equivalent to the PM ISR & IIR cannot be read 402 * without affecting the current state of the system 403 */ 404 pm_isr = 0; 405 pm_iir = 0; 406 } else if (GRAPHICS_VER(i915) >= 8) { 407 pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2)); 408 pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2)); 409 pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2)); 410 pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2)); 411 } else { 412 pm_ier = intel_uncore_read(uncore, GEN6_PMIER); 413 pm_imr = intel_uncore_read(uncore, GEN6_PMIMR); 414 pm_isr = intel_uncore_read(uncore, GEN6_PMISR); 415 pm_iir = intel_uncore_read(uncore, GEN6_PMIIR); 416 } 417 pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK); 418 419 drm_printf(p, "Video Turbo Mode: %s\n", 420 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); 421 drm_printf(p, "HW control enabled: %s\n", 422 yesno(rpmodectl & GEN6_RP_ENABLE)); 423 drm_printf(p, "SW control enabled: %s\n", 424 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == 425 GEN6_RP_MEDIA_SW_MODE)); 426 427 drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", 428 pm_ier, pm_imr, pm_mask); 429 if (GRAPHICS_VER(i915) <= 10) 430 drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n", 431 pm_isr, pm_iir); 432 drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", 433 rps->pm_intrmsk_mbz); 434 drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 435 drm_printf(p, "Render p-state ratio: %d\n", 436 (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8); 437 drm_printf(p, "Render p-state VID: %d\n", 438 gt_perf_status & 0xff); 439 drm_printf(p, "Render p-state limit: %d\n", 440 rp_state_limits & 0xff); 441 drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat); 442 drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl); 443 drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit); 444 drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit); 445 drm_printf(p, "RPNSWREQ: %dMHz\n", reqf); 446 drm_printf(p, "CAGF: %dMHz\n", cagf); 447 drm_printf(p, "RP CUR UP EI: %d (%lldns)\n", 448 rpcurupei, 449 intel_gt_pm_interval_to_ns(gt, rpcurupei)); 450 drm_printf(p, "RP CUR UP: %d (%lldns)\n", 451 rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup)); 452 drm_printf(p, "RP PREV UP: %d (%lldns)\n", 453 rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup)); 454 drm_printf(p, "Up threshold: %d%%\n", 455 rps->power.up_threshold); 456 drm_printf(p, "RP UP EI: %d (%lldns)\n", 457 rpupei, intel_gt_pm_interval_to_ns(gt, rpupei)); 458 drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n", 459 rpupt, intel_gt_pm_interval_to_ns(gt, rpupt)); 460 461 drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n", 462 rpcurdownei, 463 intel_gt_pm_interval_to_ns(gt, rpcurdownei)); 464 drm_printf(p, "RP CUR DOWN: %d (%lldns)\n", 465 rpcurdown, 466 intel_gt_pm_interval_to_ns(gt, rpcurdown)); 467 drm_printf(p, "RP PREV DOWN: %d (%lldns)\n", 468 rpprevdown, 469 intel_gt_pm_interval_to_ns(gt, rpprevdown)); 470 drm_printf(p, "Down threshold: %d%%\n", 471 rps->power.down_threshold); 472 drm_printf(p, "RP DOWN EI: %d (%lldns)\n", 473 rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei)); 474 drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n", 475 rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt)); 476 477 max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 : 478 rp_state_cap >> 16) & 0xff; 479 max_freq *= (IS_GEN9_BC(i915) || 480 GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); 481 drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", 482 intel_gpu_freq(rps, max_freq)); 483 484 max_freq = (rp_state_cap & 0xff00) >> 8; 485 max_freq *= (IS_GEN9_BC(i915) || 486 GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); 487 drm_printf(p, "Nominal (RP1) frequency: %dMHz\n", 488 intel_gpu_freq(rps, max_freq)); 489 490 max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 : 491 rp_state_cap >> 0) & 0xff; 492 max_freq *= (IS_GEN9_BC(i915) || 493 GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); 494 drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n", 495 intel_gpu_freq(rps, max_freq)); 496 drm_printf(p, "Max overclocked frequency: %dMHz\n", 497 intel_gpu_freq(rps, rps->max_freq)); 498 499 drm_printf(p, "Current freq: %d MHz\n", 500 intel_gpu_freq(rps, rps->cur_freq)); 501 drm_printf(p, "Actual freq: %d MHz\n", cagf); 502 drm_printf(p, "Idle freq: %d MHz\n", 503 intel_gpu_freq(rps, rps->idle_freq)); 504 drm_printf(p, "Min freq: %d MHz\n", 505 intel_gpu_freq(rps, rps->min_freq)); 506 drm_printf(p, "Boost freq: %d MHz\n", 507 intel_gpu_freq(rps, rps->boost_freq)); 508 drm_printf(p, "Max freq: %d MHz\n", 509 intel_gpu_freq(rps, rps->max_freq)); 510 drm_printf(p, 511 "efficient (RPe) frequency: %d MHz\n", 512 intel_gpu_freq(rps, rps->efficient_freq)); 513 } else { 514 drm_puts(p, "no P-state info available\n"); 515 } 516 517 drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk); 518 drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq); 519 drm_printf(p, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); 520 521 intel_runtime_pm_put(uncore->rpm, wakeref); 522 } 523 524 static int frequency_show(struct seq_file *m, void *unused) 525 { 526 struct intel_gt *gt = m->private; 527 struct drm_printer p = drm_seq_file_printer(m); 528 529 intel_gt_pm_frequency_dump(gt, &p); 530 531 return 0; 532 } 533 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(frequency); 534 535 static int llc_show(struct seq_file *m, void *data) 536 { 537 struct intel_gt *gt = m->private; 538 struct drm_i915_private *i915 = gt->i915; 539 const bool edram = GRAPHICS_VER(i915) > 8; 540 struct intel_rps *rps = >->rps; 541 unsigned int max_gpu_freq, min_gpu_freq; 542 intel_wakeref_t wakeref; 543 int gpu_freq, ia_freq; 544 545 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(i915))); 546 seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC", 547 i915->edram_size_mb); 548 549 min_gpu_freq = rps->min_freq; 550 max_gpu_freq = rps->max_freq; 551 if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { 552 /* Convert GT frequency to 50 HZ units */ 553 min_gpu_freq /= GEN9_FREQ_SCALER; 554 max_gpu_freq /= GEN9_FREQ_SCALER; 555 } 556 557 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); 558 559 wakeref = intel_runtime_pm_get(gt->uncore->rpm); 560 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { 561 ia_freq = gpu_freq; 562 snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE, 563 &ia_freq, NULL); 564 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", 565 intel_gpu_freq(rps, 566 (gpu_freq * 567 (IS_GEN9_BC(i915) || 568 GRAPHICS_VER(i915) >= 11 ? 569 GEN9_FREQ_SCALER : 1))), 570 ((ia_freq >> 0) & 0xff) * 100, 571 ((ia_freq >> 8) & 0xff) * 100); 572 } 573 intel_runtime_pm_put(gt->uncore->rpm, wakeref); 574 575 return 0; 576 } 577 578 static bool llc_eval(void *data) 579 { 580 struct intel_gt *gt = data; 581 582 return HAS_LLC(gt->i915); 583 } 584 585 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(llc); 586 587 static const char *rps_power_to_str(unsigned int power) 588 { 589 static const char * const strings[] = { 590 [LOW_POWER] = "low power", 591 [BETWEEN] = "mixed", 592 [HIGH_POWER] = "high power", 593 }; 594 595 if (power >= ARRAY_SIZE(strings) || !strings[power]) 596 return "unknown"; 597 598 return strings[power]; 599 } 600 601 static int rps_boost_show(struct seq_file *m, void *data) 602 { 603 struct intel_gt *gt = m->private; 604 struct drm_i915_private *i915 = gt->i915; 605 struct intel_rps *rps = >->rps; 606 607 seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps))); 608 seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps))); 609 seq_printf(m, "GPU busy? %s, %llums\n", 610 yesno(gt->awake), 611 ktime_to_ms(intel_gt_get_awake_time(gt))); 612 seq_printf(m, "Boosts outstanding? %d\n", 613 atomic_read(&rps->num_waiters)); 614 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 615 seq_printf(m, "Frequency requested %d, actual %d\n", 616 intel_gpu_freq(rps, rps->cur_freq), 617 intel_rps_read_actual_frequency(rps)); 618 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 619 intel_gpu_freq(rps, rps->min_freq), 620 intel_gpu_freq(rps, rps->min_freq_softlimit), 621 intel_gpu_freq(rps, rps->max_freq_softlimit), 622 intel_gpu_freq(rps, rps->max_freq)); 623 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 624 intel_gpu_freq(rps, rps->idle_freq), 625 intel_gpu_freq(rps, rps->efficient_freq), 626 intel_gpu_freq(rps, rps->boost_freq)); 627 628 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 629 630 if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) { 631 struct intel_uncore *uncore = gt->uncore; 632 u32 rpup, rpupei; 633 u32 rpdown, rpdownei; 634 635 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 636 rpup = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; 637 rpupei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; 638 rpdown = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; 639 rpdownei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; 640 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 641 642 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", 643 rps_power_to_str(rps->power.mode)); 644 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", 645 rpup && rpupei ? 100 * rpup / rpupei : 0, 646 rps->power.up_threshold); 647 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", 648 rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, 649 rps->power.down_threshold); 650 } else { 651 seq_puts(m, "\nRPS Autotuning inactive\n"); 652 } 653 654 return 0; 655 } 656 657 static bool rps_eval(void *data) 658 { 659 struct intel_gt *gt = data; 660 661 return HAS_RPS(gt->i915); 662 } 663 664 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost); 665 666 void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root) 667 { 668 static const struct intel_gt_debugfs_file files[] = { 669 { "drpc", &drpc_fops, NULL }, 670 { "frequency", &frequency_fops, NULL }, 671 { "forcewake", &fw_domains_fops, NULL }, 672 { "forcewake_user", &forcewake_user_fops, NULL}, 673 { "llc", &llc_fops, llc_eval }, 674 { "rps_boost", &rps_boost_fops, rps_eval }, 675 }; 676 677 intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); 678 } 679