1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2019 Intel Corporation 5 */ 6 7 #include "i915_drv.h" 8 #include "i915_params.h" 9 #include "intel_engine_pm.h" 10 #include "intel_gt.h" 11 #include "intel_gt_pm.h" 12 #include "intel_pm.h" 13 #include "intel_wakeref.h" 14 15 static void pm_notify(struct drm_i915_private *i915, int state) 16 { 17 blocking_notifier_call_chain(&i915->gt.pm_notifications, state, i915); 18 } 19 20 static int intel_gt_unpark(struct intel_wakeref *wf) 21 { 22 struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref); 23 struct drm_i915_private *i915 = gt->i915; 24 25 GEM_TRACE("\n"); 26 27 /* 28 * It seems that the DMC likes to transition between the DC states a lot 29 * when there are no connected displays (no active power domains) during 30 * command submission. 31 * 32 * This activity has negative impact on the performance of the chip with 33 * huge latencies observed in the interrupt handler and elsewhere. 34 * 35 * Work around it by grabbing a GT IRQ power domain whilst there is any 36 * GT activity, preventing any DC state transitions. 37 */ 38 gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ); 39 GEM_BUG_ON(!gt->awake); 40 41 intel_enable_gt_powersave(i915); 42 43 i915_update_gfx_val(i915); 44 if (INTEL_GEN(i915) >= 6) 45 gen6_rps_busy(i915); 46 47 i915_pmu_gt_unparked(i915); 48 49 intel_gt_queue_hangcheck(gt); 50 51 pm_notify(i915, INTEL_GT_UNPARK); 52 53 return 0; 54 } 55 56 void intel_gt_pm_get(struct intel_gt *gt) 57 { 58 struct intel_runtime_pm *rpm = >->i915->runtime_pm; 59 60 intel_wakeref_get(rpm, >->wakeref, intel_gt_unpark); 61 } 62 63 static int intel_gt_park(struct intel_wakeref *wf) 64 { 65 struct drm_i915_private *i915 = 66 container_of(wf, typeof(*i915), gt.wakeref); 67 intel_wakeref_t wakeref = fetch_and_zero(&i915->gt.awake); 68 69 GEM_TRACE("\n"); 70 71 pm_notify(i915, INTEL_GT_PARK); 72 73 i915_pmu_gt_parked(i915); 74 if (INTEL_GEN(i915) >= 6) 75 gen6_rps_idle(i915); 76 77 GEM_BUG_ON(!wakeref); 78 intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ, wakeref); 79 80 return 0; 81 } 82 83 void intel_gt_pm_put(struct intel_gt *gt) 84 { 85 struct intel_runtime_pm *rpm = >->i915->runtime_pm; 86 87 intel_wakeref_put(rpm, >->wakeref, intel_gt_park); 88 } 89 90 void intel_gt_pm_init_early(struct intel_gt *gt) 91 { 92 intel_wakeref_init(>->wakeref); 93 BLOCKING_INIT_NOTIFIER_HEAD(>->pm_notifications); 94 } 95 96 static bool reset_engines(struct intel_gt *gt) 97 { 98 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) 99 return false; 100 101 return __intel_gt_reset(gt, ALL_ENGINES) == 0; 102 } 103 104 /** 105 * intel_gt_sanitize: called after the GPU has lost power 106 * @gt: the i915 GT container 107 * @force: ignore a failed reset and sanitize engine state anyway 108 * 109 * Anytime we reset the GPU, either with an explicit GPU reset or through a 110 * PCI power cycle, the GPU loses state and we must reset our state tracking 111 * to match. Note that calling intel_gt_sanitize() if the GPU has not 112 * been reset results in much confusion! 113 */ 114 void intel_gt_sanitize(struct intel_gt *gt, bool force) 115 { 116 struct intel_engine_cs *engine; 117 enum intel_engine_id id; 118 119 GEM_TRACE("\n"); 120 121 intel_uc_sanitize(>->uc); 122 123 if (!reset_engines(gt) && !force) 124 return; 125 126 for_each_engine(engine, gt->i915, id) 127 __intel_engine_reset(engine, false); 128 } 129 130 int intel_gt_resume(struct intel_gt *gt) 131 { 132 struct intel_engine_cs *engine; 133 enum intel_engine_id id; 134 int err = 0; 135 136 /* 137 * After resume, we may need to poke into the pinned kernel 138 * contexts to paper over any damage caused by the sudden suspend. 139 * Only the kernel contexts should remain pinned over suspend, 140 * allowing us to fixup the user contexts on their first pin. 141 */ 142 intel_gt_pm_get(gt); 143 for_each_engine(engine, gt->i915, id) { 144 struct intel_context *ce; 145 146 intel_engine_pm_get(engine); 147 148 ce = engine->kernel_context; 149 if (ce) 150 ce->ops->reset(ce); 151 152 engine->serial++; /* kernel context lost */ 153 err = engine->resume(engine); 154 155 intel_engine_pm_put(engine); 156 if (err) { 157 dev_err(gt->i915->drm.dev, 158 "Failed to restart %s (%d)\n", 159 engine->name, err); 160 break; 161 } 162 } 163 intel_gt_pm_put(gt); 164 165 return err; 166 } 167