1e7858254SMatt Roper /* SPDX-License-Identifier: MIT */ 2e7858254SMatt Roper /* 3e7858254SMatt Roper * Copyright © 2022 Intel Corporation 4e7858254SMatt Roper */ 5e7858254SMatt Roper 6e7858254SMatt Roper #ifndef __INTEL_GT_MCR__ 7e7858254SMatt Roper #define __INTEL_GT_MCR__ 8e7858254SMatt Roper 9e7858254SMatt Roper #include "intel_gt_types.h" 10e7858254SMatt Roper 11e7858254SMatt Roper void intel_gt_mcr_init(struct intel_gt *gt); 12e7858254SMatt Roper 133fe6c7f5SMatt Roper u32 intel_gt_mcr_read(struct intel_gt *gt, 1458bc2453SMatt Roper i915_mcr_reg_t reg, 153fe6c7f5SMatt Roper int group, int instance); 1658bc2453SMatt Roper u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg); 1758bc2453SMatt Roper u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg); 183fe6c7f5SMatt Roper 193fe6c7f5SMatt Roper void intel_gt_mcr_unicast_write(struct intel_gt *gt, 2058bc2453SMatt Roper i915_mcr_reg_t reg, u32 value, 213fe6c7f5SMatt Roper int group, int instance); 223fe6c7f5SMatt Roper void intel_gt_mcr_multicast_write(struct intel_gt *gt, 2358bc2453SMatt Roper i915_mcr_reg_t reg, u32 value); 243fe6c7f5SMatt Roper void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, 2558bc2453SMatt Roper i915_mcr_reg_t reg, u32 value); 26e7858254SMatt Roper 2758bc2453SMatt Roper u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg, 28851435ecSMatt Roper u32 clear, u32 set); 29851435ecSMatt Roper 303fe6c7f5SMatt Roper void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, 3158bc2453SMatt Roper i915_mcr_reg_t reg, 323fe6c7f5SMatt Roper u8 *group, u8 *instance); 33e7858254SMatt Roper 343fe6c7f5SMatt Roper void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt, 35e7858254SMatt Roper bool dump_table); 36e7858254SMatt Roper 379a92732fSMatt Roper void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss, 389a92732fSMatt Roper unsigned int *group, unsigned int *instance); 399a92732fSMatt Roper 40*192bb40fSMatt Roper int intel_gt_mcr_wait_for_reg(struct intel_gt *gt, 4158bc2453SMatt Roper i915_mcr_reg_t reg, 423068bec8SMatt Roper u32 mask, 433068bec8SMatt Roper u32 value, 443068bec8SMatt Roper unsigned int fast_timeout_us, 453068bec8SMatt Roper unsigned int slow_timeout_ms); 463068bec8SMatt Roper 479a92732fSMatt Roper /* 489a92732fSMatt Roper * Helper for for_each_ss_steering loop. On pre-Xe_HP platforms, subslice 499a92732fSMatt Roper * presence is determined by using the group/instance as direct lookups in the 509a92732fSMatt Roper * slice/subslice topology. On Xe_HP and beyond, the steering is unrelated to 519a92732fSMatt Roper * the topology, so we lookup the DSS ID directly in "slice 0." 529a92732fSMatt Roper */ 539a92732fSMatt Roper #define _HAS_SS(ss_, gt_, group_, instance_) ( \ 549a92732fSMatt Roper GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 50) ? \ 559a92732fSMatt Roper intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \ 569a92732fSMatt Roper intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_)) 579a92732fSMatt Roper 589a92732fSMatt Roper /* 599a92732fSMatt Roper * Loop over each subslice/DSS and determine the group and instance IDs that 609a92732fSMatt Roper * should be used to steer MCR accesses toward this DSS. 619a92732fSMatt Roper */ 629a92732fSMatt Roper #define for_each_ss_steering(ss_, gt_, group_, instance_) \ 639a92732fSMatt Roper for (ss_ = 0, intel_gt_mcr_get_ss_steering(gt_, 0, &group_, &instance_); \ 649a92732fSMatt Roper ss_ < I915_MAX_SS_FUSE_BITS; \ 659a92732fSMatt Roper ss_++, intel_gt_mcr_get_ss_steering(gt_, ss_, &group_, &instance_)) \ 669a92732fSMatt Roper for_each_if(_HAS_SS(ss_, gt_, group_, instance_)) 679a92732fSMatt Roper 68e7858254SMatt Roper #endif /* __INTEL_GT_MCR__ */ 69