1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 8 #include "intel_gt_mcr.h" 9 #include "intel_gt_regs.h" 10 11 /** 12 * DOC: GT Multicast/Replicated (MCR) Register Support 13 * 14 * Some GT registers are designed as "multicast" or "replicated" registers: 15 * multiple instances of the same register share a single MMIO offset. MCR 16 * registers are generally used when the hardware needs to potentially track 17 * independent values of a register per hardware unit (e.g., per-subslice, 18 * per-L3bank, etc.). The specific types of replication that exist vary 19 * per-platform. 20 * 21 * MMIO accesses to MCR registers are controlled according to the settings 22 * programmed in the platform's MCR_SELECTOR register(s). MMIO writes to MCR 23 * registers can be done in either a (i.e., a single write updates all 24 * instances of the register to the same value) or unicast (a write updates only 25 * one specific instance). Reads of MCR registers always operate in a unicast 26 * manner regardless of how the multicast/unicast bit is set in MCR_SELECTOR. 27 * Selection of a specific MCR instance for unicast operations is referred to 28 * as "steering." 29 * 30 * If MCR register operations are steered toward a hardware unit that is 31 * fused off or currently powered down due to power gating, the MMIO operation 32 * is "terminated" by the hardware. Terminated read operations will return a 33 * value of zero and terminated unicast write operations will be silently 34 * ignored. 35 */ 36 37 #define HAS_MSLICE_STEERING(dev_priv) (INTEL_INFO(dev_priv)->has_mslice_steering) 38 39 static const char * const intel_steering_types[] = { 40 "L3BANK", 41 "MSLICE", 42 "LNCF", 43 "GAM", 44 "DSS", 45 "OADDRM", 46 "INSTANCE 0", 47 }; 48 49 static const struct intel_mmio_range icl_l3bank_steering_table[] = { 50 { 0x00B100, 0x00B3FF }, 51 {}, 52 }; 53 54 /* 55 * Although the bspec lists more "MSLICE" ranges than shown here, some of those 56 * are of a "GAM" subclass that has special rules. Thus we use a separate 57 * GAM table farther down for those. 58 */ 59 static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = { 60 { 0x00DD00, 0x00DDFF }, 61 { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */ 62 {}, 63 }; 64 65 static const struct intel_mmio_range xehpsdv_gam_steering_table[] = { 66 { 0x004000, 0x004AFF }, 67 { 0x00C800, 0x00CFFF }, 68 {}, 69 }; 70 71 static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = { 72 { 0x00B000, 0x00B0FF }, 73 { 0x00D800, 0x00D8FF }, 74 {}, 75 }; 76 77 static const struct intel_mmio_range dg2_lncf_steering_table[] = { 78 { 0x00B000, 0x00B0FF }, 79 { 0x00D880, 0x00D8FF }, 80 {}, 81 }; 82 83 /* 84 * We have several types of MCR registers on PVC where steering to (0,0) 85 * will always provide us with a non-terminated value. We'll stick them 86 * all in the same table for simplicity. 87 */ 88 static const struct intel_mmio_range pvc_instance0_steering_table[] = { 89 { 0x004000, 0x004AFF }, /* HALF-BSLICE */ 90 { 0x008800, 0x00887F }, /* CC */ 91 { 0x008A80, 0x008AFF }, /* TILEPSMI */ 92 { 0x00B000, 0x00B0FF }, /* HALF-BSLICE */ 93 { 0x00B100, 0x00B3FF }, /* L3BANK */ 94 { 0x00C800, 0x00CFFF }, /* HALF-BSLICE */ 95 { 0x00D800, 0x00D8FF }, /* HALF-BSLICE */ 96 { 0x00DD00, 0x00DDFF }, /* BSLICE */ 97 { 0x00E900, 0x00E9FF }, /* HALF-BSLICE */ 98 { 0x00EC00, 0x00EEFF }, /* HALF-BSLICE */ 99 { 0x00F000, 0x00FFFF }, /* HALF-BSLICE */ 100 { 0x024180, 0x0241FF }, /* HALF-BSLICE */ 101 {}, 102 }; 103 104 static const struct intel_mmio_range xelpg_instance0_steering_table[] = { 105 { 0x000B00, 0x000BFF }, /* SQIDI */ 106 { 0x001000, 0x001FFF }, /* SQIDI */ 107 { 0x004000, 0x0048FF }, /* GAM */ 108 { 0x008700, 0x0087FF }, /* SQIDI */ 109 { 0x00B000, 0x00B0FF }, /* NODE */ 110 { 0x00C800, 0x00CFFF }, /* GAM */ 111 { 0x00D880, 0x00D8FF }, /* NODE */ 112 { 0x00DD00, 0x00DDFF }, /* OAAL2 */ 113 {}, 114 }; 115 116 static const struct intel_mmio_range xelpg_l3bank_steering_table[] = { 117 { 0x00B100, 0x00B3FF }, 118 {}, 119 }; 120 121 /* DSS steering is used for SLICE ranges as well */ 122 static const struct intel_mmio_range xelpg_dss_steering_table[] = { 123 { 0x005200, 0x0052FF }, /* SLICE */ 124 { 0x005500, 0x007FFF }, /* SLICE */ 125 { 0x008140, 0x00815F }, /* SLICE (0x8140-0x814F), DSS (0x8150-0x815F) */ 126 { 0x0094D0, 0x00955F }, /* SLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */ 127 { 0x009680, 0x0096FF }, /* DSS */ 128 { 0x00D800, 0x00D87F }, /* SLICE */ 129 { 0x00DC00, 0x00DCFF }, /* SLICE */ 130 { 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */ 131 {}, 132 }; 133 134 static const struct intel_mmio_range xelpmp_oaddrm_steering_table[] = { 135 { 0x393200, 0x39323F }, 136 { 0x393400, 0x3934FF }, 137 {}, 138 }; 139 140 void intel_gt_mcr_init(struct intel_gt *gt) 141 { 142 struct drm_i915_private *i915 = gt->i915; 143 unsigned long fuse; 144 int i; 145 146 /* 147 * An mslice is unavailable only if both the meml3 for the slice is 148 * disabled *and* all of the DSS in the slice (quadrant) are disabled. 149 */ 150 if (HAS_MSLICE_STEERING(i915)) { 151 gt->info.mslice_mask = 152 intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask, 153 GEN_DSS_PER_MSLICE); 154 gt->info.mslice_mask |= 155 (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & 156 GEN12_MEML3_EN_MASK); 157 158 if (!gt->info.mslice_mask) /* should be impossible! */ 159 drm_warn(&i915->drm, "mslice mask all zero!\n"); 160 } 161 162 if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) { 163 gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table; 164 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { 165 fuse = REG_FIELD_GET(GT_L3_EXC_MASK, 166 intel_uncore_read(gt->uncore, XEHP_FUSE4)); 167 168 /* 169 * Despite the register field being named "exclude mask" the 170 * bits actually represent enabled banks (two banks per bit). 171 */ 172 for_each_set_bit(i, &fuse, 3) 173 gt->info.l3bank_mask |= 0x3 << 2 * i; 174 175 gt->steering_table[INSTANCE0] = xelpg_instance0_steering_table; 176 gt->steering_table[L3BANK] = xelpg_l3bank_steering_table; 177 gt->steering_table[DSS] = xelpg_dss_steering_table; 178 } else if (IS_PONTEVECCHIO(i915)) { 179 gt->steering_table[INSTANCE0] = pvc_instance0_steering_table; 180 } else if (IS_DG2(i915)) { 181 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table; 182 gt->steering_table[LNCF] = dg2_lncf_steering_table; 183 /* 184 * No need to hook up the GAM table since it has a dedicated 185 * steering control register on DG2 and can use implicit 186 * steering. 187 */ 188 } else if (IS_XEHPSDV(i915)) { 189 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table; 190 gt->steering_table[LNCF] = xehpsdv_lncf_steering_table; 191 gt->steering_table[GAM] = xehpsdv_gam_steering_table; 192 } else if (GRAPHICS_VER(i915) >= 11 && 193 GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) { 194 gt->steering_table[L3BANK] = icl_l3bank_steering_table; 195 gt->info.l3bank_mask = 196 ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & 197 GEN10_L3BANK_MASK; 198 if (!gt->info.l3bank_mask) /* should be impossible! */ 199 drm_warn(&i915->drm, "L3 bank mask is all zero!\n"); 200 } else if (GRAPHICS_VER(i915) >= 11) { 201 /* 202 * We expect all modern platforms to have at least some 203 * type of steering that needs to be initialized. 204 */ 205 MISSING_CASE(INTEL_INFO(i915)->platform); 206 } 207 } 208 209 /* 210 * Although the rest of the driver should use MCR-specific functions to 211 * read/write MCR registers, we still use the regular intel_uncore_* functions 212 * internally to implement those, so we need a way for the functions in this 213 * file to "cast" an i915_mcr_reg_t into an i915_reg_t. 214 */ 215 static i915_reg_t mcr_reg_cast(const i915_mcr_reg_t mcr) 216 { 217 i915_reg_t r = { .reg = mcr.reg }; 218 219 return r; 220 } 221 222 /* 223 * rw_with_mcr_steering_fw - Access a register with specific MCR steering 224 * @uncore: pointer to struct intel_uncore 225 * @reg: register being accessed 226 * @rw_flag: FW_REG_READ for read access or FW_REG_WRITE for write access 227 * @group: group number (documented as "sliceid" on older platforms) 228 * @instance: instance number (documented as "subsliceid" on older platforms) 229 * @value: register value to be written (ignored for read) 230 * 231 * Return: 0 for write access. register value for read access. 232 * 233 * Caller needs to make sure the relevant forcewake wells are up. 234 */ 235 static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore, 236 i915_mcr_reg_t reg, u8 rw_flag, 237 int group, int instance, u32 value) 238 { 239 u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0; 240 241 lockdep_assert_held(&uncore->lock); 242 243 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70)) { 244 /* 245 * Always leave the hardware in multicast mode when doing reads 246 * (see comment about Wa_22013088509 below) and only change it 247 * to unicast mode when doing writes of a specific instance. 248 * 249 * No need to save old steering reg value. 250 */ 251 intel_uncore_write_fw(uncore, MTL_MCR_SELECTOR, 252 REG_FIELD_PREP(MTL_MCR_GROUPID, group) | 253 REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance) | 254 (rw_flag == FW_REG_READ ? GEN11_MCR_MULTICAST : 0)); 255 } else if (GRAPHICS_VER(uncore->i915) >= 11) { 256 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 257 mcr_ss = GEN11_MCR_SLICE(group) | GEN11_MCR_SUBSLICE(instance); 258 259 /* 260 * Wa_22013088509 261 * 262 * The setting of the multicast/unicast bit usually wouldn't 263 * matter for read operations (which always return the value 264 * from a single register instance regardless of how that bit 265 * is set), but some platforms have a workaround requiring us 266 * to remain in multicast mode for reads. There's no real 267 * downside to this, so we'll just go ahead and do so on all 268 * platforms; we'll only clear the multicast bit from the mask 269 * when exlicitly doing a write operation. 270 */ 271 if (rw_flag == FW_REG_WRITE) 272 mcr_mask |= GEN11_MCR_MULTICAST; 273 274 mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); 275 old_mcr = mcr; 276 277 mcr &= ~mcr_mask; 278 mcr |= mcr_ss; 279 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); 280 } else { 281 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 282 mcr_ss = GEN8_MCR_SLICE(group) | GEN8_MCR_SUBSLICE(instance); 283 284 mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); 285 old_mcr = mcr; 286 287 mcr &= ~mcr_mask; 288 mcr |= mcr_ss; 289 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); 290 } 291 292 if (rw_flag == FW_REG_READ) 293 val = intel_uncore_read_fw(uncore, mcr_reg_cast(reg)); 294 else 295 intel_uncore_write_fw(uncore, mcr_reg_cast(reg), value); 296 297 /* 298 * For pre-MTL platforms, we need to restore the old value of the 299 * steering control register to ensure that implicit steering continues 300 * to behave as expected. For MTL and beyond, we need only reinstate 301 * the 'multicast' bit (and only if we did a write that cleared it). 302 */ 303 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70) && rw_flag == FW_REG_WRITE) 304 intel_uncore_write_fw(uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST); 305 else if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 70)) 306 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, old_mcr); 307 308 return val; 309 } 310 311 static u32 rw_with_mcr_steering(struct intel_uncore *uncore, 312 i915_mcr_reg_t reg, u8 rw_flag, 313 int group, int instance, 314 u32 value) 315 { 316 enum forcewake_domains fw_domains; 317 u32 val; 318 319 fw_domains = intel_uncore_forcewake_for_reg(uncore, mcr_reg_cast(reg), 320 rw_flag); 321 fw_domains |= intel_uncore_forcewake_for_reg(uncore, 322 GEN8_MCR_SELECTOR, 323 FW_REG_READ | FW_REG_WRITE); 324 325 spin_lock_irq(&uncore->lock); 326 intel_uncore_forcewake_get__locked(uncore, fw_domains); 327 328 val = rw_with_mcr_steering_fw(uncore, reg, rw_flag, group, instance, value); 329 330 intel_uncore_forcewake_put__locked(uncore, fw_domains); 331 spin_unlock_irq(&uncore->lock); 332 333 return val; 334 } 335 336 /** 337 * intel_gt_mcr_read - read a specific instance of an MCR register 338 * @gt: GT structure 339 * @reg: the MCR register to read 340 * @group: the MCR group 341 * @instance: the MCR instance 342 * 343 * Returns the value read from an MCR register after steering toward a specific 344 * group/instance. 345 */ 346 u32 intel_gt_mcr_read(struct intel_gt *gt, 347 i915_mcr_reg_t reg, 348 int group, int instance) 349 { 350 return rw_with_mcr_steering(gt->uncore, reg, FW_REG_READ, group, instance, 0); 351 } 352 353 /** 354 * intel_gt_mcr_unicast_write - write a specific instance of an MCR register 355 * @gt: GT structure 356 * @reg: the MCR register to write 357 * @value: value to write 358 * @group: the MCR group 359 * @instance: the MCR instance 360 * 361 * Write an MCR register in unicast mode after steering toward a specific 362 * group/instance. 363 */ 364 void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value, 365 int group, int instance) 366 { 367 rw_with_mcr_steering(gt->uncore, reg, FW_REG_WRITE, group, instance, value); 368 } 369 370 /** 371 * intel_gt_mcr_multicast_write - write a value to all instances of an MCR register 372 * @gt: GT structure 373 * @reg: the MCR register to write 374 * @value: value to write 375 * 376 * Write an MCR register in multicast mode to update all instances. 377 */ 378 void intel_gt_mcr_multicast_write(struct intel_gt *gt, 379 i915_mcr_reg_t reg, u32 value) 380 { 381 /* 382 * Ensure we have multicast behavior, just in case some non-i915 agent 383 * left the hardware in unicast mode. 384 */ 385 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) 386 intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST); 387 388 intel_uncore_write(gt->uncore, mcr_reg_cast(reg), value); 389 } 390 391 /** 392 * intel_gt_mcr_multicast_write_fw - write a value to all instances of an MCR register 393 * @gt: GT structure 394 * @reg: the MCR register to write 395 * @value: value to write 396 * 397 * Write an MCR register in multicast mode to update all instances. This 398 * function assumes the caller is already holding any necessary forcewake 399 * domains; use intel_gt_mcr_multicast_write() in cases where forcewake should 400 * be obtained automatically. 401 */ 402 void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value) 403 { 404 /* 405 * Ensure we have multicast behavior, just in case some non-i915 agent 406 * left the hardware in unicast mode. 407 */ 408 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) 409 intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST); 410 411 intel_uncore_write_fw(gt->uncore, mcr_reg_cast(reg), value); 412 } 413 414 /** 415 * intel_gt_mcr_multicast_rmw - Performs a multicast RMW operations 416 * @gt: GT structure 417 * @reg: the MCR register to read and write 418 * @clear: bits to clear during RMW 419 * @set: bits to set during RMW 420 * 421 * Performs a read-modify-write on an MCR register in a multicast manner. 422 * This operation only makes sense on MCR registers where all instances are 423 * expected to have the same value. The read will target any non-terminated 424 * instance and the write will be applied to all instances. 425 * 426 * This function assumes the caller is already holding any necessary forcewake 427 * domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should 428 * be obtained automatically. 429 * 430 * Returns the old (unmodified) value read. 431 */ 432 u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg, 433 u32 clear, u32 set) 434 { 435 u32 val = intel_gt_mcr_read_any(gt, reg); 436 437 intel_gt_mcr_multicast_write(gt, reg, (val & ~clear) | set); 438 439 return val; 440 } 441 442 /* 443 * reg_needs_read_steering - determine whether a register read requires 444 * explicit steering 445 * @gt: GT structure 446 * @reg: the register to check steering requirements for 447 * @type: type of multicast steering to check 448 * 449 * Determines whether @reg needs explicit steering of a specific type for 450 * reads. 451 * 452 * Returns false if @reg does not belong to a register range of the given 453 * steering type, or if the default (subslice-based) steering IDs are suitable 454 * for @type steering too. 455 */ 456 static bool reg_needs_read_steering(struct intel_gt *gt, 457 i915_mcr_reg_t reg, 458 enum intel_steering_type type) 459 { 460 const u32 offset = i915_mmio_reg_offset(reg); 461 const struct intel_mmio_range *entry; 462 463 if (likely(!gt->steering_table[type])) 464 return false; 465 466 for (entry = gt->steering_table[type]; entry->end; entry++) { 467 if (offset >= entry->start && offset <= entry->end) 468 return true; 469 } 470 471 return false; 472 } 473 474 /* 475 * get_nonterminated_steering - determines valid IDs for a class of MCR steering 476 * @gt: GT structure 477 * @type: multicast register type 478 * @group: Group ID returned 479 * @instance: Instance ID returned 480 * 481 * Determines group and instance values that will steer reads of the specified 482 * MCR class to a non-terminated instance. 483 */ 484 static void get_nonterminated_steering(struct intel_gt *gt, 485 enum intel_steering_type type, 486 u8 *group, u8 *instance) 487 { 488 u32 dss; 489 490 switch (type) { 491 case L3BANK: 492 *group = 0; /* unused */ 493 *instance = __ffs(gt->info.l3bank_mask); 494 break; 495 case MSLICE: 496 GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); 497 *group = __ffs(gt->info.mslice_mask); 498 *instance = 0; /* unused */ 499 break; 500 case LNCF: 501 /* 502 * An LNCF is always present if its mslice is present, so we 503 * can safely just steer to LNCF 0 in all cases. 504 */ 505 GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); 506 *group = __ffs(gt->info.mslice_mask) << 1; 507 *instance = 0; /* unused */ 508 break; 509 case GAM: 510 *group = IS_DG2(gt->i915) ? 1 : 0; 511 *instance = 0; 512 break; 513 case DSS: 514 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); 515 *group = dss / GEN_DSS_PER_GSLICE; 516 *instance = dss % GEN_DSS_PER_GSLICE; 517 break; 518 case INSTANCE0: 519 /* 520 * There are a lot of MCR types for which instance (0, 0) 521 * will always provide a non-terminated value. 522 */ 523 *group = 0; 524 *instance = 0; 525 break; 526 case OADDRM: 527 if ((VDBOX_MASK(gt) | VEBOX_MASK(gt) | gt->info.sfc_mask) & BIT(0)) 528 *group = 0; 529 else 530 *group = 1; 531 *instance = 0; 532 break; 533 default: 534 MISSING_CASE(type); 535 *group = 0; 536 *instance = 0; 537 } 538 } 539 540 /** 541 * intel_gt_mcr_get_nonterminated_steering - find group/instance values that 542 * will steer a register to a non-terminated instance 543 * @gt: GT structure 544 * @reg: register for which the steering is required 545 * @group: return variable for group steering 546 * @instance: return variable for instance steering 547 * 548 * This function returns a group/instance pair that is guaranteed to work for 549 * read steering of the given register. Note that a value will be returned even 550 * if the register is not replicated and therefore does not actually require 551 * steering. 552 */ 553 void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, 554 i915_mcr_reg_t reg, 555 u8 *group, u8 *instance) 556 { 557 int type; 558 559 for (type = 0; type < NUM_STEERING_TYPES; type++) { 560 if (reg_needs_read_steering(gt, reg, type)) { 561 get_nonterminated_steering(gt, type, group, instance); 562 return; 563 } 564 } 565 566 *group = gt->default_steering.groupid; 567 *instance = gt->default_steering.instanceid; 568 } 569 570 /** 571 * intel_gt_mcr_read_any_fw - reads one instance of an MCR register 572 * @gt: GT structure 573 * @reg: register to read 574 * 575 * Reads a GT MCR register. The read will be steered to a non-terminated 576 * instance (i.e., one that isn't fused off or powered down by power gating). 577 * This function assumes the caller is already holding any necessary forcewake 578 * domains; use intel_gt_mcr_read_any() in cases where forcewake should be 579 * obtained automatically. 580 * 581 * Returns the value from a non-terminated instance of @reg. 582 */ 583 u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg) 584 { 585 int type; 586 u8 group, instance; 587 588 for (type = 0; type < NUM_STEERING_TYPES; type++) { 589 if (reg_needs_read_steering(gt, reg, type)) { 590 get_nonterminated_steering(gt, type, &group, &instance); 591 return rw_with_mcr_steering_fw(gt->uncore, reg, 592 FW_REG_READ, 593 group, instance, 0); 594 } 595 } 596 597 return intel_uncore_read_fw(gt->uncore, mcr_reg_cast(reg)); 598 } 599 600 /** 601 * intel_gt_mcr_read_any - reads one instance of an MCR register 602 * @gt: GT structure 603 * @reg: register to read 604 * 605 * Reads a GT MCR register. The read will be steered to a non-terminated 606 * instance (i.e., one that isn't fused off or powered down by power gating). 607 * 608 * Returns the value from a non-terminated instance of @reg. 609 */ 610 u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg) 611 { 612 int type; 613 u8 group, instance; 614 615 for (type = 0; type < NUM_STEERING_TYPES; type++) { 616 if (reg_needs_read_steering(gt, reg, type)) { 617 get_nonterminated_steering(gt, type, &group, &instance); 618 return rw_with_mcr_steering(gt->uncore, reg, 619 FW_REG_READ, 620 group, instance, 0); 621 } 622 } 623 624 return intel_uncore_read(gt->uncore, mcr_reg_cast(reg)); 625 } 626 627 static void report_steering_type(struct drm_printer *p, 628 struct intel_gt *gt, 629 enum intel_steering_type type, 630 bool dump_table) 631 { 632 const struct intel_mmio_range *entry; 633 u8 group, instance; 634 635 BUILD_BUG_ON(ARRAY_SIZE(intel_steering_types) != NUM_STEERING_TYPES); 636 637 if (!gt->steering_table[type]) { 638 drm_printf(p, "%s steering: uses default steering\n", 639 intel_steering_types[type]); 640 return; 641 } 642 643 get_nonterminated_steering(gt, type, &group, &instance); 644 drm_printf(p, "%s steering: group=0x%x, instance=0x%x\n", 645 intel_steering_types[type], group, instance); 646 647 if (!dump_table) 648 return; 649 650 for (entry = gt->steering_table[type]; entry->end; entry++) 651 drm_printf(p, "\t0x%06x - 0x%06x\n", entry->start, entry->end); 652 } 653 654 void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt, 655 bool dump_table) 656 { 657 /* 658 * Starting with MTL we no longer have default steering; 659 * all ranges are explicitly steered. 660 */ 661 if (GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)) 662 drm_printf(p, "Default steering: group=0x%x, instance=0x%x\n", 663 gt->default_steering.groupid, 664 gt->default_steering.instanceid); 665 666 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { 667 for (int i = 0; i < NUM_STEERING_TYPES; i++) 668 if (gt->steering_table[i]) 669 report_steering_type(p, gt, i, dump_table); 670 } else if (IS_PONTEVECCHIO(gt->i915)) { 671 report_steering_type(p, gt, INSTANCE0, dump_table); 672 } else if (HAS_MSLICE_STEERING(gt->i915)) { 673 report_steering_type(p, gt, MSLICE, dump_table); 674 report_steering_type(p, gt, LNCF, dump_table); 675 } 676 } 677 678 /** 679 * intel_gt_mcr_get_ss_steering - returns the group/instance steering for a SS 680 * @gt: GT structure 681 * @dss: DSS ID to obtain steering for 682 * @group: pointer to storage for steering group ID 683 * @instance: pointer to storage for steering instance ID 684 * 685 * Returns the steering IDs (via the @group and @instance parameters) that 686 * correspond to a specific subslice/DSS ID. 687 */ 688 void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss, 689 unsigned int *group, unsigned int *instance) 690 { 691 if (IS_PONTEVECCHIO(gt->i915)) { 692 *group = dss / GEN_DSS_PER_CSLICE; 693 *instance = dss % GEN_DSS_PER_CSLICE; 694 } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) { 695 *group = dss / GEN_DSS_PER_GSLICE; 696 *instance = dss % GEN_DSS_PER_GSLICE; 697 } else { 698 *group = dss / GEN_MAX_SS_PER_HSW_SLICE; 699 *instance = dss % GEN_MAX_SS_PER_HSW_SLICE; 700 return; 701 } 702 } 703 704 /** 705 * intel_gt_mcr_wait_for_reg - wait until MCR register matches expected state 706 * @gt: GT structure 707 * @reg: the register to read 708 * @mask: mask to apply to register value 709 * @value: value to wait for 710 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait 711 * @slow_timeout_ms: slow timeout in millisecond 712 * 713 * This routine waits until the target register @reg contains the expected 714 * @value after applying the @mask, i.e. it waits until :: 715 * 716 * (intel_gt_mcr_read_any_fw(gt, reg) & mask) == value 717 * 718 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds. 719 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us 720 * must be not larger than 20,0000 microseconds. 721 * 722 * This function is basically an MCR-friendly version of 723 * __intel_wait_for_register_fw(). Generally this function will only be used 724 * on GAM registers which are a bit special --- although they're MCR registers, 725 * reads (e.g., waiting for status updates) are always directed to the primary 726 * instance. 727 * 728 * Note that this routine assumes the caller holds forcewake asserted, it is 729 * not suitable for very long waits. 730 * 731 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. 732 */ 733 int intel_gt_mcr_wait_for_reg(struct intel_gt *gt, 734 i915_mcr_reg_t reg, 735 u32 mask, 736 u32 value, 737 unsigned int fast_timeout_us, 738 unsigned int slow_timeout_ms) 739 { 740 int ret; 741 742 lockdep_assert_not_held(>->uncore->lock); 743 744 #define done ((intel_gt_mcr_read_any(gt, reg) & mask) == value) 745 746 /* Catch any overuse of this function */ 747 might_sleep_if(slow_timeout_ms); 748 GEM_BUG_ON(fast_timeout_us > 20000); 749 GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms); 750 751 ret = -ETIMEDOUT; 752 if (fast_timeout_us && fast_timeout_us <= 20000) 753 ret = _wait_for_atomic(done, fast_timeout_us, 0); 754 if (ret && slow_timeout_ms) 755 ret = wait_for(done, slow_timeout_ms); 756 757 return ret; 758 #undef done 759 } 760