1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/sched/clock.h> 7 8 #include "i915_drv.h" 9 #include "i915_irq.h" 10 #include "intel_breadcrumbs.h" 11 #include "intel_gt.h" 12 #include "intel_gt_irq.h" 13 #include "intel_gt_print.h" 14 #include "intel_gt_regs.h" 15 #include "intel_uncore.h" 16 #include "intel_rps.h" 17 #include "pxp/intel_pxp_irq.h" 18 #include "uc/intel_gsc_proxy.h" 19 20 static void guc_irq_handler(struct intel_guc *guc, u16 iir) 21 { 22 if (unlikely(!guc->interrupts.enabled)) 23 return; 24 25 if (iir & GUC_INTR_GUC2HOST) 26 intel_guc_to_host_event_handler(guc); 27 } 28 29 static u32 30 gen11_gt_engine_identity(struct intel_gt *gt, 31 const unsigned int bank, const unsigned int bit) 32 { 33 void __iomem * const regs = gt->uncore->regs; 34 u32 timeout_ts; 35 u32 ident; 36 37 lockdep_assert_held(gt->irq_lock); 38 39 raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit)); 40 41 /* 42 * NB: Specs do not specify how long to spin wait, 43 * so we do ~100us as an educated guess. 44 */ 45 timeout_ts = (local_clock() >> 10) + 100; 46 do { 47 ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank)); 48 } while (!(ident & GEN11_INTR_DATA_VALID) && 49 !time_after32(local_clock() >> 10, timeout_ts)); 50 51 if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) { 52 gt_err(gt, "INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n", 53 bank, bit, ident); 54 return 0; 55 } 56 57 raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank), 58 GEN11_INTR_DATA_VALID); 59 60 return ident; 61 } 62 63 static void 64 gen11_other_irq_handler(struct intel_gt *gt, const u8 instance, 65 const u16 iir) 66 { 67 struct intel_gt *media_gt = gt->i915->media_gt; 68 69 if (instance == OTHER_GUC_INSTANCE) 70 return guc_irq_handler(>->uc.guc, iir); 71 if (instance == OTHER_MEDIA_GUC_INSTANCE && media_gt) 72 return guc_irq_handler(&media_gt->uc.guc, iir); 73 74 if (instance == OTHER_GTPM_INSTANCE) 75 return gen11_rps_irq_handler(>->rps, iir); 76 if (instance == OTHER_MEDIA_GTPM_INSTANCE && media_gt) 77 return gen11_rps_irq_handler(&media_gt->rps, iir); 78 79 if (instance == OTHER_KCR_INSTANCE) 80 return intel_pxp_irq_handler(gt->i915->pxp, iir); 81 82 if (instance == OTHER_GSC_INSTANCE) 83 return intel_gsc_irq_handler(gt, iir); 84 85 if (instance == OTHER_GSC_HECI_2_INSTANCE) 86 return intel_gsc_proxy_irq_handler(>->uc.gsc, iir); 87 88 WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n", 89 instance, iir); 90 } 91 92 static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance) 93 { 94 struct intel_gt *media_gt = gt->i915->media_gt; 95 96 /* we expect the non-media gt to be passed in */ 97 GEM_BUG_ON(gt == media_gt); 98 99 if (!media_gt) 100 return gt; 101 102 switch (class) { 103 case VIDEO_DECODE_CLASS: 104 case VIDEO_ENHANCEMENT_CLASS: 105 return media_gt; 106 case OTHER_CLASS: 107 if (instance == OTHER_GSC_HECI_2_INSTANCE) 108 return media_gt; 109 if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0)) 110 return media_gt; 111 fallthrough; 112 default: 113 return gt; 114 } 115 } 116 117 static void 118 gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity) 119 { 120 const u8 class = GEN11_INTR_ENGINE_CLASS(identity); 121 const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity); 122 const u16 intr = GEN11_INTR_ENGINE_INTR(identity); 123 124 if (unlikely(!intr)) 125 return; 126 127 /* 128 * Platforms with standalone media have the media and GSC engines in 129 * another GT. 130 */ 131 gt = pick_gt(gt, class, instance); 132 133 if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) { 134 struct intel_engine_cs *engine = gt->engine_class[class][instance]; 135 if (engine) 136 return intel_engine_cs_irq(engine, intr); 137 } 138 139 if (class == OTHER_CLASS) 140 return gen11_other_irq_handler(gt, instance, intr); 141 142 WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n", 143 class, instance, intr); 144 } 145 146 static void 147 gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank) 148 { 149 void __iomem * const regs = gt->uncore->regs; 150 unsigned long intr_dw; 151 unsigned int bit; 152 153 lockdep_assert_held(gt->irq_lock); 154 155 intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); 156 157 for_each_set_bit(bit, &intr_dw, 32) { 158 const u32 ident = gen11_gt_engine_identity(gt, bank, bit); 159 160 gen11_gt_identity_handler(gt, ident); 161 } 162 163 /* Clear must be after shared has been served for engine */ 164 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw); 165 } 166 167 void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl) 168 { 169 unsigned int bank; 170 171 spin_lock(gt->irq_lock); 172 173 for (bank = 0; bank < 2; bank++) { 174 if (master_ctl & GEN11_GT_DW_IRQ(bank)) 175 gen11_gt_bank_handler(gt, bank); 176 } 177 178 spin_unlock(gt->irq_lock); 179 } 180 181 bool gen11_gt_reset_one_iir(struct intel_gt *gt, 182 const unsigned int bank, const unsigned int bit) 183 { 184 void __iomem * const regs = gt->uncore->regs; 185 u32 dw; 186 187 lockdep_assert_held(gt->irq_lock); 188 189 dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); 190 if (dw & BIT(bit)) { 191 /* 192 * According to the BSpec, DW_IIR bits cannot be cleared without 193 * first servicing the Selector & Shared IIR registers. 194 */ 195 gen11_gt_engine_identity(gt, bank, bit); 196 197 /* 198 * We locked GT INT DW by reading it. If we want to (try 199 * to) recover from this successfully, we need to clear 200 * our bit, otherwise we are locking the register for 201 * everybody. 202 */ 203 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit)); 204 205 return true; 206 } 207 208 return false; 209 } 210 211 void gen11_gt_irq_reset(struct intel_gt *gt) 212 { 213 struct intel_uncore *uncore = gt->uncore; 214 215 /* Disable RCS, BCS, VCS and VECS class engines. */ 216 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0); 217 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); 218 if (CCS_MASK(gt)) 219 intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0); 220 if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0)) 221 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0); 222 223 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ 224 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); 225 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0); 226 if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2)) 227 intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0); 228 if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4)) 229 intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0); 230 if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6)) 231 intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0); 232 if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8)) 233 intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0); 234 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0); 235 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0); 236 if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) 237 intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~0); 238 if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) 239 intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~0); 240 intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0); 241 if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) 242 intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0); 243 if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1)) 244 intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0); 245 if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) 246 intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0); 247 if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0)) 248 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0); 249 250 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); 251 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); 252 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0); 253 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0); 254 255 intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0); 256 intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0); 257 } 258 259 void gen11_gt_irq_postinstall(struct intel_gt *gt) 260 { 261 struct intel_uncore *uncore = gt->uncore; 262 u32 irqs = GT_RENDER_USER_INTERRUPT; 263 u32 guc_mask = intel_uc_wants_guc(>->uc) ? GUC_INTR_GUC2HOST : 0; 264 u32 gsc_mask = 0; 265 u32 heci_mask = 0; 266 u32 dmask; 267 u32 smask; 268 269 if (!intel_uc_wants_guc_submission(>->uc)) 270 irqs |= GT_CS_MASTER_ERROR_INTERRUPT | 271 GT_CONTEXT_SWITCH_INTERRUPT | 272 GT_WAIT_SEMAPHORE_INTERRUPT; 273 274 dmask = irqs << 16 | irqs; 275 smask = irqs << 16; 276 277 if (HAS_ENGINE(gt, GSC0)) { 278 /* 279 * the heci2 interrupt is enabled via the same register as the 280 * GSC interrupt, but it has its own mask register. 281 */ 282 gsc_mask = irqs; 283 heci_mask = GSC_IRQ_INTF(1); /* HECI2 IRQ for SW Proxy*/ 284 } else if (HAS_HECI_GSC(gt->i915)) { 285 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1); 286 } 287 288 BUILD_BUG_ON(irqs & 0xffff0000); 289 290 /* Enable RCS, BCS, VCS and VECS class interrupts. */ 291 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask); 292 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask); 293 if (CCS_MASK(gt)) 294 intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask); 295 if (gsc_mask) 296 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask | heci_mask); 297 298 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ 299 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask); 300 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask); 301 if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2)) 302 intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask); 303 if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4)) 304 intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask); 305 if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6)) 306 intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask); 307 if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8)) 308 intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask); 309 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask); 310 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask); 311 if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) 312 intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~dmask); 313 if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) 314 intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~dmask); 315 intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask); 316 if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) 317 intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask); 318 if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1)) 319 intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask); 320 if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) 321 intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask); 322 if (gsc_mask) 323 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask); 324 if (heci_mask) 325 intel_uncore_write(uncore, GEN12_HECI2_RSVD_INTR_MASK, 326 ~REG_FIELD_PREP(ENGINE1_MASK, heci_mask)); 327 328 if (guc_mask) { 329 /* the enable bit is common for both GTs but the masks are separate */ 330 u32 mask = gt->type == GT_MEDIA ? 331 REG_FIELD_PREP(ENGINE0_MASK, guc_mask) : 332 REG_FIELD_PREP(ENGINE1_MASK, guc_mask); 333 334 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 335 REG_FIELD_PREP(ENGINE1_MASK, guc_mask)); 336 337 /* we might not be the first GT to write this reg */ 338 intel_uncore_rmw(uncore, MTL_GUC_MGUC_INTR_MASK, mask, 0); 339 } 340 341 /* 342 * RPS interrupts will get enabled/disabled on demand when RPS itself 343 * is enabled/disabled. 344 */ 345 gt->pm_ier = 0x0; 346 gt->pm_imr = ~gt->pm_ier; 347 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); 348 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); 349 } 350 351 void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) 352 { 353 if (gt_iir & GT_RENDER_USER_INTERRUPT) 354 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 355 gt_iir); 356 357 if (gt_iir & ILK_BSD_USER_INTERRUPT) 358 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 359 gt_iir); 360 } 361 362 static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) 363 { 364 if (!HAS_L3_DPF(gt->i915)) 365 return; 366 367 spin_lock(gt->irq_lock); 368 gen5_gt_disable_irq(gt, GT_PARITY_ERROR(gt->i915)); 369 spin_unlock(gt->irq_lock); 370 371 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) 372 gt->i915->l3_parity.which_slice |= 1 << 1; 373 374 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) 375 gt->i915->l3_parity.which_slice |= 1 << 0; 376 377 schedule_work(>->i915->l3_parity.error_work); 378 } 379 380 void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) 381 { 382 if (gt_iir & GT_RENDER_USER_INTERRUPT) 383 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 384 gt_iir); 385 386 if (gt_iir & GT_BSD_USER_INTERRUPT) 387 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 388 gt_iir >> 12); 389 390 if (gt_iir & GT_BLT_USER_INTERRUPT) 391 intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], 392 gt_iir >> 22); 393 394 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | 395 GT_BSD_CS_ERROR_INTERRUPT | 396 GT_CS_MASTER_ERROR_INTERRUPT)) 397 gt_dbg(gt, "Command parser error, gt_iir 0x%08x\n", gt_iir); 398 399 if (gt_iir & GT_PARITY_ERROR(gt->i915)) 400 gen7_parity_error_irq_handler(gt, gt_iir); 401 } 402 403 void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl) 404 { 405 void __iomem * const regs = gt->uncore->regs; 406 u32 iir; 407 408 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { 409 iir = raw_reg_read(regs, GEN8_GT_IIR(0)); 410 if (likely(iir)) { 411 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 412 iir >> GEN8_RCS_IRQ_SHIFT); 413 intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], 414 iir >> GEN8_BCS_IRQ_SHIFT); 415 raw_reg_write(regs, GEN8_GT_IIR(0), iir); 416 } 417 } 418 419 if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) { 420 iir = raw_reg_read(regs, GEN8_GT_IIR(1)); 421 if (likely(iir)) { 422 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 423 iir >> GEN8_VCS0_IRQ_SHIFT); 424 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][1], 425 iir >> GEN8_VCS1_IRQ_SHIFT); 426 raw_reg_write(regs, GEN8_GT_IIR(1), iir); 427 } 428 } 429 430 if (master_ctl & GEN8_GT_VECS_IRQ) { 431 iir = raw_reg_read(regs, GEN8_GT_IIR(3)); 432 if (likely(iir)) { 433 intel_engine_cs_irq(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0], 434 iir >> GEN8_VECS_IRQ_SHIFT); 435 raw_reg_write(regs, GEN8_GT_IIR(3), iir); 436 } 437 } 438 439 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) { 440 iir = raw_reg_read(regs, GEN8_GT_IIR(2)); 441 if (likely(iir)) { 442 gen6_rps_irq_handler(>->rps, iir); 443 guc_irq_handler(>->uc.guc, iir >> 16); 444 raw_reg_write(regs, GEN8_GT_IIR(2), iir); 445 } 446 } 447 } 448 449 void gen8_gt_irq_reset(struct intel_gt *gt) 450 { 451 struct intel_uncore *uncore = gt->uncore; 452 453 GEN8_IRQ_RESET_NDX(uncore, GT, 0); 454 GEN8_IRQ_RESET_NDX(uncore, GT, 1); 455 GEN8_IRQ_RESET_NDX(uncore, GT, 2); 456 GEN8_IRQ_RESET_NDX(uncore, GT, 3); 457 } 458 459 void gen8_gt_irq_postinstall(struct intel_gt *gt) 460 { 461 /* These are interrupts we'll toggle with the ring mask register */ 462 const u32 irqs = 463 GT_CS_MASTER_ERROR_INTERRUPT | 464 GT_RENDER_USER_INTERRUPT | 465 GT_CONTEXT_SWITCH_INTERRUPT | 466 GT_WAIT_SEMAPHORE_INTERRUPT; 467 const u32 gt_interrupts[] = { 468 irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT, 469 irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT, 470 0, 471 irqs << GEN8_VECS_IRQ_SHIFT, 472 }; 473 struct intel_uncore *uncore = gt->uncore; 474 475 gt->pm_ier = 0x0; 476 gt->pm_imr = ~gt->pm_ier; 477 GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]); 478 GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]); 479 /* 480 * RPS interrupts will get enabled/disabled on demand when RPS itself 481 * is enabled/disabled. Same wil be the case for GuC interrupts. 482 */ 483 GEN8_IRQ_INIT_NDX(uncore, GT, 2, gt->pm_imr, gt->pm_ier); 484 GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]); 485 } 486 487 static void gen5_gt_update_irq(struct intel_gt *gt, 488 u32 interrupt_mask, 489 u32 enabled_irq_mask) 490 { 491 lockdep_assert_held(gt->irq_lock); 492 493 GEM_BUG_ON(enabled_irq_mask & ~interrupt_mask); 494 495 gt->gt_imr &= ~interrupt_mask; 496 gt->gt_imr |= (~enabled_irq_mask & interrupt_mask); 497 intel_uncore_write(gt->uncore, GTIMR, gt->gt_imr); 498 } 499 500 void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask) 501 { 502 gen5_gt_update_irq(gt, mask, mask); 503 intel_uncore_posting_read_fw(gt->uncore, GTIMR); 504 } 505 506 void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask) 507 { 508 gen5_gt_update_irq(gt, mask, 0); 509 } 510 511 void gen5_gt_irq_reset(struct intel_gt *gt) 512 { 513 struct intel_uncore *uncore = gt->uncore; 514 515 GEN3_IRQ_RESET(uncore, GT); 516 if (GRAPHICS_VER(gt->i915) >= 6) 517 GEN3_IRQ_RESET(uncore, GEN6_PM); 518 } 519 520 void gen5_gt_irq_postinstall(struct intel_gt *gt) 521 { 522 struct intel_uncore *uncore = gt->uncore; 523 u32 pm_irqs = 0; 524 u32 gt_irqs = 0; 525 526 gt->gt_imr = ~0; 527 if (HAS_L3_DPF(gt->i915)) { 528 /* L3 parity interrupt is always unmasked. */ 529 gt->gt_imr = ~GT_PARITY_ERROR(gt->i915); 530 gt_irqs |= GT_PARITY_ERROR(gt->i915); 531 } 532 533 gt_irqs |= GT_RENDER_USER_INTERRUPT; 534 if (GRAPHICS_VER(gt->i915) == 5) 535 gt_irqs |= ILK_BSD_USER_INTERRUPT; 536 else 537 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; 538 539 GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs); 540 541 if (GRAPHICS_VER(gt->i915) >= 6) { 542 /* 543 * RPS interrupts will get enabled/disabled on demand when RPS 544 * itself is enabled/disabled. 545 */ 546 if (HAS_ENGINE(gt, VECS0)) { 547 pm_irqs |= PM_VEBOX_USER_INTERRUPT; 548 gt->pm_ier |= PM_VEBOX_USER_INTERRUPT; 549 } 550 551 gt->pm_imr = 0xffffffff; 552 GEN3_IRQ_INIT(uncore, GEN6_PM, gt->pm_imr, pm_irqs); 553 } 554 } 555