1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/sched/clock.h> 7 8 #include "i915_drv.h" 9 #include "i915_irq.h" 10 #include "intel_breadcrumbs.h" 11 #include "intel_gt.h" 12 #include "intel_gt_irq.h" 13 #include "intel_gt_regs.h" 14 #include "intel_uncore.h" 15 #include "intel_rps.h" 16 #include "pxp/intel_pxp_irq.h" 17 18 static void guc_irq_handler(struct intel_guc *guc, u16 iir) 19 { 20 if (iir & GUC_INTR_GUC2HOST) 21 intel_guc_to_host_event_handler(guc); 22 } 23 24 static u32 25 gen11_gt_engine_identity(struct intel_gt *gt, 26 const unsigned int bank, const unsigned int bit) 27 { 28 void __iomem * const regs = gt->uncore->regs; 29 u32 timeout_ts; 30 u32 ident; 31 32 lockdep_assert_held(gt->irq_lock); 33 34 raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit)); 35 36 /* 37 * NB: Specs do not specify how long to spin wait, 38 * so we do ~100us as an educated guess. 39 */ 40 timeout_ts = (local_clock() >> 10) + 100; 41 do { 42 ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank)); 43 } while (!(ident & GEN11_INTR_DATA_VALID) && 44 !time_after32(local_clock() >> 10, timeout_ts)); 45 46 if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) { 47 DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n", 48 bank, bit, ident); 49 return 0; 50 } 51 52 raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank), 53 GEN11_INTR_DATA_VALID); 54 55 return ident; 56 } 57 58 static void 59 gen11_other_irq_handler(struct intel_gt *gt, const u8 instance, 60 const u16 iir) 61 { 62 struct intel_gt *media_gt = gt->i915->media_gt; 63 64 if (instance == OTHER_GUC_INSTANCE) 65 return guc_irq_handler(>->uc.guc, iir); 66 if (instance == OTHER_MEDIA_GUC_INSTANCE && media_gt) 67 return guc_irq_handler(&media_gt->uc.guc, iir); 68 69 if (instance == OTHER_GTPM_INSTANCE) 70 return gen11_rps_irq_handler(>->rps, iir); 71 if (instance == OTHER_MEDIA_GTPM_INSTANCE && media_gt) 72 return gen11_rps_irq_handler(&media_gt->rps, iir); 73 74 if (instance == OTHER_KCR_INSTANCE) 75 return intel_pxp_irq_handler(>->pxp, iir); 76 77 if (instance == OTHER_GSC_INSTANCE) 78 return intel_gsc_irq_handler(gt, iir); 79 80 WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n", 81 instance, iir); 82 } 83 84 static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance) 85 { 86 struct intel_gt *media_gt = gt->i915->media_gt; 87 88 /* we expect the non-media gt to be passed in */ 89 GEM_BUG_ON(gt == media_gt); 90 91 if (!media_gt) 92 return gt; 93 94 switch (class) { 95 case VIDEO_DECODE_CLASS: 96 case VIDEO_ENHANCEMENT_CLASS: 97 return media_gt; 98 case OTHER_CLASS: 99 if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0)) 100 return media_gt; 101 fallthrough; 102 default: 103 return gt; 104 } 105 } 106 107 static void 108 gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity) 109 { 110 const u8 class = GEN11_INTR_ENGINE_CLASS(identity); 111 const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity); 112 const u16 intr = GEN11_INTR_ENGINE_INTR(identity); 113 114 if (unlikely(!intr)) 115 return; 116 117 /* 118 * Platforms with standalone media have the media and GSC engines in 119 * another GT. 120 */ 121 gt = pick_gt(gt, class, instance); 122 123 if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) { 124 struct intel_engine_cs *engine = gt->engine_class[class][instance]; 125 if (engine) 126 return intel_engine_cs_irq(engine, intr); 127 } 128 129 if (class == OTHER_CLASS) 130 return gen11_other_irq_handler(gt, instance, intr); 131 132 WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n", 133 class, instance, intr); 134 } 135 136 static void 137 gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank) 138 { 139 void __iomem * const regs = gt->uncore->regs; 140 unsigned long intr_dw; 141 unsigned int bit; 142 143 lockdep_assert_held(gt->irq_lock); 144 145 intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); 146 147 for_each_set_bit(bit, &intr_dw, 32) { 148 const u32 ident = gen11_gt_engine_identity(gt, bank, bit); 149 150 gen11_gt_identity_handler(gt, ident); 151 } 152 153 /* Clear must be after shared has been served for engine */ 154 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw); 155 } 156 157 void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl) 158 { 159 unsigned int bank; 160 161 spin_lock(gt->irq_lock); 162 163 for (bank = 0; bank < 2; bank++) { 164 if (master_ctl & GEN11_GT_DW_IRQ(bank)) 165 gen11_gt_bank_handler(gt, bank); 166 } 167 168 spin_unlock(gt->irq_lock); 169 } 170 171 bool gen11_gt_reset_one_iir(struct intel_gt *gt, 172 const unsigned int bank, const unsigned int bit) 173 { 174 void __iomem * const regs = gt->uncore->regs; 175 u32 dw; 176 177 lockdep_assert_held(gt->irq_lock); 178 179 dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); 180 if (dw & BIT(bit)) { 181 /* 182 * According to the BSpec, DW_IIR bits cannot be cleared without 183 * first servicing the Selector & Shared IIR registers. 184 */ 185 gen11_gt_engine_identity(gt, bank, bit); 186 187 /* 188 * We locked GT INT DW by reading it. If we want to (try 189 * to) recover from this successfully, we need to clear 190 * our bit, otherwise we are locking the register for 191 * everybody. 192 */ 193 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit)); 194 195 return true; 196 } 197 198 return false; 199 } 200 201 void gen11_gt_irq_reset(struct intel_gt *gt) 202 { 203 struct intel_uncore *uncore = gt->uncore; 204 205 /* Disable RCS, BCS, VCS and VECS class engines. */ 206 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0); 207 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); 208 if (CCS_MASK(gt)) 209 intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0); 210 if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0)) 211 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0); 212 213 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ 214 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); 215 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0); 216 if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2)) 217 intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0); 218 if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4)) 219 intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0); 220 if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6)) 221 intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0); 222 if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8)) 223 intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0); 224 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0); 225 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0); 226 if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) 227 intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~0); 228 if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) 229 intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~0); 230 intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0); 231 if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) 232 intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0); 233 if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1)) 234 intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0); 235 if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) 236 intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0); 237 if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0)) 238 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0); 239 240 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); 241 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); 242 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0); 243 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0); 244 245 intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0); 246 intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0); 247 } 248 249 void gen11_gt_irq_postinstall(struct intel_gt *gt) 250 { 251 struct intel_uncore *uncore = gt->uncore; 252 u32 irqs = GT_RENDER_USER_INTERRUPT; 253 u32 gsc_mask = 0; 254 u32 dmask; 255 u32 smask; 256 257 if (!intel_uc_wants_guc_submission(>->uc)) 258 irqs |= GT_CS_MASTER_ERROR_INTERRUPT | 259 GT_CONTEXT_SWITCH_INTERRUPT | 260 GT_WAIT_SEMAPHORE_INTERRUPT; 261 262 dmask = irqs << 16 | irqs; 263 smask = irqs << 16; 264 265 if (HAS_ENGINE(gt, GSC0)) 266 gsc_mask = irqs; 267 else if (HAS_HECI_GSC(gt->i915)) 268 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1); 269 270 BUILD_BUG_ON(irqs & 0xffff0000); 271 272 /* Enable RCS, BCS, VCS and VECS class interrupts. */ 273 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask); 274 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask); 275 if (CCS_MASK(gt)) 276 intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask); 277 if (gsc_mask) 278 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask); 279 280 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ 281 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask); 282 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask); 283 if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2)) 284 intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask); 285 if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4)) 286 intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask); 287 if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6)) 288 intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask); 289 if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8)) 290 intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask); 291 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask); 292 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask); 293 if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) 294 intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~dmask); 295 if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) 296 intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~dmask); 297 intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask); 298 if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) 299 intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask); 300 if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1)) 301 intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask); 302 if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) 303 intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask); 304 if (gsc_mask) 305 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask); 306 307 /* 308 * RPS interrupts will get enabled/disabled on demand when RPS itself 309 * is enabled/disabled. 310 */ 311 gt->pm_ier = 0x0; 312 gt->pm_imr = ~gt->pm_ier; 313 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); 314 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); 315 316 /* Same thing for GuC interrupts */ 317 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0); 318 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0); 319 } 320 321 void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) 322 { 323 if (gt_iir & GT_RENDER_USER_INTERRUPT) 324 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 325 gt_iir); 326 327 if (gt_iir & ILK_BSD_USER_INTERRUPT) 328 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 329 gt_iir); 330 } 331 332 static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) 333 { 334 if (!HAS_L3_DPF(gt->i915)) 335 return; 336 337 spin_lock(gt->irq_lock); 338 gen5_gt_disable_irq(gt, GT_PARITY_ERROR(gt->i915)); 339 spin_unlock(gt->irq_lock); 340 341 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) 342 gt->i915->l3_parity.which_slice |= 1 << 1; 343 344 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) 345 gt->i915->l3_parity.which_slice |= 1 << 0; 346 347 schedule_work(>->i915->l3_parity.error_work); 348 } 349 350 void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) 351 { 352 if (gt_iir & GT_RENDER_USER_INTERRUPT) 353 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 354 gt_iir); 355 356 if (gt_iir & GT_BSD_USER_INTERRUPT) 357 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 358 gt_iir >> 12); 359 360 if (gt_iir & GT_BLT_USER_INTERRUPT) 361 intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], 362 gt_iir >> 22); 363 364 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | 365 GT_BSD_CS_ERROR_INTERRUPT | 366 GT_CS_MASTER_ERROR_INTERRUPT)) 367 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); 368 369 if (gt_iir & GT_PARITY_ERROR(gt->i915)) 370 gen7_parity_error_irq_handler(gt, gt_iir); 371 } 372 373 void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl) 374 { 375 void __iomem * const regs = gt->uncore->regs; 376 u32 iir; 377 378 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { 379 iir = raw_reg_read(regs, GEN8_GT_IIR(0)); 380 if (likely(iir)) { 381 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 382 iir >> GEN8_RCS_IRQ_SHIFT); 383 intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], 384 iir >> GEN8_BCS_IRQ_SHIFT); 385 raw_reg_write(regs, GEN8_GT_IIR(0), iir); 386 } 387 } 388 389 if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) { 390 iir = raw_reg_read(regs, GEN8_GT_IIR(1)); 391 if (likely(iir)) { 392 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 393 iir >> GEN8_VCS0_IRQ_SHIFT); 394 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][1], 395 iir >> GEN8_VCS1_IRQ_SHIFT); 396 raw_reg_write(regs, GEN8_GT_IIR(1), iir); 397 } 398 } 399 400 if (master_ctl & GEN8_GT_VECS_IRQ) { 401 iir = raw_reg_read(regs, GEN8_GT_IIR(3)); 402 if (likely(iir)) { 403 intel_engine_cs_irq(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0], 404 iir >> GEN8_VECS_IRQ_SHIFT); 405 raw_reg_write(regs, GEN8_GT_IIR(3), iir); 406 } 407 } 408 409 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) { 410 iir = raw_reg_read(regs, GEN8_GT_IIR(2)); 411 if (likely(iir)) { 412 gen6_rps_irq_handler(>->rps, iir); 413 guc_irq_handler(>->uc.guc, iir >> 16); 414 raw_reg_write(regs, GEN8_GT_IIR(2), iir); 415 } 416 } 417 } 418 419 void gen8_gt_irq_reset(struct intel_gt *gt) 420 { 421 struct intel_uncore *uncore = gt->uncore; 422 423 GEN8_IRQ_RESET_NDX(uncore, GT, 0); 424 GEN8_IRQ_RESET_NDX(uncore, GT, 1); 425 GEN8_IRQ_RESET_NDX(uncore, GT, 2); 426 GEN8_IRQ_RESET_NDX(uncore, GT, 3); 427 } 428 429 void gen8_gt_irq_postinstall(struct intel_gt *gt) 430 { 431 /* These are interrupts we'll toggle with the ring mask register */ 432 const u32 irqs = 433 GT_CS_MASTER_ERROR_INTERRUPT | 434 GT_RENDER_USER_INTERRUPT | 435 GT_CONTEXT_SWITCH_INTERRUPT | 436 GT_WAIT_SEMAPHORE_INTERRUPT; 437 const u32 gt_interrupts[] = { 438 irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT, 439 irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT, 440 0, 441 irqs << GEN8_VECS_IRQ_SHIFT, 442 }; 443 struct intel_uncore *uncore = gt->uncore; 444 445 gt->pm_ier = 0x0; 446 gt->pm_imr = ~gt->pm_ier; 447 GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]); 448 GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]); 449 /* 450 * RPS interrupts will get enabled/disabled on demand when RPS itself 451 * is enabled/disabled. Same wil be the case for GuC interrupts. 452 */ 453 GEN8_IRQ_INIT_NDX(uncore, GT, 2, gt->pm_imr, gt->pm_ier); 454 GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]); 455 } 456 457 static void gen5_gt_update_irq(struct intel_gt *gt, 458 u32 interrupt_mask, 459 u32 enabled_irq_mask) 460 { 461 lockdep_assert_held(gt->irq_lock); 462 463 GEM_BUG_ON(enabled_irq_mask & ~interrupt_mask); 464 465 gt->gt_imr &= ~interrupt_mask; 466 gt->gt_imr |= (~enabled_irq_mask & interrupt_mask); 467 intel_uncore_write(gt->uncore, GTIMR, gt->gt_imr); 468 } 469 470 void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask) 471 { 472 gen5_gt_update_irq(gt, mask, mask); 473 intel_uncore_posting_read_fw(gt->uncore, GTIMR); 474 } 475 476 void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask) 477 { 478 gen5_gt_update_irq(gt, mask, 0); 479 } 480 481 void gen5_gt_irq_reset(struct intel_gt *gt) 482 { 483 struct intel_uncore *uncore = gt->uncore; 484 485 GEN3_IRQ_RESET(uncore, GT); 486 if (GRAPHICS_VER(gt->i915) >= 6) 487 GEN3_IRQ_RESET(uncore, GEN6_PM); 488 } 489 490 void gen5_gt_irq_postinstall(struct intel_gt *gt) 491 { 492 struct intel_uncore *uncore = gt->uncore; 493 u32 pm_irqs = 0; 494 u32 gt_irqs = 0; 495 496 gt->gt_imr = ~0; 497 if (HAS_L3_DPF(gt->i915)) { 498 /* L3 parity interrupt is always unmasked. */ 499 gt->gt_imr = ~GT_PARITY_ERROR(gt->i915); 500 gt_irqs |= GT_PARITY_ERROR(gt->i915); 501 } 502 503 gt_irqs |= GT_RENDER_USER_INTERRUPT; 504 if (GRAPHICS_VER(gt->i915) == 5) 505 gt_irqs |= ILK_BSD_USER_INTERRUPT; 506 else 507 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; 508 509 GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs); 510 511 if (GRAPHICS_VER(gt->i915) >= 6) { 512 /* 513 * RPS interrupts will get enabled/disabled on demand when RPS 514 * itself is enabled/disabled. 515 */ 516 if (HAS_ENGINE(gt, VECS0)) { 517 pm_irqs |= PM_VEBOX_USER_INTERRUPT; 518 gt->pm_ier |= PM_VEBOX_USER_INTERRUPT; 519 } 520 521 gt->pm_imr = 0xffffffff; 522 GEN3_IRQ_INIT(uncore, GEN6_PM, gt->pm_imr, pm_irqs); 523 } 524 } 525