1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #include <linux/sched/clock.h>
7 
8 #include "i915_drv.h"
9 #include "i915_irq.h"
10 #include "intel_breadcrumbs.h"
11 #include "intel_gt.h"
12 #include "intel_gt_irq.h"
13 #include "intel_gt_print.h"
14 #include "intel_gt_regs.h"
15 #include "intel_uncore.h"
16 #include "intel_rps.h"
17 #include "pxp/intel_pxp_irq.h"
18 
19 static void guc_irq_handler(struct intel_guc *guc, u16 iir)
20 {
21 	if (unlikely(!guc->interrupts.enabled))
22 		return;
23 
24 	if (iir & GUC_INTR_GUC2HOST)
25 		intel_guc_to_host_event_handler(guc);
26 }
27 
28 static u32
29 gen11_gt_engine_identity(struct intel_gt *gt,
30 			 const unsigned int bank, const unsigned int bit)
31 {
32 	void __iomem * const regs = gt->uncore->regs;
33 	u32 timeout_ts;
34 	u32 ident;
35 
36 	lockdep_assert_held(gt->irq_lock);
37 
38 	raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
39 
40 	/*
41 	 * NB: Specs do not specify how long to spin wait,
42 	 * so we do ~100us as an educated guess.
43 	 */
44 	timeout_ts = (local_clock() >> 10) + 100;
45 	do {
46 		ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
47 	} while (!(ident & GEN11_INTR_DATA_VALID) &&
48 		 !time_after32(local_clock() >> 10, timeout_ts));
49 
50 	if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
51 		gt_err(gt, "INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
52 		       bank, bit, ident);
53 		return 0;
54 	}
55 
56 	raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
57 		      GEN11_INTR_DATA_VALID);
58 
59 	return ident;
60 }
61 
62 static void
63 gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
64 			const u16 iir)
65 {
66 	struct intel_gt *media_gt = gt->i915->media_gt;
67 
68 	if (instance == OTHER_GUC_INSTANCE)
69 		return guc_irq_handler(&gt->uc.guc, iir);
70 	if (instance == OTHER_MEDIA_GUC_INSTANCE && media_gt)
71 		return guc_irq_handler(&media_gt->uc.guc, iir);
72 
73 	if (instance == OTHER_GTPM_INSTANCE)
74 		return gen11_rps_irq_handler(&gt->rps, iir);
75 	if (instance == OTHER_MEDIA_GTPM_INSTANCE && media_gt)
76 		return gen11_rps_irq_handler(&media_gt->rps, iir);
77 
78 	if (instance == OTHER_KCR_INSTANCE)
79 		return intel_pxp_irq_handler(gt->i915->pxp, iir);
80 
81 	if (instance == OTHER_GSC_INSTANCE)
82 		return intel_gsc_irq_handler(gt, iir);
83 
84 	WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
85 		  instance, iir);
86 }
87 
88 static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)
89 {
90 	struct intel_gt *media_gt = gt->i915->media_gt;
91 
92 	/* we expect the non-media gt to be passed in */
93 	GEM_BUG_ON(gt == media_gt);
94 
95 	if (!media_gt)
96 		return gt;
97 
98 	switch (class) {
99 	case VIDEO_DECODE_CLASS:
100 	case VIDEO_ENHANCEMENT_CLASS:
101 		return media_gt;
102 	case OTHER_CLASS:
103 		if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
104 			return media_gt;
105 		fallthrough;
106 	default:
107 		return gt;
108 	}
109 }
110 
111 static void
112 gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
113 {
114 	const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
115 	const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
116 	const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
117 
118 	if (unlikely(!intr))
119 		return;
120 
121 	/*
122 	 * Platforms with standalone media have the media and GSC engines in
123 	 * another GT.
124 	 */
125 	gt = pick_gt(gt, class, instance);
126 
127 	if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) {
128 		struct intel_engine_cs *engine = gt->engine_class[class][instance];
129 		if (engine)
130 			return intel_engine_cs_irq(engine, intr);
131 	}
132 
133 	if (class == OTHER_CLASS)
134 		return gen11_other_irq_handler(gt, instance, intr);
135 
136 	WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
137 		  class, instance, intr);
138 }
139 
140 static void
141 gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank)
142 {
143 	void __iomem * const regs = gt->uncore->regs;
144 	unsigned long intr_dw;
145 	unsigned int bit;
146 
147 	lockdep_assert_held(gt->irq_lock);
148 
149 	intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
150 
151 	for_each_set_bit(bit, &intr_dw, 32) {
152 		const u32 ident = gen11_gt_engine_identity(gt, bank, bit);
153 
154 		gen11_gt_identity_handler(gt, ident);
155 	}
156 
157 	/* Clear must be after shared has been served for engine */
158 	raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
159 }
160 
161 void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl)
162 {
163 	unsigned int bank;
164 
165 	spin_lock(gt->irq_lock);
166 
167 	for (bank = 0; bank < 2; bank++) {
168 		if (master_ctl & GEN11_GT_DW_IRQ(bank))
169 			gen11_gt_bank_handler(gt, bank);
170 	}
171 
172 	spin_unlock(gt->irq_lock);
173 }
174 
175 bool gen11_gt_reset_one_iir(struct intel_gt *gt,
176 			    const unsigned int bank, const unsigned int bit)
177 {
178 	void __iomem * const regs = gt->uncore->regs;
179 	u32 dw;
180 
181 	lockdep_assert_held(gt->irq_lock);
182 
183 	dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
184 	if (dw & BIT(bit)) {
185 		/*
186 		 * According to the BSpec, DW_IIR bits cannot be cleared without
187 		 * first servicing the Selector & Shared IIR registers.
188 		 */
189 		gen11_gt_engine_identity(gt, bank, bit);
190 
191 		/*
192 		 * We locked GT INT DW by reading it. If we want to (try
193 		 * to) recover from this successfully, we need to clear
194 		 * our bit, otherwise we are locking the register for
195 		 * everybody.
196 		 */
197 		raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
198 
199 		return true;
200 	}
201 
202 	return false;
203 }
204 
205 void gen11_gt_irq_reset(struct intel_gt *gt)
206 {
207 	struct intel_uncore *uncore = gt->uncore;
208 
209 	/* Disable RCS, BCS, VCS and VECS class engines. */
210 	intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
211 	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE,	  0);
212 	if (CCS_MASK(gt))
213 		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
214 	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
215 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
216 
217 	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
218 	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK,	~0);
219 	intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK,	~0);
220 	if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
221 		intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
222 	if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
223 		intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
224 	if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
225 		intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
226 	if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
227 		intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
228 	intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK,	~0);
229 	intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK,	~0);
230 	if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
231 		intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK,   ~0);
232 	if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
233 		intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK,   ~0);
234 	intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK,	~0);
235 	if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
236 		intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0);
237 	if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
238 		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
239 	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
240 		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
241 	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
242 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
243 
244 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
245 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
246 	intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
247 	intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK,  ~0);
248 
249 	intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
250 	intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK,  ~0);
251 }
252 
253 void gen11_gt_irq_postinstall(struct intel_gt *gt)
254 {
255 	struct intel_uncore *uncore = gt->uncore;
256 	u32 irqs = GT_RENDER_USER_INTERRUPT;
257 	u32 guc_mask = intel_uc_wants_guc(&gt->uc) ? GUC_INTR_GUC2HOST : 0;
258 	u32 gsc_mask = 0;
259 	u32 dmask;
260 	u32 smask;
261 
262 	if (!intel_uc_wants_guc_submission(&gt->uc))
263 		irqs |= GT_CS_MASTER_ERROR_INTERRUPT |
264 			GT_CONTEXT_SWITCH_INTERRUPT |
265 			GT_WAIT_SEMAPHORE_INTERRUPT;
266 
267 	dmask = irqs << 16 | irqs;
268 	smask = irqs << 16;
269 
270 	if (HAS_ENGINE(gt, GSC0))
271 		gsc_mask = irqs;
272 	else if (HAS_HECI_GSC(gt->i915))
273 		gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
274 
275 	BUILD_BUG_ON(irqs & 0xffff0000);
276 
277 	/* Enable RCS, BCS, VCS and VECS class interrupts. */
278 	intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask);
279 	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
280 	if (CCS_MASK(gt))
281 		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
282 	if (gsc_mask)
283 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask);
284 
285 	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
286 	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
287 	intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask);
288 	if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
289 		intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
290 	if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
291 		intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
292 	if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
293 		intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
294 	if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
295 		intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
296 	intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask);
297 	intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask);
298 	if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
299 		intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~dmask);
300 	if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
301 		intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~dmask);
302 	intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);
303 	if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
304 		intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask);
305 	if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
306 		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
307 	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
308 		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
309 	if (gsc_mask)
310 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
311 
312 	if (guc_mask) {
313 		/* the enable bit is common for both GTs but the masks are separate */
314 		u32 mask = gt->type == GT_MEDIA ?
315 			REG_FIELD_PREP(ENGINE0_MASK, guc_mask) :
316 			REG_FIELD_PREP(ENGINE1_MASK, guc_mask);
317 
318 		intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE,
319 				   REG_FIELD_PREP(ENGINE1_MASK, guc_mask));
320 
321 		/* we might not be the first GT to write this reg */
322 		intel_uncore_rmw(uncore, MTL_GUC_MGUC_INTR_MASK, mask, 0);
323 	}
324 
325 	/*
326 	 * RPS interrupts will get enabled/disabled on demand when RPS itself
327 	 * is enabled/disabled.
328 	 */
329 	gt->pm_ier = 0x0;
330 	gt->pm_imr = ~gt->pm_ier;
331 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
332 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
333 }
334 
335 void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
336 {
337 	if (gt_iir & GT_RENDER_USER_INTERRUPT)
338 		intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],
339 				    gt_iir);
340 
341 	if (gt_iir & ILK_BSD_USER_INTERRUPT)
342 		intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],
343 				    gt_iir);
344 }
345 
346 static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir)
347 {
348 	if (!HAS_L3_DPF(gt->i915))
349 		return;
350 
351 	spin_lock(gt->irq_lock);
352 	gen5_gt_disable_irq(gt, GT_PARITY_ERROR(gt->i915));
353 	spin_unlock(gt->irq_lock);
354 
355 	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
356 		gt->i915->l3_parity.which_slice |= 1 << 1;
357 
358 	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
359 		gt->i915->l3_parity.which_slice |= 1 << 0;
360 
361 	schedule_work(&gt->i915->l3_parity.error_work);
362 }
363 
364 void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
365 {
366 	if (gt_iir & GT_RENDER_USER_INTERRUPT)
367 		intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],
368 				    gt_iir);
369 
370 	if (gt_iir & GT_BSD_USER_INTERRUPT)
371 		intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],
372 				    gt_iir >> 12);
373 
374 	if (gt_iir & GT_BLT_USER_INTERRUPT)
375 		intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0],
376 				    gt_iir >> 22);
377 
378 	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
379 		      GT_BSD_CS_ERROR_INTERRUPT |
380 		      GT_CS_MASTER_ERROR_INTERRUPT))
381 		gt_dbg(gt, "Command parser error, gt_iir 0x%08x\n", gt_iir);
382 
383 	if (gt_iir & GT_PARITY_ERROR(gt->i915))
384 		gen7_parity_error_irq_handler(gt, gt_iir);
385 }
386 
387 void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)
388 {
389 	void __iomem * const regs = gt->uncore->regs;
390 	u32 iir;
391 
392 	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
393 		iir = raw_reg_read(regs, GEN8_GT_IIR(0));
394 		if (likely(iir)) {
395 			intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],
396 					    iir >> GEN8_RCS_IRQ_SHIFT);
397 			intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0],
398 					    iir >> GEN8_BCS_IRQ_SHIFT);
399 			raw_reg_write(regs, GEN8_GT_IIR(0), iir);
400 		}
401 	}
402 
403 	if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
404 		iir = raw_reg_read(regs, GEN8_GT_IIR(1));
405 		if (likely(iir)) {
406 			intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],
407 					    iir >> GEN8_VCS0_IRQ_SHIFT);
408 			intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][1],
409 					    iir >> GEN8_VCS1_IRQ_SHIFT);
410 			raw_reg_write(regs, GEN8_GT_IIR(1), iir);
411 		}
412 	}
413 
414 	if (master_ctl & GEN8_GT_VECS_IRQ) {
415 		iir = raw_reg_read(regs, GEN8_GT_IIR(3));
416 		if (likely(iir)) {
417 			intel_engine_cs_irq(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
418 					    iir >> GEN8_VECS_IRQ_SHIFT);
419 			raw_reg_write(regs, GEN8_GT_IIR(3), iir);
420 		}
421 	}
422 
423 	if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
424 		iir = raw_reg_read(regs, GEN8_GT_IIR(2));
425 		if (likely(iir)) {
426 			gen6_rps_irq_handler(&gt->rps, iir);
427 			guc_irq_handler(&gt->uc.guc, iir >> 16);
428 			raw_reg_write(regs, GEN8_GT_IIR(2), iir);
429 		}
430 	}
431 }
432 
433 void gen8_gt_irq_reset(struct intel_gt *gt)
434 {
435 	struct intel_uncore *uncore = gt->uncore;
436 
437 	GEN8_IRQ_RESET_NDX(uncore, GT, 0);
438 	GEN8_IRQ_RESET_NDX(uncore, GT, 1);
439 	GEN8_IRQ_RESET_NDX(uncore, GT, 2);
440 	GEN8_IRQ_RESET_NDX(uncore, GT, 3);
441 }
442 
443 void gen8_gt_irq_postinstall(struct intel_gt *gt)
444 {
445 	/* These are interrupts we'll toggle with the ring mask register */
446 	const u32 irqs =
447 		GT_CS_MASTER_ERROR_INTERRUPT |
448 		GT_RENDER_USER_INTERRUPT |
449 		GT_CONTEXT_SWITCH_INTERRUPT |
450 		GT_WAIT_SEMAPHORE_INTERRUPT;
451 	const u32 gt_interrupts[] = {
452 		irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
453 		irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT,
454 		0,
455 		irqs << GEN8_VECS_IRQ_SHIFT,
456 	};
457 	struct intel_uncore *uncore = gt->uncore;
458 
459 	gt->pm_ier = 0x0;
460 	gt->pm_imr = ~gt->pm_ier;
461 	GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
462 	GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
463 	/*
464 	 * RPS interrupts will get enabled/disabled on demand when RPS itself
465 	 * is enabled/disabled. Same wil be the case for GuC interrupts.
466 	 */
467 	GEN8_IRQ_INIT_NDX(uncore, GT, 2, gt->pm_imr, gt->pm_ier);
468 	GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
469 }
470 
471 static void gen5_gt_update_irq(struct intel_gt *gt,
472 			       u32 interrupt_mask,
473 			       u32 enabled_irq_mask)
474 {
475 	lockdep_assert_held(gt->irq_lock);
476 
477 	GEM_BUG_ON(enabled_irq_mask & ~interrupt_mask);
478 
479 	gt->gt_imr &= ~interrupt_mask;
480 	gt->gt_imr |= (~enabled_irq_mask & interrupt_mask);
481 	intel_uncore_write(gt->uncore, GTIMR, gt->gt_imr);
482 }
483 
484 void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask)
485 {
486 	gen5_gt_update_irq(gt, mask, mask);
487 	intel_uncore_posting_read_fw(gt->uncore, GTIMR);
488 }
489 
490 void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask)
491 {
492 	gen5_gt_update_irq(gt, mask, 0);
493 }
494 
495 void gen5_gt_irq_reset(struct intel_gt *gt)
496 {
497 	struct intel_uncore *uncore = gt->uncore;
498 
499 	GEN3_IRQ_RESET(uncore, GT);
500 	if (GRAPHICS_VER(gt->i915) >= 6)
501 		GEN3_IRQ_RESET(uncore, GEN6_PM);
502 }
503 
504 void gen5_gt_irq_postinstall(struct intel_gt *gt)
505 {
506 	struct intel_uncore *uncore = gt->uncore;
507 	u32 pm_irqs = 0;
508 	u32 gt_irqs = 0;
509 
510 	gt->gt_imr = ~0;
511 	if (HAS_L3_DPF(gt->i915)) {
512 		/* L3 parity interrupt is always unmasked. */
513 		gt->gt_imr = ~GT_PARITY_ERROR(gt->i915);
514 		gt_irqs |= GT_PARITY_ERROR(gt->i915);
515 	}
516 
517 	gt_irqs |= GT_RENDER_USER_INTERRUPT;
518 	if (GRAPHICS_VER(gt->i915) == 5)
519 		gt_irqs |= ILK_BSD_USER_INTERRUPT;
520 	else
521 		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
522 
523 	GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs);
524 
525 	if (GRAPHICS_VER(gt->i915) >= 6) {
526 		/*
527 		 * RPS interrupts will get enabled/disabled on demand when RPS
528 		 * itself is enabled/disabled.
529 		 */
530 		if (HAS_ENGINE(gt, VECS0)) {
531 			pm_irqs |= PM_VEBOX_USER_INTERRUPT;
532 			gt->pm_ier |= PM_VEBOX_USER_INTERRUPT;
533 		}
534 
535 		gt->pm_imr = 0xffffffff;
536 		GEN3_IRQ_INIT(uncore, GEN6_PM, gt->pm_imr, pm_irqs);
537 	}
538 }
539