1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/sched/clock.h> 7 8 #include "i915_drv.h" 9 #include "i915_irq.h" 10 #include "intel_breadcrumbs.h" 11 #include "intel_gt.h" 12 #include "intel_gt_irq.h" 13 #include "intel_gt_print.h" 14 #include "intel_gt_regs.h" 15 #include "intel_uncore.h" 16 #include "intel_rps.h" 17 #include "pxp/intel_pxp_irq.h" 18 #include "uc/intel_gsc_proxy.h" 19 20 static void guc_irq_handler(struct intel_guc *guc, u16 iir) 21 { 22 if (unlikely(!guc->interrupts.enabled)) 23 return; 24 25 if (iir & GUC_INTR_GUC2HOST) 26 intel_guc_to_host_event_handler(guc); 27 } 28 29 static u32 30 gen11_gt_engine_identity(struct intel_gt *gt, 31 const unsigned int bank, const unsigned int bit) 32 { 33 void __iomem * const regs = gt->uncore->regs; 34 u32 timeout_ts; 35 u32 ident; 36 37 lockdep_assert_held(gt->irq_lock); 38 39 raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit)); 40 41 /* 42 * NB: Specs do not specify how long to spin wait, 43 * so we do ~100us as an educated guess. 44 */ 45 timeout_ts = (local_clock() >> 10) + 100; 46 do { 47 ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank)); 48 } while (!(ident & GEN11_INTR_DATA_VALID) && 49 !time_after32(local_clock() >> 10, timeout_ts)); 50 51 if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) { 52 gt_err(gt, "INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n", 53 bank, bit, ident); 54 return 0; 55 } 56 57 raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank), 58 GEN11_INTR_DATA_VALID); 59 60 return ident; 61 } 62 63 static void 64 gen11_other_irq_handler(struct intel_gt *gt, const u8 instance, 65 const u16 iir) 66 { 67 struct intel_gt *media_gt = gt->i915->media_gt; 68 69 if (instance == OTHER_GUC_INSTANCE) 70 return guc_irq_handler(>->uc.guc, iir); 71 if (instance == OTHER_MEDIA_GUC_INSTANCE && media_gt) 72 return guc_irq_handler(&media_gt->uc.guc, iir); 73 74 if (instance == OTHER_GTPM_INSTANCE) 75 return gen11_rps_irq_handler(>->rps, iir); 76 if (instance == OTHER_MEDIA_GTPM_INSTANCE && media_gt) 77 return gen11_rps_irq_handler(&media_gt->rps, iir); 78 79 if (instance == OTHER_KCR_INSTANCE) 80 return intel_pxp_irq_handler(gt->i915->pxp, iir); 81 82 if (instance == OTHER_GSC_INSTANCE) 83 return intel_gsc_irq_handler(gt, iir); 84 85 if (instance == OTHER_GSC_HECI_2_INSTANCE) 86 return intel_gsc_proxy_irq_handler(>->uc.gsc, iir); 87 88 WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n", 89 instance, iir); 90 } 91 92 static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance) 93 { 94 struct intel_gt *media_gt = gt->i915->media_gt; 95 96 /* we expect the non-media gt to be passed in */ 97 GEM_BUG_ON(gt == media_gt); 98 99 if (!media_gt) 100 return gt; 101 102 switch (class) { 103 case VIDEO_DECODE_CLASS: 104 case VIDEO_ENHANCEMENT_CLASS: 105 return media_gt; 106 case OTHER_CLASS: 107 if (instance == OTHER_GSC_HECI_2_INSTANCE) 108 return media_gt; 109 if ((instance == OTHER_GSC_INSTANCE || instance == OTHER_KCR_INSTANCE) && 110 HAS_ENGINE(media_gt, GSC0)) 111 return media_gt; 112 fallthrough; 113 default: 114 return gt; 115 } 116 } 117 118 static void 119 gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity) 120 { 121 const u8 class = GEN11_INTR_ENGINE_CLASS(identity); 122 const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity); 123 const u16 intr = GEN11_INTR_ENGINE_INTR(identity); 124 125 if (unlikely(!intr)) 126 return; 127 128 /* 129 * Platforms with standalone media have the media and GSC engines in 130 * another GT. 131 */ 132 gt = pick_gt(gt, class, instance); 133 134 if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) { 135 struct intel_engine_cs *engine = gt->engine_class[class][instance]; 136 if (engine) 137 return intel_engine_cs_irq(engine, intr); 138 } 139 140 if (class == OTHER_CLASS) 141 return gen11_other_irq_handler(gt, instance, intr); 142 143 WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n", 144 class, instance, intr); 145 } 146 147 static void 148 gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank) 149 { 150 void __iomem * const regs = gt->uncore->regs; 151 unsigned long intr_dw; 152 unsigned int bit; 153 154 lockdep_assert_held(gt->irq_lock); 155 156 intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); 157 158 for_each_set_bit(bit, &intr_dw, 32) { 159 const u32 ident = gen11_gt_engine_identity(gt, bank, bit); 160 161 gen11_gt_identity_handler(gt, ident); 162 } 163 164 /* Clear must be after shared has been served for engine */ 165 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw); 166 } 167 168 void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl) 169 { 170 unsigned int bank; 171 172 spin_lock(gt->irq_lock); 173 174 for (bank = 0; bank < 2; bank++) { 175 if (master_ctl & GEN11_GT_DW_IRQ(bank)) 176 gen11_gt_bank_handler(gt, bank); 177 } 178 179 spin_unlock(gt->irq_lock); 180 } 181 182 bool gen11_gt_reset_one_iir(struct intel_gt *gt, 183 const unsigned int bank, const unsigned int bit) 184 { 185 void __iomem * const regs = gt->uncore->regs; 186 u32 dw; 187 188 lockdep_assert_held(gt->irq_lock); 189 190 dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); 191 if (dw & BIT(bit)) { 192 /* 193 * According to the BSpec, DW_IIR bits cannot be cleared without 194 * first servicing the Selector & Shared IIR registers. 195 */ 196 gen11_gt_engine_identity(gt, bank, bit); 197 198 /* 199 * We locked GT INT DW by reading it. If we want to (try 200 * to) recover from this successfully, we need to clear 201 * our bit, otherwise we are locking the register for 202 * everybody. 203 */ 204 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit)); 205 206 return true; 207 } 208 209 return false; 210 } 211 212 void gen11_gt_irq_reset(struct intel_gt *gt) 213 { 214 struct intel_uncore *uncore = gt->uncore; 215 216 /* Disable RCS, BCS, VCS and VECS class engines. */ 217 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0); 218 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); 219 if (CCS_MASK(gt)) 220 intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0); 221 if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0)) 222 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0); 223 224 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ 225 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); 226 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0); 227 if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2)) 228 intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0); 229 if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4)) 230 intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0); 231 if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6)) 232 intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0); 233 if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8)) 234 intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0); 235 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0); 236 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0); 237 if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) 238 intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~0); 239 if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) 240 intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~0); 241 intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0); 242 if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) 243 intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0); 244 if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1)) 245 intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0); 246 if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) 247 intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0); 248 if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0)) 249 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0); 250 251 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); 252 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); 253 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0); 254 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0); 255 256 intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0); 257 intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0); 258 } 259 260 void gen11_gt_irq_postinstall(struct intel_gt *gt) 261 { 262 struct intel_uncore *uncore = gt->uncore; 263 u32 irqs = GT_RENDER_USER_INTERRUPT; 264 u32 guc_mask = intel_uc_wants_guc(>->uc) ? GUC_INTR_GUC2HOST : 0; 265 u32 gsc_mask = 0; 266 u32 heci_mask = 0; 267 u32 dmask; 268 u32 smask; 269 270 if (!intel_uc_wants_guc_submission(>->uc)) 271 irqs |= GT_CS_MASTER_ERROR_INTERRUPT | 272 GT_CONTEXT_SWITCH_INTERRUPT | 273 GT_WAIT_SEMAPHORE_INTERRUPT; 274 275 dmask = irqs << 16 | irqs; 276 smask = irqs << 16; 277 278 if (HAS_ENGINE(gt, GSC0)) { 279 /* 280 * the heci2 interrupt is enabled via the same register as the 281 * GSC interrupt, but it has its own mask register. 282 */ 283 gsc_mask = irqs; 284 heci_mask = GSC_IRQ_INTF(1); /* HECI2 IRQ for SW Proxy*/ 285 } else if (HAS_HECI_GSC(gt->i915)) { 286 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1); 287 } 288 289 BUILD_BUG_ON(irqs & 0xffff0000); 290 291 /* Enable RCS, BCS, VCS and VECS class interrupts. */ 292 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask); 293 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask); 294 if (CCS_MASK(gt)) 295 intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask); 296 if (gsc_mask) 297 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask | heci_mask); 298 299 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ 300 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask); 301 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask); 302 if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2)) 303 intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask); 304 if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4)) 305 intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask); 306 if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6)) 307 intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask); 308 if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8)) 309 intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask); 310 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask); 311 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask); 312 if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) 313 intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~dmask); 314 if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) 315 intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~dmask); 316 intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask); 317 if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) 318 intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask); 319 if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1)) 320 intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask); 321 if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) 322 intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask); 323 if (gsc_mask) 324 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask); 325 if (heci_mask) 326 intel_uncore_write(uncore, GEN12_HECI2_RSVD_INTR_MASK, 327 ~REG_FIELD_PREP(ENGINE1_MASK, heci_mask)); 328 329 if (guc_mask) { 330 /* the enable bit is common for both GTs but the masks are separate */ 331 u32 mask = gt->type == GT_MEDIA ? 332 REG_FIELD_PREP(ENGINE0_MASK, guc_mask) : 333 REG_FIELD_PREP(ENGINE1_MASK, guc_mask); 334 335 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 336 REG_FIELD_PREP(ENGINE1_MASK, guc_mask)); 337 338 /* we might not be the first GT to write this reg */ 339 intel_uncore_rmw(uncore, MTL_GUC_MGUC_INTR_MASK, mask, 0); 340 } 341 342 /* 343 * RPS interrupts will get enabled/disabled on demand when RPS itself 344 * is enabled/disabled. 345 */ 346 gt->pm_ier = 0x0; 347 gt->pm_imr = ~gt->pm_ier; 348 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); 349 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); 350 } 351 352 void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) 353 { 354 if (gt_iir & GT_RENDER_USER_INTERRUPT) 355 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 356 gt_iir); 357 358 if (gt_iir & ILK_BSD_USER_INTERRUPT) 359 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 360 gt_iir); 361 } 362 363 static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) 364 { 365 if (!HAS_L3_DPF(gt->i915)) 366 return; 367 368 spin_lock(gt->irq_lock); 369 gen5_gt_disable_irq(gt, GT_PARITY_ERROR(gt->i915)); 370 spin_unlock(gt->irq_lock); 371 372 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) 373 gt->i915->l3_parity.which_slice |= 1 << 1; 374 375 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) 376 gt->i915->l3_parity.which_slice |= 1 << 0; 377 378 schedule_work(>->i915->l3_parity.error_work); 379 } 380 381 void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) 382 { 383 if (gt_iir & GT_RENDER_USER_INTERRUPT) 384 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 385 gt_iir); 386 387 if (gt_iir & GT_BSD_USER_INTERRUPT) 388 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 389 gt_iir >> 12); 390 391 if (gt_iir & GT_BLT_USER_INTERRUPT) 392 intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], 393 gt_iir >> 22); 394 395 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | 396 GT_BSD_CS_ERROR_INTERRUPT | 397 GT_CS_MASTER_ERROR_INTERRUPT)) 398 gt_dbg(gt, "Command parser error, gt_iir 0x%08x\n", gt_iir); 399 400 if (gt_iir & GT_PARITY_ERROR(gt->i915)) 401 gen7_parity_error_irq_handler(gt, gt_iir); 402 } 403 404 void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl) 405 { 406 void __iomem * const regs = gt->uncore->regs; 407 u32 iir; 408 409 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { 410 iir = raw_reg_read(regs, GEN8_GT_IIR(0)); 411 if (likely(iir)) { 412 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 413 iir >> GEN8_RCS_IRQ_SHIFT); 414 intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], 415 iir >> GEN8_BCS_IRQ_SHIFT); 416 raw_reg_write(regs, GEN8_GT_IIR(0), iir); 417 } 418 } 419 420 if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) { 421 iir = raw_reg_read(regs, GEN8_GT_IIR(1)); 422 if (likely(iir)) { 423 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 424 iir >> GEN8_VCS0_IRQ_SHIFT); 425 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][1], 426 iir >> GEN8_VCS1_IRQ_SHIFT); 427 raw_reg_write(regs, GEN8_GT_IIR(1), iir); 428 } 429 } 430 431 if (master_ctl & GEN8_GT_VECS_IRQ) { 432 iir = raw_reg_read(regs, GEN8_GT_IIR(3)); 433 if (likely(iir)) { 434 intel_engine_cs_irq(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0], 435 iir >> GEN8_VECS_IRQ_SHIFT); 436 raw_reg_write(regs, GEN8_GT_IIR(3), iir); 437 } 438 } 439 440 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) { 441 iir = raw_reg_read(regs, GEN8_GT_IIR(2)); 442 if (likely(iir)) { 443 gen6_rps_irq_handler(>->rps, iir); 444 guc_irq_handler(>->uc.guc, iir >> 16); 445 raw_reg_write(regs, GEN8_GT_IIR(2), iir); 446 } 447 } 448 } 449 450 void gen8_gt_irq_reset(struct intel_gt *gt) 451 { 452 struct intel_uncore *uncore = gt->uncore; 453 454 GEN8_IRQ_RESET_NDX(uncore, GT, 0); 455 GEN8_IRQ_RESET_NDX(uncore, GT, 1); 456 GEN8_IRQ_RESET_NDX(uncore, GT, 2); 457 GEN8_IRQ_RESET_NDX(uncore, GT, 3); 458 } 459 460 void gen8_gt_irq_postinstall(struct intel_gt *gt) 461 { 462 /* These are interrupts we'll toggle with the ring mask register */ 463 const u32 irqs = 464 GT_CS_MASTER_ERROR_INTERRUPT | 465 GT_RENDER_USER_INTERRUPT | 466 GT_CONTEXT_SWITCH_INTERRUPT | 467 GT_WAIT_SEMAPHORE_INTERRUPT; 468 const u32 gt_interrupts[] = { 469 irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT, 470 irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT, 471 0, 472 irqs << GEN8_VECS_IRQ_SHIFT, 473 }; 474 struct intel_uncore *uncore = gt->uncore; 475 476 gt->pm_ier = 0x0; 477 gt->pm_imr = ~gt->pm_ier; 478 GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]); 479 GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]); 480 /* 481 * RPS interrupts will get enabled/disabled on demand when RPS itself 482 * is enabled/disabled. Same wil be the case for GuC interrupts. 483 */ 484 GEN8_IRQ_INIT_NDX(uncore, GT, 2, gt->pm_imr, gt->pm_ier); 485 GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]); 486 } 487 488 static void gen5_gt_update_irq(struct intel_gt *gt, 489 u32 interrupt_mask, 490 u32 enabled_irq_mask) 491 { 492 lockdep_assert_held(gt->irq_lock); 493 494 GEM_BUG_ON(enabled_irq_mask & ~interrupt_mask); 495 496 gt->gt_imr &= ~interrupt_mask; 497 gt->gt_imr |= (~enabled_irq_mask & interrupt_mask); 498 intel_uncore_write(gt->uncore, GTIMR, gt->gt_imr); 499 } 500 501 void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask) 502 { 503 gen5_gt_update_irq(gt, mask, mask); 504 intel_uncore_posting_read_fw(gt->uncore, GTIMR); 505 } 506 507 void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask) 508 { 509 gen5_gt_update_irq(gt, mask, 0); 510 } 511 512 void gen5_gt_irq_reset(struct intel_gt *gt) 513 { 514 struct intel_uncore *uncore = gt->uncore; 515 516 GEN3_IRQ_RESET(uncore, GT); 517 if (GRAPHICS_VER(gt->i915) >= 6) 518 GEN3_IRQ_RESET(uncore, GEN6_PM); 519 } 520 521 void gen5_gt_irq_postinstall(struct intel_gt *gt) 522 { 523 struct intel_uncore *uncore = gt->uncore; 524 u32 pm_irqs = 0; 525 u32 gt_irqs = 0; 526 527 gt->gt_imr = ~0; 528 if (HAS_L3_DPF(gt->i915)) { 529 /* L3 parity interrupt is always unmasked. */ 530 gt->gt_imr = ~GT_PARITY_ERROR(gt->i915); 531 gt_irqs |= GT_PARITY_ERROR(gt->i915); 532 } 533 534 gt_irqs |= GT_RENDER_USER_INTERRUPT; 535 if (GRAPHICS_VER(gt->i915) == 5) 536 gt_irqs |= ILK_BSD_USER_INTERRUPT; 537 else 538 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; 539 540 GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs); 541 542 if (GRAPHICS_VER(gt->i915) >= 6) { 543 /* 544 * RPS interrupts will get enabled/disabled on demand when RPS 545 * itself is enabled/disabled. 546 */ 547 if (HAS_ENGINE(gt, VECS0)) { 548 pm_irqs |= PM_VEBOX_USER_INTERRUPT; 549 gt->pm_ier |= PM_VEBOX_USER_INTERRUPT; 550 } 551 552 gt->pm_imr = 0xffffffff; 553 GEN3_IRQ_INIT(uncore, GEN6_PM, gt->pm_imr, pm_irqs); 554 } 555 } 556