124635c51STvrtko Ursulin /* SPDX-License-Identifier: MIT */ 224635c51STvrtko Ursulin /* 324635c51STvrtko Ursulin * Copyright © 2019 Intel Corporation 424635c51STvrtko Ursulin */ 524635c51STvrtko Ursulin 624635c51STvrtko Ursulin #ifndef __INTEL_GT__ 724635c51STvrtko Ursulin #define __INTEL_GT__ 824635c51STvrtko Ursulin 9f1530f91SJonathan Cavitt #include "i915_drv.h" 10eaf522f6STvrtko Ursulin #include "intel_engine_types.h" 1124635c51STvrtko Ursulin #include "intel_gt_types.h" 12cb823ed9SChris Wilson #include "intel_reset.h" 1324635c51STvrtko Ursulin 14724e9564STvrtko Ursulin struct drm_i915_private; 15792592e7SDaniele Ceraolo Spurio struct drm_printer; 16724e9564STvrtko Ursulin 17*18e77951SMatt Roper /* 18*18e77951SMatt Roper * Check that the GT is a graphics GT and has an IP version within the 19*18e77951SMatt Roper * specified range (inclusive). 20*18e77951SMatt Roper */ 21*18e77951SMatt Roper #define IS_GFX_GT_IP_RANGE(gt, from, until) ( \ 22*18e77951SMatt Roper BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \ 23*18e77951SMatt Roper BUILD_BUG_ON_ZERO((until) < (from)) + \ 24*18e77951SMatt Roper ((gt)->type != GT_MEDIA && \ 25*18e77951SMatt Roper GRAPHICS_VER_FULL((gt)->i915) >= (from) && \ 26*18e77951SMatt Roper GRAPHICS_VER_FULL((gt)->i915) <= (until))) 27*18e77951SMatt Roper 2888405440SVenkata Sandeep Dhanalakota #define GT_TRACE(gt, fmt, ...) do { \ 2988405440SVenkata Sandeep Dhanalakota const struct intel_gt *gt__ __maybe_unused = (gt); \ 3088405440SVenkata Sandeep Dhanalakota GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \ 31639f2f24SVenkata Sandeep Dhanalakota ##__VA_ARGS__); \ 32639f2f24SVenkata Sandeep Dhanalakota } while (0) 33639f2f24SVenkata Sandeep Dhanalakota 34b9741faaSAndi Shyti static inline bool gt_is_root(struct intel_gt *gt) 35b9741faaSAndi Shyti { 36b9741faaSAndi Shyti return !gt->info.id; 37b9741faaSAndi Shyti } 38b9741faaSAndi Shyti 39f1530f91SJonathan Cavitt static inline bool intel_gt_needs_wa_22016122933(struct intel_gt *gt) 40f1530f91SJonathan Cavitt { 41f1530f91SJonathan Cavitt return MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0) && gt->type == GT_MEDIA; 42f1530f91SJonathan Cavitt } 43f1530f91SJonathan Cavitt 44ca7b2c1bSDaniele Ceraolo Spurio static inline struct intel_gt *uc_to_gt(struct intel_uc *uc) 45ca7b2c1bSDaniele Ceraolo Spurio { 46ca7b2c1bSDaniele Ceraolo Spurio return container_of(uc, struct intel_gt, uc); 47ca7b2c1bSDaniele Ceraolo Spurio } 48ca7b2c1bSDaniele Ceraolo Spurio 4984b1ca2fSDaniele Ceraolo Spurio static inline struct intel_gt *guc_to_gt(struct intel_guc *guc) 5084b1ca2fSDaniele Ceraolo Spurio { 5184b1ca2fSDaniele Ceraolo Spurio return container_of(guc, struct intel_gt, uc.guc); 5284b1ca2fSDaniele Ceraolo Spurio } 5384b1ca2fSDaniele Ceraolo Spurio 5484b1ca2fSDaniele Ceraolo Spurio static inline struct intel_gt *huc_to_gt(struct intel_huc *huc) 5584b1ca2fSDaniele Ceraolo Spurio { 5684b1ca2fSDaniele Ceraolo Spurio return container_of(huc, struct intel_gt, uc.huc); 5784b1ca2fSDaniele Ceraolo Spurio } 5884b1ca2fSDaniele Ceraolo Spurio 59242c4b91SDaniele Ceraolo Spurio static inline struct intel_gt *gsc_uc_to_gt(struct intel_gsc_uc *gsc_uc) 60242c4b91SDaniele Ceraolo Spurio { 61242c4b91SDaniele Ceraolo Spurio return container_of(gsc_uc, struct intel_gt, uc.gsc); 62242c4b91SDaniele Ceraolo Spurio } 63242c4b91SDaniele Ceraolo Spurio 641e3dc1d8STomas Winkler static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc) 651e3dc1d8STomas Winkler { 661e3dc1d8STomas Winkler return container_of(gsc, struct intel_gt, gsc); 671e3dc1d8STomas Winkler } 681e3dc1d8STomas Winkler 694ecd56fdSMatt Roper void intel_gt_common_init_early(struct intel_gt *gt); 7003d2c54dSMatt Roper int intel_root_gt_init_early(struct drm_i915_private *i915); 71cdeea858SAndi Shyti int intel_gt_assign_ggtt(struct intel_gt *gt); 72d0eb6866SDaniele Ceraolo Spurio int intel_gt_init_mmio(struct intel_gt *gt); 7361fa60ffSTvrtko Ursulin int __must_check intel_gt_init_hw(struct intel_gt *gt); 7442014f69SAndi Shyti int intel_gt_init(struct intel_gt *gt); 7542014f69SAndi Shyti void intel_gt_driver_register(struct intel_gt *gt); 7642014f69SAndi Shyti 7742014f69SAndi Shyti void intel_gt_driver_unregister(struct intel_gt *gt); 7842014f69SAndi Shyti void intel_gt_driver_remove(struct intel_gt *gt); 7942014f69SAndi Shyti void intel_gt_driver_release(struct intel_gt *gt); 80bec68cc9STvrtko Ursulin void intel_gt_driver_late_release_all(struct drm_i915_private *i915); 81cb823ed9SChris Wilson 82b97060a9SMatthew Brost int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout); 83b97060a9SMatthew Brost 84eaf522f6STvrtko Ursulin void intel_gt_check_and_clear_faults(struct intel_gt *gt); 851551b916SAshutosh Dixit i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt); 86eaf522f6STvrtko Ursulin void intel_gt_clear_error_registers(struct intel_gt *gt, 87eaf522f6STvrtko Ursulin intel_engine_mask_t engine_mask); 88eaf522f6STvrtko Ursulin 89a1c8a09eSTvrtko Ursulin void intel_gt_flush_ggtt_writes(struct intel_gt *gt); 90baea429dSTvrtko Ursulin void intel_gt_chipset_flush(struct intel_gt *gt); 91a1c8a09eSTvrtko Ursulin 9246c5847eSLionel Landwerlin static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt, 9346c5847eSLionel Landwerlin enum intel_gt_scratch_field field) 94db56f974STvrtko Ursulin { 9546c5847eSLionel Landwerlin return i915_ggtt_offset(gt->scratch) + field; 96db56f974STvrtko Ursulin } 97db56f974STvrtko Ursulin 983f04bdceSMichał Winiarski static inline bool intel_gt_has_unrecoverable_error(const struct intel_gt *gt) 99cb823ed9SChris Wilson { 1003f04bdceSMichał Winiarski return test_bit(I915_WEDGED_ON_INIT, >->reset.flags) || 1013f04bdceSMichał Winiarski test_bit(I915_WEDGED_ON_FINI, >->reset.flags); 102cb823ed9SChris Wilson } 103cb823ed9SChris Wilson 1043f04bdceSMichał Winiarski static inline bool intel_gt_is_wedged(const struct intel_gt *gt) 105b761a7b4SChris Wilson { 1063f04bdceSMichał Winiarski GEM_BUG_ON(intel_gt_has_unrecoverable_error(gt) && 1073f04bdceSMichał Winiarski !test_bit(I915_WEDGED, >->reset.flags)); 1083f04bdceSMichał Winiarski 1093f04bdceSMichał Winiarski return unlikely(test_bit(I915_WEDGED, >->reset.flags)); 110b761a7b4SChris Wilson } 111b761a7b4SChris Wilson 112bec68cc9STvrtko Ursulin int intel_gt_probe_all(struct drm_i915_private *i915); 113bec68cc9STvrtko Ursulin int intel_gt_tiles_init(struct drm_i915_private *i915); 114bec68cc9STvrtko Ursulin void intel_gt_release_all(struct drm_i915_private *i915); 115bec68cc9STvrtko Ursulin 116bec68cc9STvrtko Ursulin #define for_each_gt(gt__, i915__, id__) \ 117bec68cc9STvrtko Ursulin for ((id__) = 0; \ 118bec68cc9STvrtko Ursulin (id__) < I915_MAX_GT; \ 119bec68cc9STvrtko Ursulin (id__)++) \ 120bec68cc9STvrtko Ursulin for_each_if(((gt__) = (i915__)->gt[(id__)])) 121bec68cc9STvrtko Ursulin 122792592e7SDaniele Ceraolo Spurio void intel_gt_info_print(const struct intel_gt_info *info, 123792592e7SDaniele Ceraolo Spurio struct drm_printer *p); 124792592e7SDaniele Ceraolo Spurio 1259b4d0598STvrtko Ursulin void intel_gt_watchdog_work(struct work_struct *work); 1269b4d0598STvrtko Ursulin 127115cdccaSJonathan Cavitt enum i915_map_type intel_gt_coherent_map_type(struct intel_gt *gt, 128115cdccaSJonathan Cavitt struct drm_i915_gem_object *obj, 129115cdccaSJonathan Cavitt bool always_coherent); 130115cdccaSJonathan Cavitt 13124635c51STvrtko Ursulin #endif /* __INTEL_GT_H__ */ 132